Comment 3 for bug 1933532

Would also appreciate if this was enabled.

Have a RPi4 with 8GB that runs Rosetta (from BOINC) with idle priority. The tasks eat about 1G ram each; with 4 running there are quite a few TLB misses:

root@vadelma:~# perf stat -I 1000 -e dTLB-load-misses,dTLB-store-misses,iTLB-load-misses -a
# time counts unit events
   1.000395577 16,504,784 dTLB-load-misses
   1.000395577 1,562,981 dTLB-store-misses
   1.000395577 193,640 iTLB-load-misses
   2.001569068 18,044,238 dTLB-load-misses
   2.001569068 1,524,714 dTLB-store-misses
   2.001569068 86,710 iTLB-load-misses
   3.002516807 14,502,850 dTLB-load-misses
   3.002516807 1,527,325 dTLB-store-misses
   3.002516807 189,333 iTLB-load-misses
   4.003480550 27,343,138 dTLB-load-misses
   4.003480550 1,542,708 dTLB-store-misses
   4.003480550 118,987 iTLB-load-misses

After recompiling the kernel with transparent hugepages and enabling them:

root@vadelma:~# perf stat -I 1000 -e dTLB-load-misses,dTLB-store-misses,iTLB-load-misses -a
# time counts unit events
     1.000446250 6,559,299 dTLB-load-misses
     1.000446250 78,022 dTLB-store-misses
     1.000446250 615,533 iTLB-load-misses
     2.001771713 7,980,471 dTLB-load-misses
     2.001771713 172,949 dTLB-store-misses
     2.001771713 837,294 iTLB-load-misses
     3.002796124 6,795,584 dTLB-load-misses
     3.002796124 84,586 dTLB-store-misses
     3.002796124 760,424 iTLB-load-misses

Average TLB misses are down about 2/3 while IPC is slightly up, by 8-10%.

I'm perfectly fine if it's disabled by default, but it would be nice to not have to recompile the kernel.