Comment 7 for bug 1886165

Revision history for this message
AceLan Kao (acelankao) wrote :

below commits are in v5.9-rc1, we have to backport those commits to groovy.

09eac8277262 drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock
f153478de4b2 drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders
9fa6769952ee drm/i915/tgl: Add HBR and HBR2+ voltage swing table
84f9cbf33580 drm/i915/tgl: Implement WA_16011163337
250a353cd85f drm/i915/tgl: Update TC DP vswing table