Comment 60 for bug 893210

Table 40. Bit Mnemonic JS0 Interrupt Function JS1 TMR JS0 TMR JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0x0000

JS1INT JS0ST JS1ST JS0MD JS1MD JS0TMR JS1TMR JS0EQB JS1EQB JSMT [2:0]

JS0INT
This bit indicates that Pin JS0 has generated an interrupt. This bit remains set until the software services the JS0 interrupt, that is, JS0 ISR should clear this bit by writing a 0 to it. The interrupt to the system is an OR combination of this bit and JS1INT. The actual interrupt implementation is selected by the INTS bit (Register 0x76). It is also possible to generate a software system interrupt by writing a 1 to this bit.

Js1 Interrupt
This bit indicates that Pin JS1 has generated an interrupt. This bit remains set until the software services the JS1 interrupt, that is, JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT description for details.

JS0 State
This bit always reports the logic state of the JS0 pin.

JS1 State
This bit always reports the logic state of the JS1 pin.

JS0 Mode
This bit selects the operation mode for the JS0 pin. 0 = Jack sense mode (default). 1 = Interrupt mode.

JS1 Mode
This bit selects the operation mode for the JS1 pin. 0 = Jack sense mode (default). 1 = Interrupt mode.

JS0 Timer Enable
If this bit is set to 1, JS0 must be high for >278 ms to be recognized.

JS1 Timer Enable
If this bit is set to 1, JS1 must be high for >278 ms to be recognized.

 JS0 EQ Bypass Enable
This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 causes the EQ to be bypassed.

JS1 EQ Bypass Enable
This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 causes the EQ to be bypassed.

JS Mute Enable Selector

These three bits select and enable the jack sense muting action (see Table 41