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0e1f616
(Get the code!)
As there is no datasheet, we can only follow the patent description
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FIG. 15c is a diagrammatic block diagram of a mode register 382 of sub-buffer table 380(3) of FIG. 15b. Mode register 382 includes a check for fault flag 382(a), a had fault flag 382(b), a data format register 382(c), a read/write flag 382(d), an interrupt enable flag 382(e) and a current position register 382(f).
Based upon the current sub-buffer and information about the previous value of the current sub-buffer table the CPU can determine that the peripheral has moved on to the next data segment. CPU 210 may then update the sub-buffer table.
Current position register 382(f) is initially set by CPU 210 when the DMA channel is first established to indicate where to begin reading (or writing) data 150 from main memory 212 within the current data segment (e.g., 150(3)). During the process of retrieving data 150 from main memory 212, DMA engine 372 keeps track of the next location to be read from in the current data segment (e.g., 150(3)). The location of the next piece of data is stored in current position register 382(f). Thus, current position register 382(f) typically contains an offset address relative to the address of the current data segment (e.g., 150(3)).