Comment 42 for bug 1033299

In comment #40, I mistakenly said "we reassign 80:01.0 to an address that is under PCI0, not PCI1." I had misread the address 0xfd00000000 as 0xfd000000, but it is actually 0xfd_0000_0000, which is just after the [mem 0x80000000-0xfcffffffff] range from amd_bus.c, and is not in any of the apertures of either PCI host bridge.

I also mis-typed the boot option in comment #41. The workaround should be "pci=use_crs" (not "pcie=use_crs").

I'm planning to merge this patch, which should fix the problem:

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If all goes well, this will appear in v4.2-rc1.