Comment 4 for bug 2029382

Tinkered a bit with it...

My current problem is how to translate following from arm64 to riscv64.

ARM64: https://github.com/openbsd/src/blob/master/sys/arch/arm64/include/signal.h#L51

--------------------------------------------------
struct sigcontext {
 int __sc_unused;
 int sc_mask; /* signal mask to restore */

 unsigned long sc_sp;
 unsigned long sc_lr;
 unsigned long sc_elr;
 unsigned long sc_spsr;
 unsigned long sc_x[30];

 long sc_cookie;
};
--------------------------------------------------

In SBCL these registers are mapped / used in conjuction with the definion in

https://github.com/sbcl/sbcl/blob/master/src/runtime/arm-lispregs.h

in the files

https://github.com/sbcl/sbcl/blob/master/src/runtime/arm64-bsd-os.h#L13

--------------------------------------------------
# define OS_CONTEXT_PC(context) context->sc_elr
--------------------------------------------------

and

https://github.com/sbcl/sbcl/blob/master/src/runtime/arm64-bsd-os.c#L64

--------------------------------------------------
os_context_register_addr(os_context_t *context, int regno)
{
    switch (regno) {
        case reg_LR: return (&context->sc_lr);
        case reg_NSP: return (&context->sc_sp);
        default: return (&context->sc_x[regno]);
    }
}

....

os_context_lr_addr(os_context_t *context)
{
    return os_context_register_addr(context, reg_LR);
}

....

os_context_flags_addr(os_context_t *context)
{
    return (os_context_register_t*)(&context->sc_spsr);
}

--------------------------------------------------

Now on the RISCV side it looks like this:

RISCV64: https://github.com/openbsd/src/blob/master/sys/arch/riscv64/include/signal.h#L48

--------------------------------------------------
struct sigcontext {
 int __sc_unused;
 int sc_mask;

 __register_t sc_ra;
 __register_t sc_sp;
 __register_t sc_gp;
 __register_t sc_tp;
 __register_t sc_t[7];
 __register_t sc_s[12];
 __register_t sc_a[8];
 __register_t sc_sepc;

 /* 64 bit floats as well as integer registers */
 __register_t sc_f[32]; /* floating-point registers */
 __register_t sc_fcsr; /* floating-point control register */

 long sc_cookie;
};

--------------------------------------------------

I think I need to replace (extend ?) the arm64 specific registers with the ones used by riscv.

But how to do that and what do the registers mean at all ?

I can satisfy the compiler and even get over the warm init after commenting out some assembler call in threads.c, but many warnings and at the end an error...

//doing warm init - compilation phase
This is SBCL 2.3.7.37-70eb4eb77-WIP, an implementation of ANSI Common Lisp.
More information about SBCL is available at <http://www.sbcl.org/>.

SBCL is free software, provided as is, with absolutely no warranty.
It is mostly in the public domain; some portions are provided under
BSD-style licenses. See the CREDITS and COPYING files in the
distribution for more information.
Initial page table:
        Immobile Object Counts
 Gen layout fdefn symbol code Boxed Cons Raw Code SmMix Mixed LgRaw LgCode LgMix Waste% Alloc Trig Dirty GCs Mem-age
  6 0 0 0 0 0 462 0 1835 0 2460 0 0 0 0.4 38805808 2000000 1835 0 0.0000
Tot 0 0 0 0 0 462 0 1835 0 2460 0 0 0 0.4 38805808 [3.6% of 1073733632 max]
Missing required foreign symbol 'new_thread_trampoline_switch_stack'

Thanks for help.