Comment 1 for bug 700774

The problem there is that for some unknown reasons your kernel is flushing the iTLB through the memory-mmaped interface (which is not yet implemented) instead of using the MMUCR.TI bit.

I was actually playing with the SH4 MMU code this week-end and wrote this missing part of the code, but I was unable to test it. Your QEMU image helped me a lot, and I confirm that my code was correct.

I have just commited the patch qemu HEAD.