Comment 6 for bug 1920602
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| Philippe Mathieu-Daudé (philmd) wrote | #6 |
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0e1f616
(Get the code!)
FErr# IRQ raise since bf13bfab084 ("i386: implement IGNNE"):
Change the handling of port F0h writes and FPU exceptions to implement IGNNE.
The implementation mixes a bit what the chipset and processor do in real
hardware, but the effect is the same as what happens with actual FERR#
and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering
FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#.