On Tue, 2 Feb 2021 at 05:07, Venkatesh Srinivas
<email address hidden> wrote:
> BTW, the RISC-V MMU code _does_ get this right and the model could be
> followed by the x86 version - - something like
> https://github.com/vsrinivas/qemu/commit/1efa7dc689c4572d8fe0880ddbe44ec22f8f4348,
> (but with more compiling + working) might solve this problem and more
> closely model h/w
target/i386 is the wrong place to put the fix, though:
the abstraction layers for working with AddressSpaces need to
provide atomic operations and then under the hood do the right
thing to implement them. target-specific code shouldn't need
to manually do the translation, fish out a MemoryRegion,
check whether it's really host RAM, and so on.
On Tue, 2 Feb 2021 at 05:07, Venkatesh Srinivas /github. com/vsrinivas/ qemu/commit/ 1efa7dc689c4572 d8fe0880ddbe44e c22f8f4348,
<email address hidden> wrote:
> BTW, the RISC-V MMU code _does_ get this right and the model could be
> followed by the x86 version - - something like
> https:/
> (but with more compiling + working) might solve this problem and more
> closely model h/w
target/i386 is the wrong place to put the fix, though:
the abstraction layers for working with AddressSpaces need to
provide atomic operations and then under the hood do the right
thing to implement them. target-specific code shouldn't need
to manually do the translation, fish out a MemoryRegion,
check whether it's really host RAM, and so on.
thanks
-- PMM