Comment 11 for bug 1886318

No worries - I didn't spot that those memory regions were implemented as single-byte registers which means the access size won't matter anyway.

I had a quick look at your command line again and the only other obvious thing I spotted was that a 64-bit access to the q35 "blackhole" region might also be affected by this change in logic. Does the diff below help at all?

diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index b67cb9c29f..e703979488 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -281,8 +281,6 @@ static const MemoryRegionOps blackhole_ops = {
     .read = blackhole_read,
     .write = blackhole_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
     .impl.min_access_size = 4,
     .impl.max_access_size = 4,
     .endianness = DEVICE_LITTLE_ENDIAN,

ATB,

Mark.