QEMU

Bug #1856335
Comment #33

Comment 33 for bug 1856335

Revision history for this message

Heiko Sieger (h-sieger) wrote on 2020-07-10:

#33

@Jan: this coreinfo output looks good.

I finally managed to get the core /cache alignment right, I believe:

...
  <cpu mode="host-passthrough" check="none">
    <topology sockets="1" dies="1" cores="16" threads="2"/>
    <cache mode="passthrough"/>

The Windows Coreinfo output is this:

Logical to Physical Processor Map:
**---------------- Physical Processor 0 (Hyperthreaded)
--**-------------- Physical Processor 1 (Hyperthreaded)
----**------------ Physical Processor 2 (Hyperthreaded)
------**---------- Physical Processor 3 (Hyperthreaded)
--------**-------- Physical Processor 4 (Hyperthreaded)
----------**------ Physical Processor 5 (Hyperthreaded)
------------**---- Physical Processor 6 (Hyperthreaded)
--------------**-- Physical Processor 7 (Hyperthreaded)
----------------** Physical Processor 8 (Hyperthreaded)

Logical Processor to Socket Map:
****************** Socket 0

Logical Processor to NUMA Node Map:
****************** NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**---------------- Data Cache **---------------- Instruction Cache **---------------- Unified Cache ******------------ Unified Cache --**-------------- Data Cache --**-------------- Instruction Cache --**-------------- Unified Cache ----**------------ Data Cache ----**------------ Instruction Cache ----**------------ Unified Cache ------**---------- Data Cache ------**---------- Instruction Cache ------**---------- Unified Cache ------******------ Unified Cache --------**-------- Data Cache --------**-------- Instruction Cache --------**-------- Unified Cache ----------**------ Data Cache ----------**------ Instruction Cache ----------**------ Unified Cache ------------**---- Data Cache ------------**---- Instruction Cache ------------**---- Unified Cache ------------****** Unified Cache --------------**-- Data Cache --------------**-- Instruction Cache --------------**-- Unified Cache ----------------** Data Cache ----------------** Instruction Cache ----------------** Unified Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
0, Level 1, 32 KB, Assoc 8, LineSize 64
0, Level 2, 512 KB, Assoc 8, LineSize 64
1, Level 3, 16 MB, Assoc 16, LineSize 64
1, Level 1, 32 KB, Assoc 8, LineSize 64
1, Level 1, 32 KB, Assoc 8, LineSize 64
2, Level 2, 512 KB, Assoc 8, LineSize 64
2, Level 1, 32 KB, Assoc 8, LineSize 64
2, Level 1, 32 KB, Assoc 8, LineSize 64
3, Level 2, 512 KB, Assoc 8, LineSize 64
3, Level 1, 32 KB, Assoc 8, LineSize 64
3, Level 1, 32 KB, Assoc 8, LineSize 64
4, Level 2, 512 KB, Assoc 8, LineSize 64
5, Level 3, 16 MB, Assoc 16, LineSize 64
4, Level 1, 32 KB, Assoc 8, LineSize 64
4, Level 1, 32 KB, Assoc 8, LineSize 64
6, Level 2, 512 KB, Assoc 8, LineSize 64
5, Level 1, 32 KB, Assoc 8, LineSize 64
5, Level 1, 32 KB, Assoc 8, LineSize 64
7, Level 2, 512 KB, Assoc 8, LineSize 64
6, Level 1, 32 KB, Assoc 8, LineSize 64
6, Level 1, 32 KB, Assoc 8, LineSize 64
8, Level 2, 512 KB, Assoc 8, LineSize 64
9, Level 3, 16 MB, Assoc 16, LineSize 64
7, Level 1, 32 KB, Assoc 8, LineSize 64
7, Level 1, 32 KB, Assoc 8, LineSize 64
10, Level 2, 512 KB, Assoc 8, LineSize 64
8, Level 1, 32 KB, Assoc 8, LineSize 64
8, Level 1, 32 KB, Assoc 8, LineSize 64
11, Level 2, 512 KB, Assoc 8, LineSize 64

Logical Processor to Group Map:
****************** Group 0

Haven't been able to test if it performs as expected. Need to do that.

Of course it would be great if QEMU was patched to recognize correct CCX alignment as I'm not sure if and what will be the penalty of this weird setup.

@Jan: this coreinfo output looks good.

I finally managed to get the core /cache alignment right, I believe:

...
  <cpu mode="host-passthrough" check="none">
    <topology sockets="1" dies="1" cores="16" threads="2"/>
    <cache mode="passthrough"/>

The Windows Coreinfo output is this:

Logical to Physical Processor Map:
**----------------  Physical Processor 0 (Hyperthreaded)
--**--------------  Physical Processor 1 (Hyperthreaded)
----**------------  Physical Processor 2 (Hyperthreaded)
------**----------  Physical Processor 3 (Hyperthreaded)
--------**--------  Physical Processor 4 (Hyperthreaded)
----------**------  Physical Processor 5 (Hyperthreaded)
------------**----  Physical Processor 6 (Hyperthreaded)
--------------**--  Physical Processor 7 (Hyperthreaded)
----------------**  Physical Processor 8 (Hyperthreaded)

Logical Processor to Socket Map:
******************  Socket 0

Logical Processor to NUMA Node Map:
******************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**----------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**----------------  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**----------------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
******------------  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
--**--------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**--------------  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**--------------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
----**------------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**------------  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**------------  Unified Cache       3, Level 2,  512 KB, Assoc   8, LineSize  64
------**----------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**----------  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**----------  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
------******------  Unified Cache       5, Level 3,   16 MB, Assoc  16, LineSize  64
--------**--------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**--------  Instruction Cache   4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**--------  Unified Cache       6, Level 2,  512 KB, Assoc   8, LineSize  64
----------**------  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**------  Instruction Cache   5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**------  Unified Cache       7, Level 2,  512 KB, Assoc   8, LineSize  64
------------**----  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**----  Instruction Cache   6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**----  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
------------******  Unified Cache       9, Level 3,   16 MB, Assoc  16, LineSize  64
--------------**--  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**--  Instruction Cache   7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**--  Unified Cache      10, Level 2,  512 KB, Assoc   8, LineSize  64
----------------**  Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**  Instruction Cache   8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**  Unified Cache      11, Level 2,  512 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
******************  Group 0

Haven't been able to test if it performs as expected. Need to do that.

Of course it would be great if QEMU was patched to recognize correct CCX alignment as I'm not sure if and what will be the penalty of this weird setup.