`vsl` appears to be acting incorrectly as well, per the test 'vec_bcdsr':
=> 0x100006e0 <vec_slq+132>: vsl v0,v0,v1 (gdb) p $vr0.uint128 $21 = 0x10111213141516172021222324252650 (gdb) p $vr1.uint128 $22 = 0x0 (gdb) stepi 0x00000000100006e4 in vec_slq () 1: x/i $pc each byte => 0x100006e4 <vec_slq+136>: xxlor vs0,vs32,vs32 (gdb) p $vr0.uint128 $23 = 0x10111213141516572021222324252650
=> 0x100006e0 <vec_slq+132>: vsl v0,v0,v1 (gdb) p $vr0.uint128 $21 = 0x10111213141516172021222324252650 (gdb) p $vr1.uint128 $22 = 0x0 (gdb) stepi 0x00000000100006e4 in vec_slq () 1: x/i $pc => 0x100006e4 <vec_slq+136>: xxlor vs0,vs32,vs32 (gdb) p $vr0.uint128 $23 = 0x10111213141516172021222324252650
Note in the final result differs in the first nybble of the 8th MSB ('57' vs '17').
`vsl` appears to be acting incorrectly as well, per the test 'vec_bcdsr':
=> 0x100006e0 <vec_slq+132>: vsl v0,v0,v1 617202122232425 2650 657202122232425 2650
(gdb) p $vr0.uint128
$21 = 0x1011121314151
(gdb) p $vr1.uint128
$22 = 0x0
(gdb) stepi
0x00000000100006e4 in vec_slq ()
1: x/i $pc each byte
=> 0x100006e4 <vec_slq+136>: xxlor vs0,vs32,vs32
(gdb) p $vr0.uint128
$23 = 0x1011121314151
=> 0x100006e0 <vec_slq+132>: vsl v0,v0,v1 617202122232425 2650 617202122232425 2650
(gdb) p $vr0.uint128
$21 = 0x1011121314151
(gdb) p $vr1.uint128
$22 = 0x0
(gdb) stepi
0x00000000100006e4 in vec_slq ()
1: x/i $pc
=> 0x100006e4 <vec_slq+136>: xxlor vs0,vs32,vs32
(gdb) p $vr0.uint128
$23 = 0x1011121314151
Note in the final result differs in the first nybble of the 8th MSB ('57' vs '17').