I bisected the failure for all but the IEEE6 test to:
commit 602f6e42cfbfe9278be34e9b91d2ceb695837e02
Author: Peter Maydell <email address hidden>
Date: Thu Feb 28 10:55:16 2019 +0000
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.
This change doesn't alter behaviour for any of our CPUs.
Signed-off-by: Peter Maydell <email address hidden>
Reviewed-by: Richard Henderson <email address hidden>
Message-id: <email address hidden>
I bisected the failure for all but the IEEE6 test to:
commit 602f6e42cfbfe92 78be34e9b91d2ce b695837e02
Author: Peter Maydell <email address hidden>
Date: Thu Feb 28 10:55:16 2019 +0000
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Instead of gating the A32/T32 FP16 conversion instructions on VFP_FP16 flag, switch to our new approach of
the ARM_FEATURE_
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.
This change doesn't alter behaviour for any of our CPUs.
Signed-off-by: Peter Maydell <email address hidden>
Reviewed-by: Richard Henderson <email address hidden>
Message-id: <email address hidden>