Looks like support for this was not fully added; my apologies for closing this bug too early.
Adding full support for strong-on-weak emulation would be simple, at least when it comes to memory ordering. The slowdown would be huge though, see Figure 12 in http://www.cs.columbia.edu/~cota/pubs/cota_cgo17.pdf (i.e. ~2x hmean overhead for SPEC).
The good news is that with hardware support this overhead is ~0 (see SAO in that figure).
The other feature that is not yet implemented in upstream QEMU is the correct emulation of LL/SC, although for most code out there this shouldn't be an issue in practice given that most parallel code relies on cmpxchg, not on LL/SC pairs.
I'm reopening this bug an Cc'ing a few people who are more familiar with the current code than I am in case I missed anything.
Looks like support for this was not fully added; my apologies for closing this bug too early.
Adding full support for strong-on-weak emulation would be simple, at least when it comes to memory ordering. The slowdown would be huge though, see Figure 12 in http:// www.cs. columbia. edu/~cota/ pubs/cota_ cgo17.pdf (i.e. ~2x hmean overhead for SPEC).
The good news is that with hardware support this overhead is ~0 (see SAO in that figure).
The other feature that is not yet implemented in upstream QEMU is the correct emulation of LL/SC, although for most code out there this shouldn't be an issue in practice given that most parallel code relies on cmpxchg, not on LL/SC pairs.
I'm reopening this bug an Cc'ing a few people who are more familiar with the current code than I am in case I missed anything.