It seemed "easy" to add cortex-m7 based on cortex-m4 (copy m4 description, update ID register values), but I realized that QEMU does not support FPv5 which not only supports DP, but also adds new instructions that QEMU does not handle yet (see section A2.5 of the ARMv7-M ARM).
* Are there plans to implement them?
* If not, how difficult is it? (for a developer not very familiar with the QEMU code base)
It seemed "easy" to add cortex-m7 based on cortex-m4 (copy m4 description, update ID register values), but I realized that QEMU does not support FPv5 which not only supports DP, but also adds new instructions that QEMU does not handle yet (see section A2.5 of the ARMv7-M ARM).
* Are there plans to implement them?
* If not, how difficult is it? (for a developer not very familiar with the QEMU code base)