Comment 3 for bug 1713066

Yes, D1.13.4 is what I want, I'm not completely familiar with this part of the document.

Based on my reading of gen_load_exclusive I agree that it looks correct, and loading to a float/vector won't affect the address generation.

I have worked around this in FreeBSD my switching the order of the registers in the affected load & store, but still have an image I can test a fix with.