Comment 3 for bug 1663287

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Yongbok Kim (yongbok-kim) wrote :

Thanks for reporting this issue.
In fact, branches in a delay slot is "undefined" in the pre-Release 6 architecture.
MIPS architectre release 6 defines to signal Reserved Instruction exceptions for such cases.
However as it was undefined, it is better to signal RI and carry on rather than stopping simulation.
Hence I've made a patch for the msa case.
I will have a look into the other case. (sorry I've missed in the first place.)