Comment 1 for bug 1608802

Okay, I think there are two parts to this, and both the test case and qemu are
buggy, though perhaps the test case more seriously than qemu.

The ATA spec describes DMA commands as having two phases, preparation and
transfer. During the first phase, BSY=1,DRQ=0 is required. In the second phase,
the device can use the same status (BSY=1,DRQ=0) or switch to BSY=0,DRQ=1.
I couldn't find clear information on which state the device should be in between
receiving the ATA command and enabling the bus master operation, which is what
the test case checks, but it must be one of the two.

So the reason that the test case is buggy is that it waits for DRQ to be set,
while the spec only guarantees that either DRQ or BSY is set during the
transfer. It doesn't work on hardware that sets BSY rather than DRQ. (It also
means that the test expects the device to be in the transfer state before the
bus master is enabled.)

The problem with qemu is that it sets _both_ bits, whereas the spec requires
that only one of them is set. Apparently most drivers don't care about this as
long as any of the bits is set, but technically it's wrong.