Comment 4 for bug 1881485
Revision history for this message
| Britton Kerin (britton-kerin) wrote Re: [Bug 1881485] Re: DRC should warn about full-polys | #4 |
© 2004
Canonical Ltd.
•
Terms of use
•
Data privacy
•
Contact Launchpad Support
•
Blog
•
Careers
•
System status
•
0e1f616
(Get the code!)
On Sun, May 31, 2020 at 12:50 PM Chad Parker <email address hidden> wrote:
>
> Hi Britton-
>
> These patches have been applied in a topic branch, LP1881485 of the
> geda-project pcb repository. The test file was moved to "tests/inputs
> /drctest-
>
> Can you explain the contents of the test file? Why the thru-holes, and
> why three different polys with fullpoly set?
IIRC I was trying to determine if the mini-display that shows up in DRC
scaled in some useful way. Same with the vias. I concluded that it
doesn't since unnaturally huge vias also don't end up scaled into the
DRC finder image thingy.
> We should also add polygons that do not have the flag set, to
> demonstrate that they are not flagged.
True. I'm pretty sure I checked this on my real-life file but could be
added to the test file. The test file wasn't really intended for
commit of course.
> In preparation for some future work, I'd like to move this check to a
> separate function, and call that from the main DRC function instead of
> embedding it directly into the main function. Eventually, there will be
> a list of DRC items that can be enabled or disabled by preferences.
Sounds good.
Britton