Vias tented

[Dr M]

Vias are created tented. So far, I have not found any description in the manual of to how to change this behavior, nor any description of how to un-tent the via once it has been created. I did see a mention in a blog that there is keyboard shortcut, "k", this does not seem to work. I have been correcting this manually by editing the PCB file.

[Bert Timmerman (bert-timmerman)]

Hi,

I tried to reproduce this bug with pcb-4.0.2 (in the gtk UI).

The command MinMaskGap executed within the pcb command entry (invoked with ":") works as advertised in the manual for pins in elements.

For example ":MinMaskGap(Selected,1.0mm)" gives the result on a single selected pin inside an elemnet.

This does not work for me on a single selected via (either solo or inside a polygon, with or without thermals).

So I can confirm this bug for pcb-4.0.2.

Kind regards,

Bert Timmerman.

[Bert Timmerman (bert-timmerman)]

Hi,

This bug is getting strange ...

Searching the web I found a 9 year old mailing list thread you mentioned in your initial report (http://geda-user.delorie.narkive.com/6GluA3z7/deafult-gap-between-copper-pin-pad-and-resist).

This thread mentions hovering over the tented via and pressing [k] or [shift]+[k] for increasing/decreasing the gap ... this works for me as expected.

Invoking the "MinMaskGap(Selected,1.5mm)" command in the command entry worked too after this test, except in one instance ... and after that it resumed working.

Bug report #929123 mentions fragile code ... and it looks like that indeed.

I think this issue needs to be addressed after the pcb-4.1.0 release so I put these two reports on the pcb-4.1.1 todo list.

To be continued.

Kind regards,

Bert Timmerman.

[Dr M (drmcn)]

The "k" does not work for me.

I think I might differ in the severity. This would be a real show stopper
except for manually editing the PCB file.

On Jan 24, 2018 7:30 PM, "Bert Timmerman" <email address hidden>
wrote:

> Hi,
>
> This bug is getting strange ...
>
> Searching the web I found a 9 year old mailing list thread you mentioned
> in your initial report (http://geda-user.delorie.narkive.com/6GluA3z7
> /deafult-gap-between-copper-pin-pad-and-resist).
>
> This thread mentions hovering over the tented via and pressing [k] or
> [shift]+[k] for increasing/decreasing the gap ... this works for me as
> expected.
>
> Invoking the "MinMaskGap(Selected,1.5mm)" command in the command entry
> worked too after this test, except in one instance ... and after that it
> resumed working.
>
> Bug report #929123 mentions fragile code ... and it looks like that
> indeed.
>
> I think this issue needs to be addressed after the pcb-4.1.0 release so
> I put these two reports on the pcb-4.1.1 todo list.
>
> To be continued.
>
> Kind regards,
>
> Bert Timmerman.
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1744832
>
> Title:
> Vias tented
>
> Status in pcb:
> Confirmed
>
> Bug description:
> Vias are created tented. So far, I have not found any description in
> the manual of to how to change this behavior, nor any description of
> how to un-tent the via once it has been created. I did see a mention
> in a blog that there is keyboard shortcut, "k", this does not seem to
> work. I have been correcting this manually by editing the PCB file.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>

[Chad Parker (parker-charles)]

Dr M- What version of pcb are you using?

I'm concerned that the "k" command isn't working for you. It seems to work for Bert, and it works for me also. You may have to press it several times for the opening to be large enough.

Bert- I'm not able to get MinMaskGap(Selected, 1.5mm) to operate on the vias. I only see it operate on pins.

[Dr M (drmcn)]

The following is from the "help - about" item,

    This is PCB, an interactive
    printed circuit board editor
    version 20140316

    Compiled on Feb 11 2017 at 11:18:48

    by harry eaton

On 03/04/2018 10:47 AM, Chad Parker wrote:
> Dr M- What version of pcb are you using?
>
> I'm concerned that the "k" command isn't working for you. It seems to
> work for Bert, and it works for me also. You may have to press it
> several times for the opening to be large enough.
>
> Bert- I'm not able to get MinMaskGap(Selected, 1.5mm) to operate on the
> vias. I only see it operate on pins.
>

[Chad Parker (parker-charles)]

Dr. M-

Sorry for the delay... the last couple weeks have been rough at work.

The version of pcb you're using is quite old. Are you able to upgrade to the latest 4.1 series?

I think the real solution to this is to add solder mask clearance to the route styles.

[Chad Parker (parker-charles)]

Dr. M-

I've pushed a branch to the git repository: home/cparker/route_styles_via_sm_clearance

In this branch, the solder mask aperture can be configured using the route styles interface. You'll have to update existing vias by hand, but you should be able to create new vias with clearance you specify.

Please test if you are able.

Bert-

This branch includes a change to the file format, to add the via mask clearance to the styles string. If the clearance are all zero (default), then it uses the old format so as to be backwards compatible.

I haven't been able to test the lesstif hid yet... they updated something on my Mac and now Motif is seg faulting...

Cheers,
--Chad

[Dr M (drmcn)]

Hi Bert

Thank you for that.  Hopefully, the file format is backward compatible.
   I have a lot of python code invested in generating boards with large
arrays of sensors and amplifiers.

I have been working with the version that is provided by Fedora and
included in their collection of electronics CAD software. That they use
a version that it so wildly out of date, suggests that one of the
problems is that Fedora does not have somebody to maintain this properly
in their repositories.

So, I have to study the issue a little bit to determine how to bring in
the current version without causing a code maintenance burden with
subsequent system updates and upgrades.

Regards

Dr Mitch

On 03/18/2018 06:25 PM, Chad Parker wrote:
> Dr. M-
>
> I've pushed a branch to the git repository:
> home/cparker/route_styles_via_sm_clearance
>
> In this branch, the solder mask aperture can be configured using the
> route styles interface. You'll have to update existing vias by hand, but
> you should be able to create new vias with clearance you specify.
>
> Please test if you are able.
>
> Bert-
>
> This branch includes a change to the file format, to add the via mask
> clearance to the styles string. If the clearance are all zero (default),
> then it uses the old format so as to be backwards compatible.
>
> I haven't been able to test the lesstif hid yet... they updated
> something on my Mac and now Motif is seg faulting...
>
> Cheers,
> --Chad
>
> ** Changed in: pcb
> Status: Confirmed => In Progress
>

[Chad Parker (parker-charles)]

Dr. Mitch-

It's perfectly possible to run pcb out of the source tree. So, you can build it and test it without installing it (don't do the "make install" step. Thus, it remains entirely parallel to your existing system, and shouldn't disrupt anything.

The way I've implemented it, when a file is saved, if the all the via mask values in the styles are set to zero, then it will save in the older format. The via mask is saved as the last parameter in the styles definition, so, if your parser can handle an additional field in the line, there should be no problem. If you're using str.split(" ") to break the parameters, then your output list will just be one element longer. The order of the parameters hasn't changed, so, no existing code should break.

Thanks,
--Chad

[Dr M (drmcn)]

Okay, thank you.  I will give that a try.

On 03/25/2018 09:05 AM, Chad Parker wrote:
> Dr. Mitch-
>
> It's perfectly possible to run pcb out of the source tree. So, you can
> build it and test it without installing it (don't do the "make install"
> step. Thus, it remains entirely parallel to your existing system, and
> shouldn't disrupt anything.
>
> The way I've implemented it, when a file is saved, if the all the via
> mask values in the styles are set to zero, then it will save in the
> older format. The via mask is saved as the last parameter in the styles
> definition, so, if your parser can handle an additional field in the
> line, there should be no problem. If you're using str.split(" ") to
> break the parameters, then your output list will just be one element
> longer. The order of the parameters hasn't changed, so, no existing code
> should break.
>
> Thanks,
> --Chad
>

[Chad Parker (parker-charles)]

I started looking at why MinMaskGap wasn't working, and here's what I've found out.

There are presently two other avenues for affecting the soldermask clearance of vias.

1. ChangeClearSize
Enable the soldermask layer, select the vias you want to affect, then execute ChangeClearSize(SelectedVias, 0.5 mm) to set the soldermask clearance for all of the selected vias. Note that specifying SelectedVias will cause it to only affect vias. So, if you want to do all of them, you can just select everything on the board, and only the vias will be changed. There are other similar specifiers for other types of objects.

2. MinMaskGap
This action **only operates on vias that already have a non-zero mask gap** set. Also, this action only increases the mask gap if it's less than the specified value. If the mask is already greater than that value, the mask is not changed.

--Chad

[Chad Parker (parker-charles)]

One thing we need to decide before this fix is released is what the value in this field should actually mean. It could be:

* the absolute diameter of the aperture,
* the difference in radius between the clearance aperture and the copper ring,
* the difference in radius between the clearance aperture and the drill hole

I think the way I've implemented it presently, it's the absolute diameter of the aperture, which is the value that's stored in pcb files. Since you don't always want to have any clearance, this might make the most sense, however, it's not what I'm used to.

FWIW, polygon clearance is stored as the difference in radius between the copper ring and the aperture in the polygon. So, when you say a clearance of 20 mils, there will be 20 mils of separation between the two copper objects.

[Dr M (drmcn)]

I think I like the absolute diameter.  In general, the parameters based
on differences for pads and vias are confusing.

On 04/01/2018 01:28 PM, Chad Parker wrote:
> One thing we need to decide before this fix is released is what the
> value in this field should actually mean. It could be:
>
> * the absolute diameter of the aperture,
> * the difference in radius between the clearance aperture and the copper ring,
> * the difference in radius between the clearance aperture and the drill hole
>
> I think the way I've implemented it presently, it's the absolute
> diameter of the aperture, which is the value that's stored in pcb files.
> Since you don't always want to have any clearance, this might make the
> most sense, however, it's not what I'm used to.
>
> FWIW, polygon clearance is stored as the difference in radius between
> the copper ring and the aperture in the polygon. So, when you say a
> clearance of 20 mils, there will be 20 mils of separation between the
> two copper objects.
>

[Chad Parker (parker-charles)]

The reason I hesitate on that is the word "clearance". Maybe it's not what other people call it, but I've always called it "solder mask clearance". And the word clearance makes me think that it's a difference.

Have you been able to test out the branch?

[Dr M (drmcn)]

Sorry, not yet, very busy. I have two design mods to do, but haven't
gotten to them yet.

On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden> wrote:

> The reason I hesitate on that is the word "clearance". Maybe it's not
> what other people call it, but I've always called it "solder mask
> clearance". And the word clearance makes me think that it's a
> difference.
>
> Have you been able to test out the branch?
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1744832
>
> Title:
> Vias tented
>
> Status in pcb:
> In Progress
>
> Bug description:
> Vias are created tented. So far, I have not found any description in
> the manual of to how to change this behavior, nor any description of
> how to un-tent the via once it has been created. I did see a mention
> in a blog that there is keyboard shortcut, "k", this does not seem to
> work. I have been correcting this manually by editing the PCB file.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>

[Dr M (drmcn)]

I think I can get to it later today, will try

On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:

> Sorry, not yet, very busy. I have two design mods to do, but haven't
> gotten to them yet.
>
> On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden> wrote:
>
>> The reason I hesitate on that is the word "clearance". Maybe it's not
>> what other people call it, but I've always called it "solder mask
>> clearance". And the word clearance makes me think that it's a
>> difference.
>>
>> Have you been able to test out the branch?
>>
>> --
>> You received this bug notification because you are subscribed to the bug
>> report.
>> https://bugs.launchpad.net/bugs/1744832
>>
>> Title:
>> Vias tented
>>
>> Status in pcb:
>> In Progress
>>
>> Bug description:
>> Vias are created tented. So far, I have not found any description in
>> the manual of to how to change this behavior, nor any description of
>> how to un-tent the via once it has been created. I did see a mention
>> in a blog that there is keyboard shortcut, "k", this does not seem to
>> work. I have been correcting this manually by editing the PCB file.
>>
>> To manage notifications about this bug go to:
>> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>>
>

[Chad Parker (parker-charles)]

There's no real rush, but testing is very much appreciated :) Don't
hesitate to ask if you have any questions.

On Mon, Apr 2, 2018 at 8:35 AM, Dr M <email address hidden> wrote:

> I think I can get to it later today, will try
>
> On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:
>
> > Sorry, not yet, very busy. I have two design mods to do, but haven't
> > gotten to them yet.
> >
> > On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden>
> wrote:
> >
> >> The reason I hesitate on that is the word "clearance". Maybe it's not
> >> what other people call it, but I've always called it "solder mask
> >> clearance". And the word clearance makes me think that it's a
> >> difference.
> >>
> >> Have you been able to test out the branch?
> >>
> >> --
> >> You received this bug notification because you are subscribed to the bug
> >> report.
> >> https://bugs.launchpad.net/bugs/1744832
> >>
> >> Title:
> >> Vias tented
> >>
> >> Status in pcb:
> >> In Progress
> >>
> >> Bug description:
> >> Vias are created tented. So far, I have not found any description in
> >> the manual of to how to change this behavior, nor any description of
> >> how to un-tent the via once it has been created. I did see a mention
> >> in a blog that there is keyboard shortcut, "k", this does not seem to
> >> work. I have been correcting this manually by editing the PCB file.
> >>
> >> To manage notifications about this bug go to:
> >> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
> >>
> >
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1744832
>
> Title:
> Vias tented
>
> Status in pcb:
> In Progress
>
> Bug description:
> Vias are created tented. So far, I have not found any description in
> the manual of to how to change this behavior, nor any description of
> how to un-tent the via once it has been created. I did see a mention
> in a blog that there is keyboard shortcut, "k", this does not seem to
> work. I have been correcting this manually by editing the PCB file.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>

[Chad Parker (parker-charles)]

Have you had the opportunity to test this at all?

[Dr M (drmcn)]

Hi Chad,

I am doing some PCB designs again.  So, we are at long last testing.
Our email chain listed below.

Per your suggestion, I fetched fresh versions of geda-gaf and pcb
(version v4.1.1-g3bcbb1c6) from git and built them in my directory
tree.   I have a few designs to generate in the next few days.

The "k" function seems to work admirably well, the solder mask enlarges
and reduces (shift k) around pads and pins, without a glitch.  Its a
very nice function actually.

(The gschem program however has some serious bugs, it crashes sporadically.)

Meanwhile, I have a new question.  For a surface mount part,  which
parameter is it that I want to reduce to allow a pad to connect to a
copper "pour" on the same side as the part.  I drew the "pours" on the
top surface with the rectangle tool, but the parts have some pads have
some space around them

Thank you

Mitch

On 04/02/2018 08:58 AM, Chad Parker wrote:
> There's no real rush, but testing is very much appreciated :) Don't
> hesitate to ask if you have any questions.
>
> On Mon, Apr 2, 2018 at 8:35 AM, Dr M <email address hidden> wrote:
>
>> I think I can get to it later today, will try
>>
>> On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:
>>
>>> Sorry, not yet, very busy. I have two design mods to do, but haven't
>>> gotten to them yet.
>>>
>>> On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden>
>> wrote:
>>>> The reason I hesitate on that is the word "clearance". Maybe it's not
>>>> what other people call it, but I've always called it "solder mask
>>>> clearance". And the word clearance makes me think that it's a
>>>> difference.
>>>>
>>>> Have you been able to test out the branch?
>>>>
>>>> --
>>>> You received this bug notification because you are subscribed to the bug
>>>> report.
>>>> https://bugs.launchpad.net/bugs/1744832
>>>>
>>>> Title:
>>>> Vias tented
>>>>
>>>> Status in pcb:
>>>> In Progress
>>>>
>>>> Bug description:
>>>> Vias are created tented. So far, I have not found any description in
>>>> the manual of to how to change this behavior, nor any description of
>>>> how to un-tent the via once it has been created. I did see a mention
>>>> in a blog that there is keyboard shortcut, "k", this does not seem to
>>>> work. I have been correcting this manually by editing the PCB file.
>>>>
>>>> To manage notifications about this bug go to:
>>>> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>>>>
>> --
>> You received this bug notification because you are subscribed to the bug
>> report.
>> https://bugs.launchpad.net/bugs/1744832
>>
>> Title:
>> Vias tented
>>
>> Status in pcb:
>> In Progress
>>
>> Bug description:
>> Vias are created tented. So far, I have not found any description in
>> the manual of to how to change this behavior, nor any description of
>> how to un-tent the via once it has been created. I did see a mention
>> in a blog that there is keyboard shortcut, "k", this does not seem to
>> work. I have been correcting this manually by editing the PCB file.
>>
>> To manage notifications about this bug go to:
>> https://bugs.launchpad.net/pcb/+bug/1744832/+subscri...

[Dr M (drmcn)]

I think I figured out the answer to my question.  Is it 'ctrl-shift-k' ?

In a version where the functions are working, it really is a nice
program.  The documentation needs some work.  The recurring problem
seems to widespread use of abbreviated instructions and locally
undefined terms.

On 05/15/2018 06:01 PM, Dr M C Nelson wrote:
> Hi Chad,
>
> I am doing some PCB designs again.  So, we are at long last testing.
> Our email chain listed below.
>
> Per your suggestion, I fetched fresh versions of geda-gaf and pcb
> (version v4.1.1-g3bcbb1c6) from git and built them in my directory
> tree.   I have a few designs to generate in the next few days.
>
> The "k" function seems to work admirably well, the solder mask
> enlarges and reduces (shift k) around pads and pins, without a
> glitch.  Its a very nice function actually.
>
> (The gschem program however has some serious bugs, it crashes
> sporadically.)
>
> Meanwhile, I have a new question.  For a surface mount part, which
> parameter is it that I want to reduce to allow a pad to connect to a
> copper "pour" on the same side as the part.  I drew the "pours" on the
> top surface with the rectangle tool, but the parts have some pads have
> some space around them
>
> Thank you
>
> Mitch
>
> On 04/02/2018 08:58 AM, Chad Parker wrote:
>> There's no real rush, but testing is very much appreciated :) Don't
>> hesitate to ask if you have any questions.
>>
>> On Mon, Apr 2, 2018 at 8:35 AM, Dr M <email address hidden> wrote:
>>
>>> I think I can get to it later today, will try
>>>
>>> On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:
>>>
>>>> Sorry, not yet, very busy.  I have two design mods to do, but haven't
>>>> gotten to them yet.
>>>>
>>>> On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden>
>>> wrote:
>>>>> The reason I hesitate on that is the word "clearance". Maybe it's not
>>>>> what other people call it, but I've always called it "solder mask
>>>>> clearance". And the word clearance makes me think that it's a
>>>>> difference.
>>>>>
>>>>> Have you been able to test out the branch?
>>>>>
>>>>> --
>>>>> You received this bug notification because you are subscribed to
>>>>> the bug
>>>>> report.
>>>>> https://bugs.launchpad.net/bugs/1744832
>>>>>
>>>>> Title:
>>>>>    Vias tented
>>>>>
>>>>> Status in pcb:
>>>>>    In Progress
>>>>>
>>>>> Bug description:
>>>>>    Vias are created tented.  So far, I have not found any
>>>>> description in
>>>>>    the manual of to how to change this behavior, nor any
>>>>> description of
>>>>>    how to un-tent the via once it has been created.  I did see a
>>>>> mention
>>>>>    in a blog that there is keyboard shortcut, "k", this does not
>>>>> seem to
>>>>>    work. I have been correcting this manually by editing the PCB
>>>>> file.
>>>>>
>>>>> To manage notifications about this bug go to:
>>>>> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>>>>>
>>> --
>>> You received this bug notification because you are subscribed to the
>>> bug
>>> report.
>>> https://bugs.launchpad.net/bugs/1744832
>>>
>>> Title:
>>>    Vias tented
>>>
>>> Status in pcb:
>>>    In Progress
>>>
>>> Bug descripti...

[Chad Parker (parker-charles)]

Are you familiar with the thermal tool?

On Tue, May 15, 2018, 18:41 Dr M <email address hidden> wrote:

> I think I figured out the answer to my question. Is it 'ctrl-shift-k' ?
>
> In a version where the functions are working, it really is a nice
> program. The documentation needs some work. The recurring problem
> seems to widespread use of abbreviated instructions and locally
> undefined terms.
>
>
> On 05/15/2018 06:01 PM, Dr M C Nelson wrote:
> > Hi Chad,
> >
> > I am doing some PCB designs again. So, we are at long last testing.
> > Our email chain listed below.
> >
> > Per your suggestion, I fetched fresh versions of geda-gaf and pcb
> > (version v4.1.1-g3bcbb1c6) from git and built them in my directory
> > tree. I have a few designs to generate in the next few days.
> >
> > The "k" function seems to work admirably well, the solder mask
> > enlarges and reduces (shift k) around pads and pins, without a
> > glitch. Its a very nice function actually.
> >
> > (The gschem program however has some serious bugs, it crashes
> > sporadically.)
> >
> > Meanwhile, I have a new question. For a surface mount part, which
> > parameter is it that I want to reduce to allow a pad to connect to a
> > copper "pour" on the same side as the part. I drew the "pours" on the
> > top surface with the rectangle tool, but the parts have some pads have
> > some space around them
> >
> > Thank you
> >
> > Mitch
> >
> > On 04/02/2018 08:58 AM, Chad Parker wrote:
> >> There's no real rush, but testing is very much appreciated :) Don't
> >> hesitate to ask if you have any questions.
> >>
> >> On Mon, Apr 2, 2018 at 8:35 AM, Dr M <email address hidden>
> wrote:
> >>
> >>> I think I can get to it later today, will try
> >>>
> >>> On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:
> >>>
> >>>> Sorry, not yet, very busy. I have two design mods to do, but haven't
> >>>> gotten to them yet.
> >>>>
> >>>> On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden>
> >>> wrote:
> >>>>> The reason I hesitate on that is the word "clearance". Maybe it's not
> >>>>> what other people call it, but I've always called it "solder mask
> >>>>> clearance". And the word clearance makes me think that it's a
> >>>>> difference.
> >>>>>
> >>>>> Have you been able to test out the branch?
> >>>>>
> >>>>> --
> >>>>> You received this bug notification because you are subscribed to
> >>>>> the bug
> >>>>> report.
> >>>>> https://bugs.launchpad.net/bugs/1744832
> >>>>>
> >>>>> Title:
> >>>>> Vias tented
> >>>>>
> >>>>> Status in pcb:
> >>>>> In Progress
> >>>>>
> >>>>> Bug description:
> >>>>> Vias are created tented. So far, I have not found any
> >>>>> description in
> >>>>> the manual of to how to change this behavior, nor any
> >>>>> description of
> >>>>> how to un-tent the via once it has been created. I did see a
> >>>>> mention
> >>>>> in a blog that there is keyboard shortcut, "k", this does not
> >>>>> seem to
> >>>>> work. I have been correcting this manually by editing the PCB
> >>>>> file.
> >>>>>
> >>>>> To manage notifications about this bug go to:
> >>>>> https://bugs.launchpad.net/pcb/+bug/1744832/+subscrip...

[Dr M (drmcn)]

Yes,of course.   It did nothing.

The "pours" are drawn on the top of the board using the rectangle and
polygon tools. Its a "one layer" board.

I tried the thermal, but nothing happened.  But,  after ctl-shift-k, the
rats net shows everything is connected.

On 05/15/2018 06:47 PM, Chad Parker wrote:
> Are you familiar with the thermal tool?
>
> On Tue, May 15, 2018, 18:41 Dr M <email address hidden> wrote:
>
>> I think I figured out the answer to my question. Is it 'ctrl-shift-k' ?
>>
>> In a version where the functions are working, it really is a nice
>> program. The documentation needs some work. The recurring problem
>> seems to widespread use of abbreviated instructions and locally
>> undefined terms.
>>
>>
>> On 05/15/2018 06:01 PM, Dr M C Nelson wrote:
>>> Hi Chad,
>>>
>>> I am doing some PCB designs again. So, we are at long last testing.
>>> Our email chain listed below.
>>>
>>> Per your suggestion, I fetched fresh versions of geda-gaf and pcb
>>> (version v4.1.1-g3bcbb1c6) from git and built them in my directory
>>> tree. I have a few designs to generate in the next few days.
>>>
>>> The "k" function seems to work admirably well, the solder mask
>>> enlarges and reduces (shift k) around pads and pins, without a
>>> glitch. Its a very nice function actually.
>>>
>>> (The gschem program however has some serious bugs, it crashes
>>> sporadically.)
>>>
>>> Meanwhile, I have a new question. For a surface mount part, which
>>> parameter is it that I want to reduce to allow a pad to connect to a
>>> copper "pour" on the same side as the part. I drew the "pours" on the
>>> top surface with the rectangle tool, but the parts have some pads have
>>> some space around them
>>>
>>> Thank you
>>>
>>> Mitch
>>>
>>> On 04/02/2018 08:58 AM, Chad Parker wrote:
>>>> There's no real rush, but testing is very much appreciated :) Don't
>>>> hesitate to ask if you have any questions.
>>>>
>>>> On Mon, Apr 2, 2018 at 8:35 AM, Dr M <email address hidden>
>> wrote:
>>>>> I think I can get to it later today, will try
>>>>>
>>>>> On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:
>>>>>
>>>>>> Sorry, not yet, very busy. I have two design mods to do, but haven't
>>>>>> gotten to them yet.
>>>>>>
>>>>>> On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden>
>>>>> wrote:
>>>>>>> The reason I hesitate on that is the word "clearance". Maybe it's not
>>>>>>> what other people call it, but I've always called it "solder mask
>>>>>>> clearance". And the word clearance makes me think that it's a
>>>>>>> difference.
>>>>>>>
>>>>>>> Have you been able to test out the branch?
>>>>>>>
>>>>>>> --
>>>>>>> You received this bug notification because you are subscribed to
>>>>>>> the bug
>>>>>>> report.
>>>>>>> https://bugs.launchpad.net/bugs/1744832
>>>>>>>
>>>>>>> Title:
>>>>>>> Vias tented
>>>>>>>
>>>>>>> Status in pcb:
>>>>>>> In Progress
>>>>>>>
>>>>>>> Bug description:
>>>>>>> Vias are created tented. So far, I have not found any
>>>>>>> description in
>>>>>>> the manual of to how to change this behavior, nor any
>>>>>>> description of
>>>>>>> how to un-tent the via once it has been created. I did...

[Dr M (drmcn)]

Re the thermal tool suggestion.  I found the problem.   We are talking
about connecting pads for an SMT part to a copper pour. According the
documentation, the tool will make a thermal for a pin or via, not for a pad.

On 05/15/2018 06:47 PM, Chad Parker wrote:
> Are you familiar with the thermal tool?
>
> On Tue, May 15, 2018, 18:41 Dr M <email address hidden> wrote:
>
>> I think I figured out the answer to my question. Is it 'ctrl-shift-k' ?
>>
>> In a version where the functions are working, it really is a nice
>> program. The documentation needs some work. The recurring problem
>> seems to widespread use of abbreviated instructions and locally
>> undefined terms.
>>
>>
>> On 05/15/2018 06:01 PM, Dr M C Nelson wrote:
>>> Hi Chad,
>>>
>>> I am doing some PCB designs again. So, we are at long last testing.
>>> Our email chain listed below.
>>>
>>> Per your suggestion, I fetched fresh versions of geda-gaf and pcb
>>> (version v4.1.1-g3bcbb1c6) from git and built them in my directory
>>> tree. I have a few designs to generate in the next few days.
>>>
>>> The "k" function seems to work admirably well, the solder mask
>>> enlarges and reduces (shift k) around pads and pins, without a
>>> glitch. Its a very nice function actually.
>>>
>>> (The gschem program however has some serious bugs, it crashes
>>> sporadically.)
>>>
>>> Meanwhile, I have a new question. For a surface mount part, which
>>> parameter is it that I want to reduce to allow a pad to connect to a
>>> copper "pour" on the same side as the part. I drew the "pours" on the
>>> top surface with the rectangle tool, but the parts have some pads have
>>> some space around them
>>>
>>> Thank you
>>>
>>> Mitch
>>>
>>> On 04/02/2018 08:58 AM, Chad Parker wrote:
>>>> There's no real rush, but testing is very much appreciated :) Don't
>>>> hesitate to ask if you have any questions.
>>>>
>>>> On Mon, Apr 2, 2018 at 8:35 AM, Dr M <email address hidden>
>> wrote:
>>>>> I think I can get to it later today, will try
>>>>>
>>>>> On Mon, Apr 2, 2018, 8:35 AM M Nelson <email address hidden> wrote:
>>>>>
>>>>>> Sorry, not yet, very busy. I have two design mods to do, but haven't
>>>>>> gotten to them yet.
>>>>>>
>>>>>> On Mon, Apr 2, 2018, 8:25 AM Chad Parker <email address hidden>
>>>>> wrote:
>>>>>>> The reason I hesitate on that is the word "clearance". Maybe it's not
>>>>>>> what other people call it, but I've always called it "solder mask
>>>>>>> clearance". And the word clearance makes me think that it's a
>>>>>>> difference.
>>>>>>>
>>>>>>> Have you been able to test out the branch?
>>>>>>>
>>>>>>> --
>>>>>>> You received this bug notification because you are subscribed to
>>>>>>> the bug
>>>>>>> report.
>>>>>>> https://bugs.launchpad.net/bugs/1744832
>>>>>>>
>>>>>>> Title:
>>>>>>> Vias tented
>>>>>>>
>>>>>>> Status in pcb:
>>>>>>> In Progress
>>>>>>>
>>>>>>> Bug description:
>>>>>>> Vias are created tented. So far, I have not found any
>>>>>>> description in
>>>>>>> the manual of to how to change this behavior, nor any
>>>>>>> description of
>>>>>>> how to un-tent the via once it has been created. I did see a
>>>>>>> mention
>>>>>>> in a b...

[Chad Parker (parker-charles)]

Hi Dr. M-

Are you satisfied with the changes in the home/cparker/route_styles_via_sm_clearance branch?

The thermals for SMT pads is another issue. We should start a separate bug report for that.

Thanks,
--Chad

[Dr M (drmcn)]

I fetched your branch, built it, and installed it over  my pre-existing
geda tree,  and I have been running it for a while, to update some
existing boards.  The first one should be coming back from the pcb maker
shortly.

But, referring to your email. I don't see an extra field in the route
styles dialog.  Is there another place that I should look for the new
feature?

I

On 06/10/2018 09:48 AM, Chad Parker wrote:
> Hi Dr. M-
>
> Are you satisfied with the changes in the
> home/cparker/route_styles_via_sm_clearance branch?
>
> The thermals for SMT pads is another issue. We should start a separate
> bug report for that.
>
> Thanks,
> --Chad
>

[Dr M (drmcn)]

i just confirmed that my source tree is up to date with LP1773409

On 06/10/2018 10:46 AM, Dr M C Nelson wrote:
> I fetched your branch, built it, and installed it over  my
> pre-existing geda tree,  and I have been running it for a while, to
> update some existing boards.  The first one should be coming back from
> the pcb maker shortly.
>
> But, referring to your email. I don't see an extra field in the route
> styles dialog.  Is there another place that I should look for the new
> feature?
>
> I
>
>
> On 06/10/2018 09:48 AM, Chad Parker wrote:
>> Hi Dr. M-
>>
>> Are you satisfied with the changes in the
>> home/cparker/route_styles_via_sm_clearance branch?
>>
>> The thermals for SMT pads is another issue. We should start a separate
>> bug report for that.
>>
>> Thanks,
>> --Chad
>>
>

[Chad Parker (parker-charles)]

LP1773409 is the wrong branch. Did you checkout the branch, or just fetch
it?

On Sun, Jun 10, 2018, 11:00 Dr M <email address hidden> wrote:

> i just confirmed that my source tree is up to date with LP1773409
>
>
> On 06/10/2018 10:46 AM, Dr M C Nelson wrote:
> > I fetched your branch, built it, and installed it over my
> > pre-existing geda tree, and I have been running it for a while, to
> > update some existing boards. The first one should be coming back from
> > the pcb maker shortly.
> >
> > But, referring to your email. I don't see an extra field in the route
> > styles dialog. Is there another place that I should look for the new
> > feature?
> >
> > I
> >
> >
> > On 06/10/2018 09:48 AM, Chad Parker wrote:
> >> Hi Dr. M-
> >>
> >> Are you satisfied with the changes in the
> >> home/cparker/route_styles_via_sm_clearance branch?
> >>
> >> The thermals for SMT pads is another issue. We should start a separate
> >> bug report for that.
> >>
> >> Thanks,
> >> --Chad
> >>
> >
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1744832
>
> Title:
> Vias tented
>
> Status in pcb:
> In Progress
>
> Bug description:
> Vias are created tented. So far, I have not found any description in
> the manual of to how to change this behavior, nor any description of
> how to un-tent the via once it has been created. I did see a mention
> in a blog that there is keyboard shortcut, "k", this does not seem to
> work. I have been correcting this manually by editing the PCB file.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>

[Dr M (drmcn)]

i followed the instructions in your your email of 6/1/'18 4:45PM, it was
a checkout.

scanning through the email chain, i see the context at that point was
the directory defaults.  so perhaps i misunderstood.

how should i get the branch?

On 06/10/2018 12:27 PM, Chad Parker wrote:
> LP1773409 is the wrong branch. Did you checkout the branch, or just fetch
> it?
>
> On Sun, Jun 10, 2018, 11:00 Dr M <email address hidden> wrote:
>
>> i just confirmed that my source tree is up to date with LP1773409
>>
>>
>> On 06/10/2018 10:46 AM, Dr M C Nelson wrote:
>>> I fetched your branch, built it, and installed it over my
>>> pre-existing geda tree, and I have been running it for a while, to
>>> update some existing boards. The first one should be coming back from
>>> the pcb maker shortly.
>>>
>>> But, referring to your email. I don't see an extra field in the route
>>> styles dialog. Is there another place that I should look for the new
>>> feature?
>>>
>>> I
>>>
>>>
>>> On 06/10/2018 09:48 AM, Chad Parker wrote:
>>>> Hi Dr. M-
>>>>
>>>> Are you satisfied with the changes in the
>>>> home/cparker/route_styles_via_sm_clearance branch?
>>>>
>>>> The thermals for SMT pads is another issue. We should start a separate
>>>> bug report for that.
>>>>
>>>> Thanks,
>>>> --Chad
>>>>
>> --
>> You received this bug notification because you are subscribed to the bug
>> report.
>> https://bugs.launchpad.net/bugs/1744832
>>
>> Title:
>> Vias tented
>>
>> Status in pcb:
>> In Progress
>>
>> Bug description:
>> Vias are created tented. So far, I have not found any description in
>> the manual of to how to change this behavior, nor any description of
>> how to un-tent the via once it has been created. I did see a mention
>> in a blog that there is keyboard shortcut, "k", this does not seem to
>> work. I have been correcting this manually by editing the PCB file.
>>
>> To manage notifications about this bug go to:
>> https://bugs.launchpad.net/pcb/+bug/1744832/+subscriptions
>>

[Chad Parker (parker-charles)]

you have to replace "LP1773409" with "home/cparker/route_styles_via_sm_clearance". In general, the syntax is

git checkout <branch name>
git pull

The first command switches your source tree to the specified branch. The second command checks the server and merges any updates into your source tree. So, in this case you want to do

git checkout home/cparker/route_styles_via_sm_clearance
git pull

The first time you checkout a branch, it downloads it from the server, so, the git pull is not necessary, but it doesn't hurt. So, if you're not sure if you already have the branch downloaded, you should just run it.

[Dr M (drmcn)]

and then   make install, and it automatically goes to the configured tree?

On 06/10/2018 01:33 PM, Chad Parker wrote:
> you have to replace "LP1773409" with
> "home/cparker/route_styles_via_sm_clearance". In general, the syntax is
>
> git checkout <branch name>
> git pull
>
> The first command switches your source tree to the specified branch. The
> second command checks the server and merges any updates into your source
> tree. So, in this case you want to do
>
> git checkout home/cparker/route_styles_via_sm_clearance
> git pull
>
> The first time you checkout a branch, it downloads it from the server,
> so, the git pull is not necessary, but it doesn't hurt. So, if you're
> not sure if you already have the branch downloaded, you should just run
> it.
>

[Chad Parker (parker-charles)]

when you switch branches, it's often a good idea to

make clean
configure
make

the first gets rid of all of the previously compiled objects. This ensures that there will be no hold-over from the last branch. The second and third I assume you're familiar with.

You don't actually have to do the "make install", of course, you can if you want to. You can run pcb directly from the source tree by executing the script

src/pcbtest.sh

When your testing a branch, this is the approach I recommend. Branches by their nature are not always production ready and can be unstable. Here's how I would describe things:

branches: used to fix bugs and develop new features. Could be unstable, not recommended for actual work
"master": stable, but not guaranteed to be bug free (we try, but it's hard to test all possible use cases). May be used for work if you need a new feature, or particular bug fix.
releases: stable, recommended for work.

[Dr M (drmcn)]

i am familiar with the make tool chain.  my use of git has been very
cursory to-date

On 06/10/2018 02:27 PM, Chad Parker wrote:
> when you switch branches, it's often a good idea to
>
> make clean
> configure
> make
>
> the first gets rid of all of the previously compiled objects. This
> ensures that there will be no hold-over from the last branch. The second
> and third I assume you're familiar with.
>
> You don't actually have to do the "make install", of course, you can if
> you want to. You can run pcb directly from the source tree by executing
> the script
>
> src/pcbtest.sh
>
> When your testing a branch, this is the approach I recommend. Branches
> by their nature are not always production ready and can be unstable.
> Here's how I would describe things:
>
> branches: used to fix bugs and develop new features. Could be unstable, not recommended for actual work
> "master": stable, but not guaranteed to be bug free (we try, but it's hard to test all possible use cases). May be used for work if you need a new feature, or particular bug fix.
> releases: stable, recommended for work.
>

[Dr M (drmcn)]

i see the reason for the discussion on nomenclature

clearance seems like its a quantity that is dded to some diameter like
the other clearance.  but on the other hand, you want to be able to have
a tented via, and zero seems like the right way to represent that,    i
don't see a better solution except perhaps to call it something else,
like "solder mask opening"

i apologize for not getting to it sooner, it really is quite nice.  I
like it.

On 06/10/2018 02:27 PM, Chad Parker wrote:
> when you switch branches, it's often a good idea to
>
> make clean
> configure
> make
>
> the first gets rid of all of the previously compiled objects. This
> ensures that there will be no hold-over from the last branch. The second
> and third I assume you're familiar with.
>
> You don't actually have to do the "make install", of course, you can if
> you want to. You can run pcb directly from the source tree by executing
> the script
>
> src/pcbtest.sh
>
> When your testing a branch, this is the approach I recommend. Branches
> by their nature are not always production ready and can be unstable.
> Here's how I would describe things:
>
> branches: used to fix bugs and develop new features. Could be unstable, not recommended for actual work
> "master": stable, but not guaranteed to be bug free (we try, but it's hard to test all possible use cases). May be used for work if you need a new feature, or particular bug fix.
> releases: stable, recommended for work.
>

[Chad Parker (parker-charles)]

I've been bothered by that term for a while. What do you think of the term "mask aperture"?

BTW, thanks for all of your testing and feedback. I appreciate it, and it's very helpful.

[Dr M (drmcn)]

that's also good.  'opening' is good for the less educated.  i think
they're synonyms.

on the file management thing, with gsch2pcb overwriting my design,  i
think that occurred when i had unsaved changes in the pcb editing
session, and so it was really my fault.   pcb and emacs know when a file
has been changed while they have it open, and i still both together for
some more complicated situations, so a lock file that gsch2pcb would see
when the file is open by pcb might be a solution, but it would be
inconvenient to also lock-out the editor that i sometimes keep open in
parallel,

On 06/10/2018 03:17 PM, Chad Parker wrote:
> I've been bothered by that term for a while. What do you think of the
> term "mask aperture"?
>
> BTW, thanks for all of your testing and feedback. I appreciate it, and
> it's very helpful.
>