Finally, Will Deacon figured out a workaround for the issue on arm code, see below upstream commit:
(CONFIG_PL310_ERRATA_769419 is needed for the fix)
commit 11ed0ba1754841316d4095478944300acf19acc3
Author: Will Deacon <email address hidden>
Date: Mon Nov 14 17:24:58 2011 +0100
ARM: 7161/1: errata: no automatic store buffer drain
This patch implements a workaround for PL310 erratum 769419. On
revisions of the PL310 prior to r3p2, the Store Buffer does not
automatically drain. This can cause normal, non-cacheable writes to be
retained when the memory system is idle, leading to suboptimal I/O
performance for drivers using coherent DMA.
This patch adds an optional wmb() call to the cpu_idle loop. On systems
with an outer cache, this causes an explicit flush of the store buffer.
Cc: <email address hidden>
Acked-by: Catalin Marinas <email address hidden>
Tested-by: Marc Zyngier <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
Signed-off-by: Russell King <email address hidden>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 44789ef..83aa746 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.
+config PL310_ERRATA_769419
+ bool "PL310 errata: no automatic Store Buffer drain"
+ depends on CACHE_L2X0
+ help
+ On revisions of the PL310 prior to r3p2, the Store Buffer does
+ not automatically drain. This can cause normal, non-cacheable
+ writes to be retained when the memory system is idle, leading
+ to suboptimal I/O performance for drivers using coherent DMA.
+ This option adds a write barrier to the cpu_idle loop so that,
+ on systems with an outer cache, the store buffer is drained
+ explicitly.
+
endmenu
Finally, Will Deacon figured out a workaround for the issue on arm code, see below upstream commit: PL310_ERRATA_ 769419 is needed for the fix)
(CONFIG_
commit 11ed0ba17548413 16d409547894430 0acf19acc3
Author: Will Deacon <email address hidden>
Date: Mon Nov 14 17:24:58 2011 +0100
ARM: 7161/1: errata: no automatic store buffer drain
This patch implements a workaround for PL310 erratum 769419. On
revisions of the PL310 prior to r3p2, the Store Buffer does not
automatically drain. This can cause normal, non-cacheable writes to be
retained when the memory system is idle, leading to suboptimal I/O
performance for drivers using coherent DMA.
This patch adds an optional wmb() call to the cpu_idle loop. On systems
with an outer cache, this causes an explicit flush of the store buffer.
Cc: <email address hidden>
Acked-by: Catalin Marinas <email address hidden>
Tested-by: Marc Zyngier <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
Signed-off-by: Russell King <email address hidden>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 44789ef..83aa746 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.
+config PL310_ERRATA_769419
+ bool "PL310 errata: no automatic Store Buffer drain"
+ depends on CACHE_L2X0
+ help
+ On revisions of the PL310 prior to r3p2, the Store Buffer does
+ not automatically drain. This can cause normal, non-cacheable
+ writes to be retained when the memory system is idle, leading
+ to suboptimal I/O performance for drivers using coherent DMA.
+ This option adds a write barrier to the cpu_idle loop so that,
+ on systems with an outer cache, the store buffer is drained
+ explicitly.
+
endmenu
source "arch/arm/ common/ Kconfig" arm/kernel/ process. c b/arch/ arm/kernel/ process. c arm/kernel/ process. c arm/kernel/ process. c
diff --git a/arch/
index 75316f0..3d0c6fb 100644
--- a/arch/
+++ b/arch/
@@ -192,6 +192,9 @@ void cpu_idle(void)
#endif
local_ irq_disable( ); PL310_ERRATA_ 769419 irq_enable( );
+#ifdef CONFIG_
+ wmb();
+#endif
if (hlt_counter) {
local_
cpu_relax();