This rather implies the need for every architecture target, not just x86, to set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_[1248] macros according to whether that target provides CAS ops of varying sizes.
FYI I just got bit on this bug but with an ARM target, hence me finding this report.
@Michael Spencer: Is there a good reason why your fix adding the __GCC_HAVE_ SYNC_COMPARE_ AND_SWAP_ [1248] macros in SVN rev 178816 is x86 only?
If you look at http:// sourceware. org/ml/ libc-ports/ 2010-11/ msg00005. html you'll see that on ARM the use of atomic builtins only happens if __GCC_HAVE_ SYNC_COMPARE_ AND_SWAP_ 4 is set.
This rather implies the need for every architecture target, not just x86, to set __GCC_HAVE_ SYNC_COMPARE_ AND_SWAP_ [1248] macros according to whether that target provides CAS ops of varying sizes.
FYI I just got bit on this bug but with an ARM target, hence me finding this report.
Niall