Comment 5 for bug 1171382

On Mon, 2013-04-22 at 18:56 +0530, Amit Kucheria wrote:
> Tixy, Any theories?

Theories:

1. The value of s3c_cpu_resume will have bit 0 set to indicate Thumb
code and the bootloader doesn't cope with that, e.g. when looking for
the magic 0x2bedf00d value before that address.

2. The bootloader calls s3c_cpu_resume in ARM mode, not thumb mode. Not
likely, because in ARMv7 I believe most (all?) methods of branching to
an address now switch from ARM to Thumb mode if bit zero is set. If
s3c_cpu_resume is getting called in ARM mode you could try pinching the
code from the boot entrypoint 'stext' from arch/arm/kernel/head.S. I.e.
replace "ENTRY(s3c_cpu_resume)" in s5p-sleep.S with:

 .arm
ENTRY(s3c_cpu_resume)
 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
 THUMB( .thumb ) @ switch to Thumb now.
 THUMB(1:

The above will also be needed if theory 1. is the problem and you work
around it by clearing bit zero of the address.

3. Another (unlikely) theory is that the "b ." in the code in bug
comment #1 may not do what we expect, you could try:

1:
 b 1b

--
Tixy