This bug is currently being investigated internally by ARM as a potential platform problem. The issue occurs when the file system is hosted on MMC.
The hypothesis is that a DMA transfer is in progress when a cache flush is requested. The flush operation needs to wait for the MMC DMA transfer to finish, hence introducing a delay that is deemed too long by the firmware. When faced with such condition the processor is switched off without the final cache flush going through, resulting in a corruption of the processor bring-up state machine.
This bug is currently being investigated internally by ARM as a potential platform problem. The issue occurs when the file system is hosted on MMC.
The hypothesis is that a DMA transfer is in progress when a cache flush is requested. The flush operation needs to wait for the MMC DMA transfer to finish, hence introducing a delay that is deemed too long by the firmware. When faced with such condition the processor is switched off without the final cache flush going through, resulting in a corruption of the processor bring-up state machine.