Quick potential solution for internal nets in PCB layout could be assigning a kind of 'local net names' in each pin. e.g. assign pin1 and pin2 net name like $local_interconn would affect a connection of pin1 and 2.
I do not know whether the same solution is possible in EESCHEMA, but I think it is.
Quick potential solution for internal nets in PCB layout could be assigning a kind of 'local net names' in each pin. e.g. assign pin1 and pin2 net name like $local_interconn would affect a connection of pin1 and 2.
I do not know whether the same solution is possible in EESCHEMA, but I think it is.