Comment 2 for bug 1827233

This should include vias. Details from lp:1837207 :

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An intuitive place to have the control may be in Board setup->Tracks and vias and add in the vias frame have "External size" and "Inner size" (this is the approach used in Pads).

An example of such needs can be shown in the xilinx document:
https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf

around page 32 - 33 - 34, where there is almost no copper on the non-connected via.

More examples and usage cases in:
https://forum.kicad.info/t/optimizing-annular-rings-of-vias-in-inner-layers/1514/22
(with new features ideas as "enlarge via copper on layers with connection")

Also is one of the points in:
https://blueprints.launchpad.net/kicad/+spec/few-improvements-for-pcbnew