Comment 7 for bug 1825532
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| Hildo Guillardi Júnior (hildogjr) wrote | #7 |
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a60fb26
(Get the code!)
Yes @Jon. This project worked just fine.
I have one, design now quite more complex (more busses and hierarchical block) and this is not working properly.
I think the issue is related to the fact that (mainly the indicated *):
1) I use a sheet and use in 4 hierarchical blocks;
2) I rename the output bus from `signal[3..0]` to `signal0_[3..0]`, `signal1_[3..0]` ...
3) This "opened busses" are resorted in a `ADC[7..0]` *.