Zone vs. Soldermask clearance collisions at corners

[Paul "LeoNerd" Evans]

If you place an SMT pad in a zone, due to the way the zone clearance gets rounded corners it can mean there's a little bit of copper that overlaps into the pad area.

For example: the attached screenshot shows a zone of clearance 0.01in inside which is placed an SMT pad of mask clearance just under 0.008in (the actual value 0.007874015748in being 0.2mm). You would expect that this is perfectly safe; a nice 0.002in of safety margin between the solder mask opening and the copper zone.

But you'd be wrong. The problem is that the zone clearance only applies vertically and horizontally from the pad; the cleared area within the zone gets a rounded corner of radius 0.010in, meaning it could only guarantee clearance of a square corner at most 0.00707...in (0.01in * sqrt(2)) wide. The mask clearance of 0.008in gives a tiny margin of bare copper from the filled zone exposed within the pad clearance area.

This isn't just a rendering issue; I have had a bad copper run of boards from the fab because of actual spilled out copper in these pad areas, causing grounding shorts to the pads when soldered.

As a workaround for these collisions I've been manually editing the per-pad Cu clearance settings and increasing it on any pad that would be affected. I'd prefer to leave the global zone clearance at a nice small 0.01in though because I need to route some grounding pour between TTH connector pads, so that can't be too big.

[Nick Østergaard (nickoe)]

Please paste your version information.

[jean-pierre charras (jp-charras)]

Zone clearance and solder mask clearance are 2 separate things.

I do not think the zone clearance has a bug. Your png screen copy does not show the copper clearance.
You are mistaken by the clearance word.

[Thor-Arne Hovland (o-lp)]

I don't think this is a bug, rather a design error.

Both the soldermask and zone is filled as it is set up to do.

It is true that these settings leave some of the copper of the zone exposed in the soldermask corners, this should perhaps be trapped by the DRC (zone inside soldermask).

[Paul "LeoNerd" Evans (leonerd)]

jean-pierre charras: The red curvy bit overlaps the purple rectangular bit. This is bad. If I make the red curvy bit further away from the red rectangle inside the purple bit (increase the zone's "clearance"), or if I make the purple bit smaller (decrease the "solder mask clearance") the problem goes away.

By my understanding, the zone "clearance" is the gap between the red rectangle of the pad and the red arbitrary shape of the filled zone, and the "solder mask clearance" is the size of the purple margin around the edge of the pad.

The problem occurs because of that rounded corner - it is insufficient that the copper gap (the region of no-red) is wider than the nominal width of the solder mask aperture (the purple rectangle), because while the copper gap maintains a constant 0.010in clearance, at the apex of the corner the solder mask aperture is sqrt(2)*0.008 = 0.0113...in out; so it overlaps over that red curve by 0.0013...in

Now I'm happy to accept Thor-Arne Hovland's point that this isn't strictly a bug. However, it is still an issue that will catch many newbies out, having caused me and no doubt many others failed copper runs that cost actual money. I'm keen to find a way to ensure this doesn't happen to other people. How we do that is open to question.

We could

  1) Alert a DRC warning if a zone can potentially spill out from a soldermask around a pad of a different net - by my calculations, the zone clearance has to be bigger than sqrt(2) times the mask clearance, for that to be safe.

  2) Alter the way that filled zones are calculated so they don't have rounded corners, and instead have a sharp square corner that follows the shape of the mask aperture.

  3) Alter the way that solder mask apertures work at the edges of filled zones, so they follow the same rounded corner.

Of these options, I feel that 1 is the least-impact safest thing to manage. It means no changes to the geometries of any existing boards, and simply waves a little warning sign to alert newbies such as myself to the potential copper spillout.

[Paul "LeoNerd" Evans (leonerd)]

I'm happy to put it down to a "newbie error", because at a glance a newbie would expect that a zone clearance of 0.010in would definitely be safe from spillout around a solder mask aperture margin of 0.008in, because "surely that's larger". Whereas in fact it is not due to the difference in geometry around the corners - the margin of safety is that it must be larger than sqrt(2) bigger.. maybe call it 1.5 times for layer misalignment safety.

[Paul "LeoNerd" Evans (leonerd)]

Nick Østergaard (nickoe): My current version info is that pcbnew claims (2016-03-29 BZR 6653), and that matches the comment in the top of the .kicad_pcb file. However, I did recently update source, and the PCB file itself may have been generated initially from a copy around mid-February.

If it's any help, the settings my .kicad_pcb file are:

(kicad_pcb (version 4) (host pcbnew "(2016-03-29 BZR 6653)-product")

  (general
    (links 29)
    (no_connects 1)
    (area 101.006729 63.02641 147.913272 87.13192)
    (thickness 1.6)
    (drawings 20)
    (tracks 83)
    (zones 0)
    (modules 11)
    (nets 14)
  )

  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.2032)
    (trace_clearance 0.2032)
    (zone_clearance 0.3048)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.508)
    (via_drill 0.4064)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0)
    (uvia_min_drill 0)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 0.762 0.762)
    (mod_text_width 0.127)
    (pad_size 1.2 0.75)
    (pad_drill 0)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFEF7F)
    (pcbplotparams
      (layerselection 0x010f0_ffffffff)
      (usegerberextensions true)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory ""))
  )

[jean-pierre charras (jp-charras)]

Again, copper zone clearance and solder mask clearance are not related.
Moreover, copper zones and solder mask are not related, no matter you are a newbie or not.

Solder mask clearance has meaning *only* for pads, not for tracks and copper zones.
Therefore what you are asking has just no meaning for me.

[Paul "LeoNerd" Evans (leonerd)]

> Solder mask clearance has meaning *only* for pads, not for tracks and copper zones.

I am aware of that. The solder mask clearance is the size of the purple margin around the pad, such as the pad named "Net-(U1-Pad14)" in my original screenshot. The mask applies only to that pad, nothing else. Not the zone, not the track. I understand that.

Please see my newly-attached image, containing three parts. Hopefully this will make my complaint clear.

Part A) I have indicated the solder mask clearance - the width of the purple margin is 8mil. I have indicated the zone clearance, which in this example is set to 20mil. All is safe- note how the red curving corner does not go anywhere near the purple aperture of the solder mask. No chance of a spillout here.

Before we continue - do you agree that I have correctly identified the measurements in this example that are
  solder mask clearance - the upper green arrow, measured as 0.008in (8mil)
  zone clearance - the lower green arrow, measured as 0.020in (20mil)
For the rest of my explanation to make sense it is important that I've got these correct, so please point out if they are not.

Part B) The zone clearance is now set to the same value as the solder mask clearance - 8mil. Note how the constant gap between the red parts (the copper clearance) is a constant 8mil, including an 8mil radius curve at the corner. This causes the copper of the outside zone fill to become exposed at the rectangular sharp corners of the solder mask aperture - as indicated ringed in bright green on the bottom two corners. It is this exposed copper that caused me grounding shorts when I soldered up a board, and is the problem I am trying to avoid.

Part C) The zone clearance is now set to 12mil (which is 1.5*8mil), meaning that the 12mil radius curves are now clear of the sharp corners of the purple solder mask aperture - note how the red copper zone no longer spills out from behind the solder mask aperture. 12mil is the smallest value that achieves this safety - at 11mil or smaller, the sharp corner of the mask aperture manages to just catch a little of that zone copper, risking a short.

My complaint is that as a newbie I was not aware of these rounded corners - the cause of the spillout in part B. I had thought it safe enough to simply set a value of zone clearance that is larger than the solder mask clearance and that would be good enough. I am now aware, from my mistake, that it has to be at least 1.5 times larger, before this is actually safe. I would therefore like something to help people avoid this mistake - see the list in my previous comment for my suggestions on how to do this.

[jean-pierre charras (jp-charras)]

I perfectly understand what you mean.
But there is nothing which can be fixed in Pcbnew.
Each user should set clearances depending on her constraints.

This discussion should be in a Kicad forum or user group, not in a bug report.

[Artsiom Shchatsko (cioma)]

Definitely not a tool issue. Ways to solve the problem:

- Decrease the solder mask aperture margin. 0.008 in (8 mil, 0.2032 mm) is rather large for modern manufacturing process
- Create cutouts on zone

[Paul "LeoNerd" Evans (leonerd)]

If 0.008in is "rather large" for a modern process, maybe KiCad's default could be set smaller than that? Right now if I just start a new blank pcb by running pcbnew directly and hit the menu option, I get 0.2mm, or 0.007874...inch.

I still think that this should appear as a DRC warning though. Can we consider this bug to be a feature request in that direction? I'd like a DRC warning whenever there's a risk of (or actual) copper spilling out from under the solder mask into one of the apertures.

[Brooke Hedrick (brooke-t-hedrick)]

Hi,

I am a hobbyist and have been using KiCAD for about 3 or 4 years. My last 4 boards had issues where the ground plane had a small sliver of copper exposed around any through-hole pads. As a result, I was getting shorts as the solder was bridging from the through-hole pad to the ground plane.

Here's a thread I started on the Contextual Electronics forums:
https://forum.contextualelectronics.com/t/pcb-manufacture-troubleshooting/301/6

I thought maybe I had changed something on my last 4 boards that caused the issue, but between this ticket and some others that have seen similar issues, it looks like maybe KiCAD's defaults changed from 0 to .007...

Unfortunately for me, I didn't think to check all of the KiCAD settings before ordering boards to notice that the defaults had changed and ended up spending quite a bit of troubleshooting to figure out the pattern of shorts.

If this is due to KiCAD default values, could there be a better set of defaults for these settings or something that prompts the user that they need to set them?

For me, KiCAD has been an awesome tool so I have donated to the project. If my very first boards hadn't worked due to default settings, I would have probably been too frustrated and it would have made me look for a different tool.

I really appreciate the work you guys do on KiCAD. Please keep it up.

Thanks,
Brooke Hedrick

[Paul "LeoNerd" Evans (leonerd)]

I have just encountered this issue yet again on yet another board. I feel that it might want looking into at some point.

It occurs to me, I think the problem ultimately stems from the fact that the solder mask and the copper pour layers each have different ideas on how to enlarge the area of the rectangular pad. There's two equally-valid approaches:

 1) make another rectangle with longer sides

 2) make an arbitrary area with straight sides and rounded corners

Either approach is technically valid, as long as all layers consistently pick the same approach. This copper spillover collision happens because the solder mask layer makes a bigger rectangle, but the copper pour zone clears an area with rounded corners, which then collide with the sharp square corners of the mask.

It seems that fixing this issue properly in code so that it can't happen to anyone ever again should be a simple matter of making both layers pick the same algorithm for rectangular pads - either have both pours and mask use rounded corners, or have neither do so.

I'm unfamiliar enough with any potential knock-on effects on other layers of the stack (e.g. the solder paste or adhesives) that this might also affect, so I can't make a firm suggestion on which technique. But generally I feel all layers should pick *the same* algorithm, whichever it happens to be.

[Jt Whissel (jtwhissel)]

I have this issue too using the latest nightly build.

[Jt Whissel (jtwhissel)]

Here is another screenshot showing I have Corner smoothing on "None" and yet you can see the +BATT zone has its corners rounded.

[Jeff Young (jeyjey)]

This is a bug. If I set the solder mask clearance to 0.008" I don't mean a clearance of 0.008" on the sides and a clearance of 0.011" at the corners. I mean 0.008".

It's got nothing to do with zones.

[jean-pierre charras (jp-charras)]

@Jeff,

I am thinking you are wrong.

The purpose of the solder mask clearance is to avoid issues due to registration defects between the copper layer and the solder mask.

If you have set a clearance of 0.008", this is because the registration defect can be up to 0.008" on X axis and Y axis.
And if you want a corner clearance of 0.008", it means you cannot accept a registration error in X+Y axis bigger than 0.0057".

The mask clearance is a XY margin, not a minimal distance between copper and solder mask.

Clearance between copper items is an other thing: it is a minimal distance, not a registration margin.

[Jeff Young (jeyjey)]

@JP, excellent point.

So we have a conundrum between getting enough solder down with respect to registration errors, and preventing too much solder (bridges) with respect to zone outline mismatches.

Still, it seems to me that not getting solder on the corner of a square pad (because a registration error with a rounded-corner-solder-mask clipped a bit of it off) is better than getting a bridge because they had a mask/zone mismatch.

[Rene Poeschl (poeschlr)]

Is this the same thing reported in this forum post?
https://forum.kicad.info/t/filled-zone-cuts-corner-of-mask-on-square-pads/12009/

Or should we open a new bug for that? (That report shows that it is now easily possible to have exposed copper near pads as the copper clearance is calculated differently to the mask clearance)

[Jan-Åke Larsson (jalar)]

Yes, it is the same thing.

I find it really really strange that Mask clearance defaults to the same value as Copper clearance.

This means, even without a filled zone, that a copper trace near an SMD pad can get exposed by the tiniest registration error (mask offset wrt copper).

I'd suggest at the very least to make Mask clearance default to /half/ of Copper clearance.

[Jan-Åke Larsson (jalar)]

Actually this means, even without a filled zone, that a 45 degree copper trace near an SMD pad will get exposed even without any registration error (mask offset wrt copper). See below.

Again, I’d suggest at the very least to make Mask clearance default to half the Copper clearance. (Or even take the rounded copper clearance into account, so that the default Mask clearance=Copper clearance/sqrt5 [~0.09mm], allowing the registration error to be equal in both x and y, and also both positive and negative.)

[Rene Poeschl (poeschlr)]

Setting solder mask clearance to half the copper clearance does not solve the problem. Unless you set both clearances to much larger values then the possible misalignment vector length. (So goodbye high density boards)

---

I also doubt the interpretation of @jp-charras. IPC defines misalignment as a vector of fixed length. So if you expect a misalignment of 0.1mm, you will never have 0.1mm in both x and y direction.

Here are the two options to solve this as described in my post over on the forum. (see screenshot for more details)

- Option 1 (cyan) Use the same center point for the mask rounding as for the copper pad rounding. This would be how the copper clearance is calculated right now. -> smallest possible area for copper and mask clearance.
- Option 2 (red) Use the mask rounding center as the center for the copper clearance as well. -> largest sensible area for copper and mask clearance.

If we use the misalignment definition by IPC we can use option 1. Otherwise option 2 will be the way to go. No matter what interpretation is used, the current way of doing it creates boards that are wrong. (They result in different soldermask to copper clearances around all pads.)

---

I strongly object the first few posts where it was put to user error! This is definitively not a user error. You can not use different calculation methods for different clearances. This just creates problems if both clearances go in the same direction (Meaning in this case if you have non solder mask defined pads. Which is the industry standard.)

[Rene Poeschl (poeschlr)]

Split away as second answer as i can not add multiple pictures per post.

The expectation is that if one sets 0.2mm copper to copper clearance and 0.1mm mask clearance, one can never have problems as no matter how badly misaligned the mask is it will still cover nearby copper. With the current way of calculating the two clearances this is not the case. If the misalignment is at 45° you will get free copper. (opposite of where the mask to pad clearance is reduced by the misalignement) Even with misalignment vector at 0 degree you will have a small area free of copper. (I showcase this by using a pad on bottom with the same settings but misaligned by 0.1mm. Note the areas of possible free copper near the corners of the mask.)

[Jan-Åke Larsson (jalar)]

I was actually addressing a different issue in items #21 and #22 (except for the very first sentence in #21), I think that mask clearance default is too big, independent of the issue reported here. I will report that separately.

[Jakub Kozdon (fldrivers)]

Both options which Rene described in #23 can be options in SW so designer can make a decision what is better for him and mainly for manufacturing. Maybe this can be an option also for footprint/pad as footprint or pad can have set own clearancies. This can be option also for net class. So file format is needed. But definitely this can cause shorts on PCBs.

[Rene Poeschl (poeschlr)]

I just noticed another inconsistency. Polygon pads behave differently to normal pads. They use rounded corners on the soldermask. (So they look like solution 1)

[Jt Whissel (jtwhissel)]

Honestly Kicad should be 100% perfect output since it is electronic. There
should not be any misalignment that happens in kicad that will only be
exaggerated by the manufacturer which is allowed to have misalignment since
there is human and mechanical error in the process.

On Mon, Aug 27, 2018 at 3:57 AM Rene Poeschl <email address hidden>
wrote:

> I just noticed another inconsistency. Polygon pads behave differently to
> normal pads. They use rounded corners on the soldermask. (So they look
> like solution 1)
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1563744
>
> Title:
> Zone vs. Soldermask clearance collisions at corners
>
> Status in KiCad:
> Triaged
>
> Bug description:
> If you place an SMT pad in a zone, due to the way the zone clearance
> gets rounded corners it can mean there's a little bit of copper that
> overlaps into the pad area.
>
> For example: the attached screenshot shows a zone of clearance 0.01in
> inside which is placed an SMT pad of mask clearance just under 0.008in
> (the actual value 0.007874015748in being 0.2mm). You would expect that
> this is perfectly safe; a nice 0.002in of safety margin between the
> solder mask opening and the copper zone.
>
> But you'd be wrong. The problem is that the zone clearance only
> applies vertically and horizontally from the pad; the cleared area
> within the zone gets a rounded corner of radius 0.010in, meaning it
> could only guarantee clearance of a square corner at most 0.00707...in
> (0.01in * sqrt(2)) wide. The mask clearance of 0.008in gives a tiny
> margin of bare copper from the filled zone exposed within the pad
> clearance area.
>
> This isn't just a rendering issue; I have had a bad copper run of
> boards from the fab because of actual spilled out copper in these pad
> areas, causing grounding shorts to the pads when soldered.
>
> As a workaround for these collisions I've been manually editing the
> per-pad Cu clearance settings and increasing it on any pad that would
> be affected. I'd prefer to leave the global zone clearance at a nice
> small 0.01in though because I need to route some grounding pour
> between TTH connector pads, so that can't be too big.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/kicad/+bug/1563744/+subscriptions
>

--
From,
Jt Whissel

[Rene Poeschl (poeschlr)]

@jtwhissel
The misalignment i mention above is the one of the manufacturer. (I just used kicad to showcase it as i was not motivated enough to make the drawing in another tool)
Kicad outputs the soldermask correctly.

[Rene Poeschl (poeschlr)]

Solving this will require taking https://bugs.launchpad.net/kicad/+bug/1782957 into account.

[KiCad Janitor (kicad-janitor)]

Fixed in revision e1d5cf1a87947ed29690c6cd31d541dc535fa013
https://git.launchpad.net/kicad/patch/?id=e1d5cf1a87947ed29690c6cd31d541dc535fa013