Using tilde inside labels may confuse ERC module in Eeschema

[Kerusey Karyu]

Eeschema permits the use of tilde character (~) in labels to distinguish inverted signals.
You can use both "~LABEL" and "~LABEL~" scheme which has the same visual effect: the label become overscored.

Unfortunately for the ERC module these two labels are different which results in an ERC error:
"ErrType (2): Pin not connected (and do not connect the symbol found on this pin)"

I see two options, keeping current functionality:
 - Eeschema will automatically add the ending tilde, when will not find another one in the string.
 - Eeschema will remove the final tilde if there are no more characters following the tilde.

Application: eeschema
Version: (2015-11-29 BZR 6336)-product release build
wxWidgets: Version 3.0.0 (debug,wchar_t,compiler with C++ ABI 1002,GCC 4.8.2,wx containers,compatible with 2.8)
Platform: Windows 7 (build 7601, Service Pack 1), 64-bit edition, 64 bit, Little endian, wxMSW
Boost version: 1.54.0
         USE_WX_GRAPHICS_CONTEXT=OFF
         USE_WX_OVERLAY=OFF
         KICAD_SCRIPTING=ON
         KICAD_SCRIPTING_MODULES=ON
         KICAD_SCRIPTING_WXPYTHON=ON
         USE_FP_LIB_TABLE=HARD_CODED_ON
         BUILD_GITHUB_PLUGIN=ON

[Kerusey Karyu (keruseykaryu-deactivatedaccount)]

Global labels also affected. For example:

ErrType(8): Global label not connected to any other global label
  @ (2.000 in,9.500 in): Global label ~LABEL~ is not connected to any other global label.

[Kerusey Karyu (keruseykaryu-deactivatedaccount)]

Just one comment for those who might not see where the dangerous created with this problem is.

A hypothetical situation. Four hierarchical sheets. The two sheets have global labels called ~LABEL. The other two have global labels ~LABEL~. For the ERC such a situation is normal, because every global label merges with another label. Unfortunately, it does not create single connection as engineer/engineers (team work) wants but create two separate connections.

[Wayne Stambaugh (stambaughw)]

On 12/03/2015 04:09 PM, Kerusey Karyu wrote:
> Public bug reported:
>
> Eeschema permits the use of tilde character (~) in labels to distinguish inverted signals.
> You can use both "~LABEL" and "~LABEL~" scheme which has the same visual effect: the label become overscored.

This isn't unexpected. ~LABEL and ~LABEL~ are not the same label even
though they may look the same.

>
> Unfortunately for the ERC module these two labels are different which results in an ERC error:
> "ErrType (2): Pin not connected (and do not connect the symbol found on this pin)"

It seems to me the ERC is doing it's job as expect.

>
> I see two options, keeping current functionality:
> - Eeschema will automatically add the ending tilde, when will not find another one in the string.
> - Eeschema will remove the final tilde if there are no more characters following the tilde.

I would prefer not to strip anything off my labels. The trailing ~ in
you hypothetical example is unnecessary. Either Eeschema should
complain about an invalid label or it should display the all ~s but the
first one. Maybe we should prevent users from getting too creative with
their label naming. I'm not sure how serious this problem is given that
the ERC does the correct thing.

>
>
> Application: eeschema
> Version: (2015-11-29 BZR 6336)-product release build
> wxWidgets: Version 3.0.0 (debug,wchar_t,compiler with C++ ABI 1002,GCC 4.8.2,wx containers,compatible with 2.8)
> Platform: Windows 7 (build 7601, Service Pack 1), 64-bit edition, 64 bit, Little endian, wxMSW
> Boost version: 1.54.0
> USE_WX_GRAPHICS_CONTEXT=OFF
> USE_WX_OVERLAY=OFF
> KICAD_SCRIPTING=ON
> KICAD_SCRIPTING_MODULES=ON
> KICAD_SCRIPTING_WXPYTHON=ON
> USE_FP_LIB_TABLE=HARD_CODED_ON
> BUILD_GITHUB_PLUGIN=ON
>
> ** Affects: kicad
> Importance: Undecided
> Status: New
>
>
> ** Tags: eeschema erc labels
>

[Kerusey Karyu (keruseykaryu-deactivatedaccount)]

> It seems to me the ERC is doing it's job as expect.

In an example of two local labels written in different scheme. If we have at least one pair for them, ERC will fail.

> I would prefer not to strip anything off my labels. The trailing ~ in
> you hypothetical example is unnecessary.

Look at it from the right side. The two designers involved in the one project. One design microprocessor part sheets, a second an I/O sheets. One has a habit of writing ~LABEL, second one use ~LABEL~.
Do they have a chance to draw a diagram so that the ERC will detect no error? Yes! Terms that I described are enough.

> I'm not sure how serious this problem is given that
> the ERC does the correct thing.

Use this simple schematic and check. ERC will be blind...

[Chris Pavlina (pavlina-chris)]

I'm with Kerusey. This is confusing and surprising behavior - a stray tilde could easily make for weird issues that are quite hard to track down if you don't know what you're looking for.

What about *displaying* tildes that have no visible effect?

[Jon Neal (reportingsjr)]

Kind of related to this bug. Tildes adding overlines is something that I never liked and it actually bit me when I first started using kicad. Tildes are commonly used to indicate an AC signal. If you put text anywhere that is just a tilde it just vanishes without warning and you have to randomly click around to try and find the text again.

How about adding a flag to text in the new eeschema file format that specifies if text should have an overline? Then it could just be an option in the text dialog which is much more obvious than adding a tilde AND allows people to use tildes in schematics.

Then ERC can go off of the flag and tildes will be treated like regular text.

[Chris Pavlina (pavlina-chris)]

No, because then how do you type things like "R/~W"?

[jean-pierre charras (jp-charras)]

"Tildes are commonly used to indicate an AC signal"
No problem.
Type "~~" like you have to do in printf format to print a %.

[KiCad Janitor (kicad-janitor)]

KiCad bug tracker has moved to Gitlab. This report is now available here: https://gitlab.com/kicad/code/kicad/-/issues/2000