filled zone clearance influenced by edge.cuts line width

Bug #1516244 reported by Joan
28
This bug affects 6 people
Affects Status Importance Assigned to Milestone
KiCad
Won't Fix
Undecided
Unassigned

Bug Description

tested and confirmed in:
KiCAD BZR 6097, in module pcbnew
KiCAD 4.0.0 RC1, in module pcbnew

A copper pour zone that goes to/over a board outside definition has a clearance setting which allows to define a clear space between the board edge and the copper pour.
The board edge is defined as the center of the graphic lines on the edge.cuts layer.

The problem is that the zone fill clearance setting doesn't use the center of the edge.cuts graphics lines, but the edge of those lines that is closest to it (madworm: I suspect the code doesn't care what object is in the way, be it a track or line).
Undesired result - changing the width of those lines affects the zone pour.

For screenshots and more see this link on KiCAD.info:
https://forum.kicad.info/t/zone-setback-influenced-by-edgecut-line-thickness-why/1690

Revision history for this message
Joan (joanthesparky) wrote :
Joan (joanthesparky)
description: updated
Revision history for this message
jean-pierre charras (jp-charras) wrote :

Where is the bug?

"The board edge is defined as the center of the graphic lines on the edge.cuts layer."
I already saw other definitions. This is therefore not alway true, although it is the more usual definition.

Revision history for this message
Joan (joanthesparky) wrote :

>Where is the bug?

If the graphic line width on the edge.cuts layer work as you describe, then one has to calculate different coordinates for the board outline versus what the actual coordinates of the lines defining them are.
I don't see this kind of thinking applied anywhere else in KiCAD nor any other CAD package I've been working with in the last 15 years?
This means cutouts would need to be undersized for coordinate input, while board outline coordinate inputs would need to be oversized.. and all that depending on the chosen line width?

Revision history for this message
Chris Gibson (chris-w-gibson) wrote :

I believe this line...

429 int linewidth = m_Width + (2 * aClearanceValue);

in TransformShapeWithClearanceToPolygon.cpp to be the culprit.

Changing it to...

429 int linewidth = 2 * aClearanceValue;

Fixes the problem. Others may disagree but I do see it as a problem not a feature.

Changed in kicad:
status: New → Won't Fix
Revision history for this message
Nicholas Savenlid (nicholas-z) wrote :

Maybe not a bug but it is a lack of vital functionality

You should be able to define edge keep-out under design rules and traces and zones should stay out of there.

zones should auto adjust themselves and traces give DRC if too close to edge.
the zone-clearance attribute is not usable as it affects all clearences.

clearance to edge typically is 0.25mm and clearance to other metal is 0.15mm (typically)
Not same parameter.

please, re-open / rename / move to correct place

Revision history for this message
Nicholas Savenlid (nicholas-z) wrote :

the undesired result of changing the line-width of edge-cut is what i use to force to zones 0.25mm from edge
so i set the line width to 0.5mm for edge-cut

of course the traces dont care about that but its another story.

how-ever its a massive editing attack to edit edge-cuts on boards that have complicated shapes.
(i know, can do in text editor)

correct place for edge-cut-keep-out should be under design-rules tab

IMHO
Respectfully

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