Wishlist: "harnesses" or buses with named members

[Chris Pavlina]

It would be exceedingly useful if KiCad allowed buses to have named members. As far as I can tell, buses are intended to be used exclusively for numbered, sequential elements like data bits; one can "fake" named members but the support code such as hierarchy traversal will balk. The grouping functionality could be quite nice to have for named signals as well.

Example use cases include a memory bus including control signals, and in the project I'm working on right now, a differential bus which has signals "BUS0+, BUS0-" through "BUS7+, BUS7-" as well as "BUSCLK+, BUSCLK-". Grouping them into separate positive and negative buses could work, but it doesn't really fit with the usual differential design practice of keeping signals paired at all times.

(Side note - I know there's current work on differential routing; dunno if there are related plans at least to support pairs because of that.)

Altium implements this as "signal harnesses", see here: http://techdocs.altium.com/display/ADOH/Using+Signal+Harnesses

I'm not familiar with the code that implements buses, so I don't know how difficult this would be to add, though I might look into it myself later tonight...

[Nicholas Savenlid (nicholas-z)]

crucial feature available on all other major tools out there
mentor, cadence etc

cant live without it

[Nicholas Savenlid (nicholas-z)]

in mentor you edit a separate bus file containing all the project´s buses and its members.

so you actually get suggestions on members when you connect to the bus, of course you need to name it ta a valid bus name existing in your file first
bus members can be arbitrary names and arrays net[0:10]
also signed bus members net[0:10]+ , net[0:10]- this will form diff-pair automatically in constraints editor.

i am up to some major head-ache now on to how to avoid this bug that will make schematics way more complex and logical

being logical is the point with schematics

[Doug McKnight (doug-f)]

I'm not sure if this is precisely the same issue/request but I think it would be excellent if there was a way to, elegantly, split buses for connection to hierarchical sub-sheets.

E.g. I have a 64-bit bus Analog[0..63] and I want to hook it up to a set of drivers. Each driver has its input, In[0..7] which it presents as a hierarchical pin in the usual way.
So, the connections would be:

Analog[0..7] ---> Driver_0[0..7]
Analog[8..15] ---> Driver_1[0..7]
Analog[16..23] ---> Driver_2[0..7]

Analog[56..63] ---> Driver_7[0..7]

If there's already a way to do this, I'd love to be corrected, but the only work round I have found is to draw a stack of wires, each with both names on it...

I've used another schematic tool that does this. If one rips a bus into smaller buses, with the correct number of wires (8 in this case) and connect it to an input with that number of wires, it simply does the mapping in the obvious way by incrementing the wire labels appropriately.

IMHO hierarchical schematics are essential for logic, clarity, and sanity for certain types of design. I would love it if KiCad were to strengthen its support for this kind of design.
Doug

[Stephen Walker-Weinshenker (sww1235)]

@Doug, have you tried manually placing junctions at branches of your busses. You might be able to get your scenario to work if you create short branches off of the main bus using junctions (not certain if bus to bus connectors would work as well) and then use a label to select the appropriate 8 signals from the main bus on each short branch.

[Hack Spider (hackspider)]

This feature is "In Progress" over a year. Are there any updates since then?

I would love to see the heterogeneous bus feature in KiCAD since this is the last feature why we are currently sticking to Altium (with the high subscription fees). Anything else is solved/work around.

Best regards
    hackspider

[Maciej Suminski (orsonmmz)]

Hi Hack Spider,

The main reason why the feature is not in the master branch is that we have not started yet the 6.0 development cycle. It means that we currently focus on fixing Python and GTK3 issues that will land in 5.1 and after that we will starting adding new stuff.

Feel free to take the feature branch [1] for a test ride. Be warned that it is still considered experimental and you might not be able to open your schematics with the standard KiCad builds once you start using the new features. If you do not want to risk too much, then you may find interesting an early announcement and demo [2].

1. https://github.com/craftyjon/kicad/tree/bus_upgrades
2. https://lists.launchpad.net/kicad-developers/msg32423.html

[Theo Beisch (tb3000)]

Hi Jon,
new here and still in learning curve mode while getting ready for a larger multisheet project.
I saw your 2017 video on the new bus features - exactly what I neeed!
Is this available in the nightly builds already or do I need to wait (and use global labels for now ;-()
Thanks
Theo

[Wayne Stambaugh (stambaughw)]

@Theo, this is available nightly builds. The documentation for the new bus notation can be found at http://docs.kicad-pcb.org/5.1.2/en/eeschema/eeschema.html#wires-buses-labels-power-ports. Please keep in mind that nightly builds are a work in progress so there may be some usability and stability issues.

[John McNelly (coolnamesalltaken)]

I just tried this on the latest nightly build--unfolding a wire from the bus can cause EESchema to crash if it isn't connected to a pin. Fantastic looking tool though, can't wait to use it when it's ready :)

[Theo Beisch (tb3000)]

Thanks guys, impressive - also the quick response!!
Is there a timeframe for when it might become available in stable?

[Jon Evans (craftyjon)]

@John -- please file a bug report for this. It used to work but likely was broken by the massive changes that have been happening to Eeschema editing tools recently. Keep in mind that current nightlies are not very stable in general at this point in the V6 development process and so it's not recommended to use them for production work.

@Theo -- There is not yet an established timeline for V6 release.

[Gonçalo Camelo Neves Pereira (c4f4s0g0)]

I am having crashes too. I don't have a clear idea how to use a bus in terms on naming schemes. I have a bus called "Camera" and I have all the pins there, like D0..D7 but also HSync and VSync and it doesn't work across a hierarchical label that in the top-level design connects to a normal label that is in another hierarchical sheet and only then, on the second sheet I need to unfold the bus.
I am not sure how can I fix it. Maybe you can help me with it? https://github.com/ieeeupsb/Dora/tree/master/electrical/core