intel

  1. Bug #1849581
  2. Comment #0

Comment 0 for bug 1849581

Revision history for this message
quanxian (quanxian-wang) wrote :

Description
The core count in the Turbo ratio limit buckets can be non linear. So need to read TRL MSR and display correctly.

Since we don't allow MSR access from user space, added to the whitelist to read TRL MSR.

Also intel-speed-select tool is changed to use this new interface.

Target Kernel: 5.4
Target Release: 20.04