Comment 1 for bug 1759188

This commit fix the issue.

commit 30414f3010aff95ffdb6bed7b9dce62cde94fdc7
Author: Lucas De Marchi <email address hidden>
Date: Tue Jan 2 12:18:37 2018 -0800

    drm/i915: Apply Display WA #1183 on skl, kbl, and cfl

    Display WA #1183 was recently added to workaround
    "Failures when enabling DPLL0 with eDP link rate 2.16
    or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
    (CDCLK_CTL CD Frequency Select 10b or 11b) used in this
     enabling or in previous enabling."

    This workaround was designed to minimize the impact only
    to save the bad case with that link rates. But HW engineers
    indicated that it should be safe to apply broadly, although
    they were expecting the DPLL0 link rate to be unchanged on
    runtime.

    We need to cover 2 cases: when we are in fact enabling DPLL0
    and when we are just changing the frequency with small
    differences.

    This is based on previous patch by Rodrigo Vivi with suggestions
    from Ville Syrjälä.

    Cc: Arthur J Runyan <email address hidden>
    Cc: Ville Syrjälä <email address hidden>
    Cc: Rodrigo Vivi <email address hidden>
    Cc: <email address hidden>
    Signed-off-by: Lucas De Marchi <email address hidden>
    Reviewed-by: Ville Syrjälä <email address hidden>
    Signed-off-by: Rodrigo Vivi <email address hidden>
    Link: https://patchwork.<email address hidden>
    (cherry picked from commit 53421c2fe99ce16838639ad89d772d914a119a49)
    [ Lucas: Backport to 4.15 adding back variable that has been removed on
      commits not meant to be backported ]
    Signed-off-by: Jani Nikula <email address hidden>
    Link: https://patchwork.<email address hidden>