Enhancement: Hierarchical Bus handling and netlisting

[nobody]

From Dan Deisz at Rochester Electronics:
<email address hidden>

It would be great if gschem handled hierarchical bussing by enabling the bus notation to be more than just a graphic notation as it is today. This would have to include netlisting capability (preferrably for verilog). At my company, we have to re-enter schematics in a hierarchical fashion that includes bussing up and down the hierarchy. If we don't preserve the graphics as they were originally done (about 20 years ago), we won't be able to validate what we have done easily. In addition, the explosion of pins on a single page makes the schematic largely unreadable. Currently, it's looking like we need to go buy a package somewhere that can do this, but I would love to use gschem because it's easier to use.

I know that hierarchical bussing support can almost lead to religious wars as to how it should be handled. From my perspective, I would rather see something done than nothing done for this.

[Peter Clifton (pcjc2)]

Proper bus support won't come quickly, however Steve Meier has a fork of libgeda / gnetlist which does support busses. I'm not sure of the exact details of the syntax though.

If you're able, posting an example screen-shot of the kind of bus syntax you're using in the old schematics might give food for thought when this feature is looked at in the future.

I presume by "explosion of pins", you're referring to what would happen if you had to manually route to every wire inside a bus on each symbol.

[nobody (nobody-users)]

I posted an example schematic with busses at id #2459501.

[ddeisz (ddeisz)]

I haven't been able to find an official release of gschem or gnetlist that supports hierarchical busses through to a hierarchical verilog netlist yet. Did I miss something or does anyone want more examples?