Generated code is wrong due to the output template of the patterns (please see below). Commit 201250 Fixes it.
243.dfinish ============= (insn 62 61 63 2 (set (reg:SI 3 r3 [orig:156 _qh ] [156]) (plus:SI (plus:SI (geu:SI (reg:CC 100 cc) (const_int 0 [0])) (reg:SI 3 r3 [orig:151 D.4776 ] [151])) (reg/v:SI 1 r1 [orig:110 __x3 ] [110]))) test.c:44 18 {*addsi3_carryin_alt2_geu} (expr_list:REG_DEAD (reg:CC 100 cc) (expr_list:REG_DEAD (reg/v:SI 1 r1 [orig:110 __x3 ] [110]) (nil))))
Generated Wrong Code =============== adc r3, r3 @ 62 *addsi3_carryin_alt2_geu/1 [length = 4]
Generated code is wrong due to the output template of the patterns (please see below). Commit 201250 Fixes it.
243.dfinish
( const_int 0 [0]))
(reg: SI 3 r3 [orig:151 D.4776 ] [151]))
(reg/ v:SI 1 r1 [orig:110 __x3 ] [110]))) test.c:44 18 {*addsi3_ carryin_ alt2_geu} list:REG_ DEAD (reg:CC 100 cc)
(expr_ list:REG_ DEAD (reg/v:SI 1 r1 [orig:110 __x3 ] [110])
(nil) )))
=============
(insn 62 61 63 2 (set (reg:SI 3 r3 [orig:156 _qh ] [156])
(plus:SI (plus:SI (geu:SI (reg:CC 100 cc)
(expr_
Generated Wrong Code carryin_ alt2_geu/ 1 [length = 4]
===============
adc r3, r3 @ 62 *addsi3_