Comment 5 for bug 1608882

Hi Thomas,
I must reformulate my original description - I have missed very important fact: the consecutive write-read operations above the same address. CPU writes some command value X at the address A and the device (FPGA, in our case) "responds" by writing some confirmation value Y at the same address A - CPU reads this value Y back to get the device acceptance.
Well, such consecutive write-read operations can be somehow understood by the optimizer - but I would expect no optimization impact in this case - the variable (the type respectively) is defined as the volatile one... and that is obviously done as the piece of Assembler below shows:

So the better C snippet is as follows:

  typedef volatile struct tExtMemDev
  {
    unsigned short regA;
    unsigned short regB;
    unsigned short regC;
  } __attribute__((packed)) T_EXT_MEM_DEV;

  T_EXT_MEM_DEV rxBuff __attribute__ ((section (".external_device")));

  int foo (void)
  {
    int ret;

    rxBuff.regA = 0xDEAD;

    if(rxBuff.regA == 0xBEEF)
    { ret = 0; }
    else
    { ret = -1; }

    return ret;
  }

The Assembler looks good ;-)

  39 0010 801A strh r2, [r3] @ movhi
  16:test.c **** { ret = 0; }
  40 .loc 1 16 0
  41 0012 881B ldrh r3, [r3]

I am continuing...