Comment 2 for bug 1322526

More information for NW and CD as below:

CD: Cache Disable (bit 30 of CR0) - When the CD and NW flags are clear,
caching of memory locations for the whole of physical memory in the
processor's internal (and external) caches is enabled. When the CD flag is
set, caching is restricted as described in Table 11-5. To prevent the processor
from accessing and updating its caches, the CD flag must be set and the
caches must be invalidated so that no cache hits can occur.

NW: Not Write-through (bit 29 of CR0) - When the NW and CD flags are
clear, write-back (for Pentium 4, Intel Xeon, P6 family, and Pentium proces-
sors) or write-through (for Intel486 processors) is enabled for writes that hit
the cache and invalidation cycles are enabled. See Table 11-5 for detailed
information about the affect of the NW flag on caching for other settings of
the CD and NW flags.