[Patch] Add support for UART FIFO status registers
Bug #970252 reported by
Jan Vesely
This bug affects 1 person
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
Linaro QEMU |
Fix Released
|
Low
|
Unassigned |
Bug Description
AM/DM37x Multimedia Device Silicon Revision 1.x Version O Technical Reference Manual page 2951
describes UART RO registers at offsets 0x64 and 0x68, that report FIFO levels.
Using these registers one can monitor the FIFO levels and handle arbitrary number of recieved characters in interrupt handler (wihtout knowing the value of the FIFO trigger level).
The attached patch adds fifo level report for the serial device and uses this functionality in omap_uart device.
Changed in qemu-linaro: | |
status: | Fix Committed → Fix Released |
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Thanks. Do you have a test case for this feature?