FDC reset should reset the MSR

[Benjamin David Lunt]

I believe that the MSR resgister should also be reset to zero on a software reset. All of the FDC hardware I have does this. The current code leaves the MSR as 0x80, which means that the controller is ready for a write. The controller should not be ready for a write while in reset.

fdc.c Line 899
    /* Reset */
    if (!(value & FD_DOR_nRESET)) {
 + fdctrl->msr = 0x00;
        if (fdctrl->dor & FD_DOR_nRESET) {
            FLOPPY_DPRINTF("controller enter RESET state\n");
        }
    } else {

[Anthony Liguori (anthony-codemonkey)]

Is there a test case that this fixes?

[Benjamin David Lunt (bandwconstruction-deactivatedaccount)]

I know of no test case. The reason for the bug report is that I have been doing some studies of the FDC and have noticed that the MSR register is 0x00 during reset. Before and after the reset it is 0x80, but during the reset it is zero. I just wanted to make QEMU more like the hardware.

Thanks,
Ben

[Launchpad Janitor (janitor)]

[Expired for QEMU because there has been no activity for 60 days.]