Need MTTCG support for x86 guests

[Timothy Pearson]

MTTCG support is notably absent for x86_64 guests. The last Wiki update on MTTCG was back in 2015, and I am having some difficulty determining the current status of the underlying requirements to enable this feature on x86 hosts.

For instance, has support for strong-on-weak memory consistency been added into QEMU GIT at this point?

Thanks!

[Emilio G. Cota (cota)]

Patches are now on the list to enable MTTCG for i386 and x86_64 guests. See v2 here:

https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg00237.html

I'm hoping these patches will be in the next QEMU release.

Regarding your last question:
> For instance, has support for strong-on-weak memory consistency been added into QEMU GIT at this point?

Yes, TCG inserts the appropriate barriers around memory accesses since commit b32dc3370a ("tcg: Implement implicit ordering semantics", 2017-09-05)

[Emilio G. Cota (cota)]

This feature is in QEMU v3.1, which was released today.

[Jim Kleckner (jek-ubuntu)]

See the discussion linked below that says that strong on weak is not actually fully supported yet.

Is that discussion correct?

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In short they explained to me that since the host arm64 is a weaker memory order than the guest x86 they disabled mttcg because if they would implement it would slow everything down but the good news is that if the guest is the same memory order it is not disabled and if it is weaker memory order it is not disabled also.

https://github.com/utmapp/UTM/issues/257#issuecomment-612675960

===

Right, that's what I figured from the code. So basically the launchpad comment was incorrect. There is no MTTCG support for x86 on ARM64.

https://github.com/utmapp/UTM/issues/257#issuecomment-612689011

[Emilio G. Cota (cota)]

Looks like support for this was not fully added; my apologies for closing this bug too early.

Adding full support for strong-on-weak emulation would be simple, at least when it comes to memory ordering. The slowdown would be huge though, see Figure 12 in http://www.cs.columbia.edu/~cota/pubs/cota_cgo17.pdf (i.e. ~2x hmean overhead for SPEC).

The good news is that with hardware support this overhead is ~0 (see SAO in that figure).

The other feature that is not yet implemented in upstream QEMU is the correct emulation of LL/SC, although for most code out there this shouldn't be an issue in practice given that most parallel code relies on cmpxchg, not on LL/SC pairs.

I'm reopening this bug an Cc'ing a few people who are more familiar with the current code than I am in case I missed anything.

[Emilio G. Cota (cota)]

OK, looks like I cannot reopen the bug, probably because the bug tracker moved to gitlab.

If you care about this feature, please file a bug over there: https://gitlab.com/qemu-project/qemu/-/issues