pcb

Clearance between traces, increase from default?

Bug #1517473 reported by Nicklas Karlsson
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
pcb
Invalid
Undecided
Unassigned

Bug Description

Clearance between two traces and shown while drawing are wrong. Clearance between copper and trace is however correct.

I expected same clearance value between traces, shown while drawing and copper although values are different.

It only seems to happen then value is increased from default, there seems to some kind of lag. It should be very easy to see the difference if "Cross hair show DRC clearance"/"Auto enforce DRC clearance" is turned on, clearance increased to substantially and drawing a trace adjacent to another inside a copper area.

Revision history for this message
Nicklas Karlsson (nicklas-karlsson17) wrote :
Revision history for this message
Peter Clifton (pcjc2) wrote :

I don't think this is a bug...

The clearance width in polygons is a separate value to the min-copper-spacing DRC rule.

The yellow line you get when drawing traces with "Crosshair shows DRC clearance" enabled, is the DRC rule for min-spacing. The clearance width in polygons is set explicitly in the Route Styles

Changed in pcb:
status: New → Invalid
Revision history for this message
Nicklas Karlsson (nicklas-karlsson17) wrote : Re: [Bug 1517473] Re: Clearance between traces, increase from default?

I consider this a problem to but I am looking at implementing different
clearance values between different nets and think time is better spent
there.

Nicklas Karlsson

2016-02-07 15:05 GMT+01:00 Peter Clifton <
<email address hidden>>:

> I don't think this is a bug...
>
> The clearance width in polygons is a separate value to the min-copper-
> spacing DRC rule.
>
> The yellow line you get when drawing traces with "Crosshair shows DRC
> clearance" enabled, is the DRC rule for min-spacing. The clearance width
> in polygons is set explicitly in the Route Styles
>
> ** Changed in: pcb
> Status: New => Invalid
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1517473
>
> Title:
> Clearance between traces, increase from default?
>
> Status in gEDA project:
> New
> Status in pcb:
> Invalid
>
> Bug description:
> Clearance between two traces and shown while drawing are wrong.
> Clearance between copper and trace is however correct.
>
> I expected same clearance value between traces, shown while drawing
> and copper although values are different.
>
> It only seems to happen then value is increased from default, there
> seems to some kind of lag. It should be very easy to see the
> difference if "Cross hair show DRC clearance"/"Auto enforce DRC
> clearance" is turned on, clearance increased to substantially and
> drawing a trace adjacent to another inside a copper area.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/geda-project/+bug/1517473/+subscriptions
>

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