diff -Nru gcc-4.8-4.8.1/debian/README.Debian gcc-4.8-4.8.2/debian/README.Debian --- gcc-4.8-4.8.1/debian/README.Debian 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/README.Debian 2013-11-29 20:02:23.000000000 +0000 @@ -18,10 +18,11 @@ Ludovic Brenta (gnat) Iain Buclaw (gdc) Aurelien Jarno (mips*-linux) +Aurelien Jarno (s390X*-linux) The following ports lack maintenance in Debian: powerpc, ppc64, -s390, s390x, sparc, sparc64 (unmentioned ports are usually -handled by the Debian porters). +sparc, sparc64 (unmentioned ports are usually handled by the Debian +porters). Former and/or inactive maintainers of these packages ---------------------------------------------------- diff -Nru gcc-4.8-4.8.1/debian/README.Debian.ppc64el gcc-4.8-4.8.2/debian/README.Debian.ppc64el --- gcc-4.8-4.8.1/debian/README.Debian.ppc64el 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/README.Debian.ppc64el 2013-11-29 20:02:23.000000000 +0000 @@ -0,0 +1,265 @@ + The Debian GNU Compiler Collection setup + ======================================== + +Please see the README.Debian in /usr/share/doc/gcc, contained in the +gcc package for a description of the setup of the different compiler +versions. + +For general discussion about the Debian toolchain (GCC, glibc, binutils) +please use the mailing list debian-toolchain@lists.debian.org; for GCC +specific things, please use debian-gcc@lists.debian.org. When in doubt +use the debian-toolchain ML. + + +Maintainers of these packages +----------------------------- + +Matthias Klose +Ludovic Brenta (gnat) +Iain Buclaw (gdc) +Aurelien Jarno (mips*-linux) +Aurelien Jarno (s390X*-linux) + +The following ports lack maintenance in Debian: powerpc, ppc64, +sparc, sparc64 (unmentioned ports are usually handled by the Debian +porters). + +Former and/or inactive maintainers of these packages +---------------------------------------------------- + +Falk Hueffner (alpha-linux) +Ray Dassen +Jeff Bailey (hurd-i386) +Joel Baker (netbsd-i386) +Randolph Chung (ia64-linux) +Philip Blundell (arm-linux) +Ben Collins (sparc-linux) +Dan Jacobowitz (powerpc-linux) +Thiemo Seufer (mips*-linux) +Matt Taggart (hppa-linux) +Gerhard Tonn (s390-linux) +Roman Zippel (m68k-linux) +Arthur Loiret (gdc) + +=============================================================================== + + +svn-updates: + updates from the 4.8 branch upto 20131121 (r205210). + +rename-info-files: + Allow transformations on info file names. Reference the + transformed info file names in the texinfo files. + +gcc-gfdl-build: + Build a dummy s-tm-texi without access to the texinfo sources + +gcc-textdomain: + Set gettext's domain and textdomain to the versioned package name. + +gcc-driver-extra-langs: + Add options and specs for languages that are not built from a source + (but built from separate sources). + +gcc-hash-style-gnu: + Link using --hash-style=gnu (aarch64, alpha, amd64, armel, armhf, ia64, + i386, powerpc, ppc64, s390, sparc) + +libstdc++-pic: + Build and install libstdc++_pic.a library. + +libstdc++-doclink: + adjust hrefs to point to the local documentation + +libstdc++-man-3cxx: + Install libstdc++ man pages with suffix .3cxx instead of .3 + +libstdc++-test-installed: + Add support to run the libstdc++-v3 testsuite using the + installed shared libraries. + +libjava-stacktrace: + libgcj: Lookup source file name and line number in separated + debug files found in /usr/lib/debug + +libjava-jnipath: + - Add /usr/lib/jni and /usr/lib//jni to java.library.path. + - When running the i386 binaries on amd64, look in + - /usr/lib32/gcj-x.y and /usr/lib32/jni instead. + +libjava-sjlj: + Don't try to use _Unwind_Backtrace on SJLJ targets. + See bug #387875, #388505, GCC PR 29206. + +libjava-disable-plugin: + Don't build the gcjwebplugin, even when configured with --enable-plugin + +alpha-no-ev4-directive: + never emit .ev4 directive. + +boehm-gc-getnprocs: + boehm-gc/pthread_support.c (GC_get_nprocs): Use sysconf as fallback. + +note-gnu-stack: + Add .note.GNU-stack sections for gcc's crt files, libffi and boehm-gc + Taken from FC. + +libgomp-omp_h-multilib: + Fix up omp.h for multilibs. + +sparc-force-cpu: + On sparc default to ultrasparc (v9a) in 32bit mode + +pr24619: + Proposed patch for PR mudflap/24619 (instrumentation of dlopen) + +gccgo-version: + Omit the subminor number from the go libdir + +pr47818: + Fix PR ada/47818: Pragma Assert is rejected with No_Implementation_Pragmas restriction. + +pr49944: + apply proposed patch for PR ada/49444. + +gcc-base-version: + Set base version to 4.8, introduce full version 4.8.x. + +libgo-testsuite: + Only run the libgo testsuite for flags configured in RUNTESTFLAGS + +gcc-target-include-asm: + Search $(builddir)/sys-include for the asm header files + +libgo-revert-timeout-exp: + +arm-sanitizer: + Enable libsanitizer on ARM. + +aarch64-libjava: + Build gcj for aarch64-linux-gnu + +libgo-setcontext-config: + libgo: Overwrite the setcontext_clobbers_tls check on mips* + +pr57211: + Fix PR c++/57211, don't warn about unused parameters of defaulted functions. + +gcc-auto-build: + Fix cross building a native compiler. + +kfreebsd-unwind: + +libgcc-no-limits-h: + Don't include in libgcc/libgcc2.c. + +kfreebsd-boehm-gc: + boehm-gc: use mmap instead of brk also on kfreebsd-*. + +pr49847: + +libffi-m68k: + Apply #660525 fix to in-tree libffi + +gotest-elfv2: + +libstdc++-python3: + Make the libstdc++-v3 pretty printer compatible with Python3. + +gdc-updates: + gdc updates up to 20130611. + +gdc-4.8: + This implements D language support in the GCC back end, and adds + relevant documentation about the GDC front end (code part). + +gdc-versym-cpu: + Implements D CPU version conditions. + +gdc-versym-os: + Implements D OS version conditions. + +gdc-frontend-posix: + Fix build of the D frontend on the Hurd and KFreeBSD. + +gdc-4.8-doc: + This implements D language support in the GCC back end, and adds + relevant documentation about the GDC front end (documentation part). + +gdc-driver-nophobos: + Modify gdc driver to have no libphobos by default. + +disable-gdc-tests: + +gcc-ppc64el: + Changes from the ibm/gcc-4_8-branch (20131125) + +libffi-ppc64el: + +gcc-ppc64el-doc: + Changes from the ibm/gcc-4_8-branch (documentation) + +gcc-sysroot: + Allow building --with-sysroot=/ + +ada-kfreebsd: + Fix gnat build failure on kfreebsd. + +arm-multilib-defaults: + Set MULTILIB_DEFAULTS for ARM multilib builds + +gcc-ice-hack: + Retry the build on an ice, save the calling options and preprocessed + source when the ice is reproducible. + +gcc-ice-apport: + Report an ICE to apport (if apport is available + and the environment variable GCC_NOAPPORT is not set) + +libjava-fixed-symlinks: + Remove unneed '..' elements from symlinks in JAVA_HOME + +libstdc++-arm-wno-abi: + Temporary work around: + On arm-linux-gnueabi run the libstdc++v3 testsuite with -Wno-abi + +ada-mips: + Improve support for mips. + +libffi-ro-eh_frame_sect: + PR libffi/47248, force a read only eh frame section. + +gcc-multiarch: + - Remaining multiarch patches, not yet submitted upstream. + - Add MULTIARCH_DIRNAME definitions for multilib configurations, + which are used for the non-multilib builds. + +libjava-multiarch: + Install libjava libraries to multiarch location + +libjava-nobiarch-check: + For biarch builds, disable the testsuite for the non-default architecture + for runtime libraries, which are not built by default (libjava). + +config-ml: + - Disable some biarch libraries for biarch builds. + - Fix multilib builds on kernels which don't support all multilibs. + +g++-multiarch-incdir: + Use /usr/include//c++/4.x as the include directory + for host dependent c++ header files. + +gcc-multilib-multiarch: + Don't auto-detect multilib osdirnames. + +powerpc64le-multilib-definitions: + +gcc-as-needed: + On linux targets pass --as-needed by default to the linker. + +mips-fix-loongson2f-nop: + On mips, pass -mfix-loongson2f-nop to as, if -mno-fix-loongson2f-nop + is not passed. + +libgomp-kfreebsd-testsuite: + Disable lock-2.c test on kfreebsd-* diff -Nru gcc-4.8-4.8.1/debian/README.maintainers gcc-4.8-4.8.2/debian/README.maintainers --- gcc-4.8-4.8.1/debian/README.maintainers 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/README.maintainers 2013-11-29 20:02:23.000000000 +0000 @@ -10,7 +10,7 @@ 3 source packages are: gcc-4.3: C, C++, Fortran, Objective-C and Objective-C++, plus many - common libraries like libssp, libmudflap, and libgcc. + common libraries like libssp and libgcc. gcj-4.3: Java. gnat-4.3: Ada. diff -Nru gcc-4.8-4.8.1/debian/changelog gcc-4.8-4.8.2/debian/changelog --- gcc-4.8-4.8.1/debian/changelog 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/changelog 2013-11-29 20:02:23.000000000 +0000 @@ -1,8 +1,162 @@ -gcc-4.8 (4.8.1-10ubuntu8) saucy; urgency=low +gcc-4.8 (4.8.2-7ubuntu1~saucy1) saucy; urgency=low + * PPA upload for saucy. + + -- Matthias Klose Fri, 29 Nov 2013 20:45:51 +0100 + +gcc-4.8 (4.8.2-7ubuntu1) trusty; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream source. + + -- Matthias Klose Fri, 29 Nov 2013 19:09:33 +0100 + +gcc-4.8 (4.8.2-7) unstable; urgency=low + + * Update to SVN 20131129 (r205535) from the gcc-4_8-branch. + * Introduce aarch64 goarch. + * libgo: Backport fix for calling a function or method that takes or returns + an empty struct via reflection. + * go frontend: Backport fix for the generated hash functions of types that + are aliases for structures containing unexported fields. + * Skip Go testcase on AArch64 which hangs on the buildds. + * Fix freetype includes in libjava/classpath. + + -- Matthias Klose Fri, 29 Nov 2013 18:19:12 +0100 + +gcc-4.8 (4.8.2-6ubuntu2) trusty; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream source. + + -- Matthias Klose Thu, 28 Nov 2013 15:41:43 +0100 + +gcc-4.8 (4.8.2-6) unstable; urgency=low + + * Update to SVN 20131128 (r205478) from the gcc-4_8-branch. + + [ Matthias Klose ] + * gcc-4.8-base: Breaks gcc-4.4-base (<< 4.4.7). Closes: #729963. + * Update the gcc-as-needed patch for mips*. Closes: #722067. + * Use dpkg-vendor information for distribution specific settings. + Closes: #697805. + * Check for the sys/auxv.h header file. + * On AArch64, make the frame grow downwards, taken from the trunk. + Enable ssp on AArch64. + * Pass -fuse-ld=gold to gccgo on targets supporting split-stack. + + [ Aurelien Jarno ] + * Update README.Debian for s390 and s390x. + + [ Thorsten Glaser ] + * m68k-ada.diff: Add gcc-4.8.0-m68k-ada-pr48835-2.patch and + gcc-4.8.0-m68k-ada-pr51483.patch by Mikael Pettersson, to + fix more CC0-specific and m68k/Ada-specific problems. + * m68k-picflag.diff: New, backport from trunk, by Andreas Schwab, + to avoid relocation errors when linking big shared objects. + * pr58369.diff: New, backport from trunk, by Jeffrey A. Law, + to fix ICE while building boost 1.54 on m68k. + * pr52306.diff: Disables -fauto-inc-dec by default on m68k to + work around ICE when building C++ code (e.g. Qt-related). + + -- Matthias Klose Thu, 28 Nov 2013 10:29:09 +0100 + +gcc-4.8 (4.8.2-5ubuntu3) trusty; urgency=low + + * Update to SVN 20131119 (r205005) from the gcc-4_8-branch. + + -- Matthias Klose Tue, 19 Nov 2013 08:12:38 +0100 + +gcc-4.8 (4.8.2-5ubuntu2) trusty; urgency=low + + * Fix build failure on powerpc. + + -- Matthias Klose Mon, 18 Nov 2013 08:14:00 +0100 + +gcc-4.8 (4.8.2-5ubuntu1) trusty; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream source. + + -- Matthias Klose Mon, 18 Nov 2013 06:29:52 +0100 + +gcc-4.8 (4.8.2-5) unstable; urgency=low + + * Update to SVN 20131115 (r204839) from the gcc-4_8-branch. + * Update the Linaro support to the 4.8-2013.11 release. + * Add missing replaces in libgcj14. Closes: #729022. + + -- Matthias Klose Sat, 16 Nov 2013 20:15:09 +0100 + +gcc-4.8 (4.8.2-4ubuntu1) trusty; urgency=low + + * Fix LP #1243656, miscompilation of tar on armhf. + + -- Matthias Klose Wed, 13 Nov 2013 10:12:35 +0100 + +gcc-4.8 (4.8.2-4) unstable; urgency=low + + * Really fix disabling the gdc tests. + + -- Matthias Klose Wed, 13 Nov 2013 00:44:35 +0100 + +gcc-4.8 (4.8.2-3) unstable; urgency=low + + * Update to SVN 20131112 (r204704) from the gcc-4_8-branch. + * Don't ship java.security in both libgcj14 and gcj-4.8-headless. + Closes: #729022. + * Disable gdc tests on architectures without libphobos port. + + -- Matthias Klose Tue, 12 Nov 2013 18:08:44 +0100 + +gcc-4.8 (4.8.2-2ubuntu1) trusty; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream source. + + -- Matthias Klose Thu, 07 Nov 2013 16:27:04 +0100 + +gcc-4.8 (4.8.2-2) unstable; urgency=low + + * Update to SVN 20131017 (r204496) from the gcc-4_8-branch. * Build ObjC, Obj-C++ and Go for AArch64. + * Fix some gcj symlinks. Closes: #726792, #728403. + * Stop building libmudflap (removed in GCC 4.9). + + -- Matthias Klose Thu, 07 Nov 2013 01:40:15 +0100 + +gcc-4.8 (4.8.2-1ubuntu2) trusty; urgency=low + + * Build ObjC, Obj-C++ and Go for AArch64. + + -- Matthias Klose Mon, 21 Oct 2013 00:07:57 +0200 + +gcc-4.8 (4.8.2-1ubuntu1) trusty; urgency=low + + * Merge with Debian; remaining changes: + - Build from the upstream source. + + -- Matthias Klose Wed, 16 Oct 2013 13:43:20 +0200 + +gcc-4.8 (4.8.2-1) unstable; urgency=low + + * GCC 4.8.2 release. + + * Update to SVN 20131017 (r203751) from the gcc-4_8-branch. + * Update the Linaro support to the 4.8-2013.10 release. + * Fix PR c++/57850, option -fdump-translation-unit not working. + * Don't run the testsuite on aarch64. + * Fix PR target/58578, wrong-code regression on ARM. LP: #1232017. + * [ARM] Fix bug in add patterns due to commutativity modifier, + backport from trunk. LP: #1234060. + * Build libatomic on AArch64. + * Fix dependency generation for the cross gcc-4.8 package. + * Make the libstdc++ pretty printers compatible with Python3, if + gdb is built with Python3 support. + * Fix loading of libstdc++ pretty printers. Closes: #701935. + * Don't let gcc-snapshot build-depend on gnat on AArch64. - -- Matthias Klose Sat, 12 Oct 2013 03:25:36 +0200 + -- Matthias Klose Thu, 17 Oct 2013 14:37:55 +0200 gcc-4.8 (4.8.1-10ubuntu7) saucy; urgency=low diff -Nru gcc-4.8-4.8.1/debian/control gcc-4.8-4.8.2/debian/control --- gcc-4.8-4.8.1/debian/control 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/control 2013-11-29 20:02:23.000000000 +0000 @@ -16,7 +16,7 @@ texinfo (>= 4.3), locales, sharutils, procps, zlib1g-dev, libantlr-java, python, libffi-dev, fastjar, libmagic-dev, libecj-java (>= 3.3.0-2), zip, libasound2-dev [ !hurd-any !kfreebsd-any], libxtst-dev, libxt-dev, libgtk2.0-dev (>= 2.4.4-2), libart-2.0-dev, libcairo2-dev, g++-4.8 [armel armhf], netbase, libcloog-isl-dev (>= 0.18), libmpc-dev (>= 1.0), libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), - dejagnu [!arm64 !m68k !hurd-amd64 !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, quilt + dejagnu [!m68k !hurd-amd64 !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, quilt Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, Homepage: http://gcc.gnu.org/ XS-Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-4.8/ @@ -29,7 +29,7 @@ Priority: required Depends: ${misc:Depends} Replaces: ${base:Replaces} -Breaks: gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) +Breaks: gcc-4.4-base (<< 4.4.7), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries contained in the GNU Compiler Collection (GCC). @@ -296,7 +296,7 @@ binutils (>= ${binutils:Version}), libgcc-4.8-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} -Suggests: ${gcc:multilib}, libmudflap0-4.8-dev (= ${gcc:Version}), gcc-4.8-doc (>= ${gcc:SoftVersion}), gcc-4.8-locales (>= ${gcc:SoftVersion}), libgcc1-dbg (>= ${libgcc:Version}), libgomp1-dbg (>= ${gcc:Version}), libitm1-dbg (>= ${gcc:Version}), libatomic1-dbg (>= ${gcc:Version}), libasan0-dbg (>= ${gcc:Version}), libtsan0-dbg (>= ${gcc:Version}), libbacktrace1-dbg (>= ${gcc:Version}), libquadmath0-dbg (>= ${gcc:Version}), libmudflap0-dbg (>= ${gcc:Version}), ${dep:libcloog}, ${dep:gold} +Suggests: ${gcc:multilib}, gcc-4.8-doc (>= ${gcc:SoftVersion}), gcc-4.8-locales (>= ${gcc:SoftVersion}), libgcc1-dbg (>= ${libgcc:Version}), libgomp1-dbg (>= ${gcc:Version}), libitm1-dbg (>= ${gcc:Version}), libatomic1-dbg (>= ${gcc:Version}), libasan0-dbg (>= ${gcc:Version}), libtsan0-dbg (>= ${gcc:Version}), libbacktrace1-dbg (>= ${gcc:Version}), libquadmath0-dbg (>= ${gcc:Version}), ${dep:libcloog}, ${dep:gold} Provides: c-compiler Description: GNU C compiler This is the GNU C compiler, a fairly portable optimizing compiler for C. @@ -306,7 +306,6 @@ Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gcc-4.8 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends} -Suggests: ${dep:libmudflapbiarch} Description: GNU C compiler (multilib files) This is the GNU C compiler, a fairly portable optimizing compiler for C. . @@ -389,160 +388,6 @@ On architectures with multilib support, the package contains files and dependencies for the non-default multilib architecture(s). -Package: libmudflap0 -Architecture: any -Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -Provides: libmudflap0-armel [armel], libmudflap0-armhf [armhf] -Section: libs -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: GCC mudflap shared support libraries - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libmudflap0-dbg -Architecture: any -Multi-Arch: same -Provides: libmudflap0-dbg-armel [armel], libmudflap0-dbg-armhf [armhf] -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), libmudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap0 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el -Section: libs -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Conflicts: ${confl:lib32} -Description: GCC mudflap shared support libraries (32bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), lib32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (32 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap0 -Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 -Section: libs -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (64bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), lib64mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (64 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap0 -Architecture: mips mipsel mips64 mips64el -Section: libs -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (n32) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap0-dbg -Architecture: mips mipsel mips64 mips64el -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), libn32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (n32 debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libx32mudflap0 -Architecture: amd64 i386 -Section: libs -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Description: GCC mudflap shared support libraries (x32) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libx32mudflap0-dbg -Architecture: amd64 i386 -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), libx32mudflap0 (= ${gcc:Version}), ${misc:Depends} -Description: GCC mudflap shared support libraries (x32 debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap0 -Architecture: armel -Section: libs -Priority: optional -Conflicts: libmudflap0-armhf [armel] -Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Description: GCC mudflap shared support libraries (hard float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap0-dbg -Architecture: armel -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), libhfmudflap0 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap0-dbg-armhf [armel] -Description: GCC mudflap shared support libraries (hard float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap0 -Architecture: armhf -Section: libs -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Conflicts: libmudflap0-armel [armhf] -Description: GCC mudflap shared support libraries (soft float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap0-dbg -Architecture: armhf -Section: debug -Priority: extra -Depends: gcc-4.8-base (= ${gcc:Version}), libsfmudflap0 (= ${gcc:Version}), ${misc:Depends} -Conflicts: libmudflap0-dbg-armel [armhf] -Description: GCC mudflap shared support libraries (soft float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libmudflap0-4.8-dev -Architecture: any -Section: libdevel -Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), libmudflap0 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} -Suggests: ${sug:libmudflapdev} -Conflicts: libmudflap0-dev -Description: GCC mudflap support libraries (development files) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - . - This package contains the headers and the static libraries. - Package: libgomp1 Section: libs Architecture: any @@ -1905,6 +1750,7 @@ Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gcj-4.8-jre-headless (= ${gcj:Version}), libgcj14-awt (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime +Replaces: gcj-4.8-jre-headless (<< 4.8.2-2) Description: Java runtime environment using GIJ/Classpath GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. It includes a class loader which can dynamically load shared objects, so @@ -1923,7 +1769,7 @@ Depends: gcc-4.8-base (>= ${gcc:SoftVersion}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} Recommends: gcj-4.8-jre-lib (>= ${gcj:SoftVersion}) Suggests: libgcj14-dbg (>= ${gcc:Version}), libgcj14-awt (= ${gcj:Version}) -Replaces: gij-4.4 (<< 4.4.0-1) +Replaces: gij-4.4 (<< 4.4.0-1), gcj-4.8-jre-headless (<< 4.8.2-5) Description: Java runtime library for use with gcj This is the runtime that goes along with the gcj front end to gcc. libgcj includes parts of the Java Class Libraries, plus glue to diff -Nru gcc-4.8-4.8.1/debian/control.m4 gcc-4.8-4.8.2/debian/control.m4 --- gcc-4.8-4.8.1/debian/control.m4 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/control.m4 2013-11-29 20:02:23.000000000 +0000 @@ -18,6 +18,7 @@ ') define(`MAINTAINER', `Debian GCC Maintainers ') +define(`depifenabled', `ifelse(index(enabled_languages, `$1'), -1, `', `$2')') define(`ifenabled', `ifelse(index(enabled_languages, `$1'), -1, `dnl', `$2')') define(`CROSS_ARCH', ifdef(`CROSS_ARCH', CROSS_ARCH, `all')) @@ -135,7 +136,7 @@ Priority: PRI(required) Depends: ${misc:Depends} Replaces: ${base:Replaces} -Breaks: gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) +Breaks: gcc-4.4-base (<< 4.4.7), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~), dehydra (<= 0.9.hg20110609-2) BUILT_USING`'dnl Description: GCC, the GNU Compiler Collection (base package) This package contains files common to all languages and libraries @@ -701,9 +702,9 @@ Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: cpp`'PV`'TS (= ${gcc:Version}),ifenabled(`gccbase',` BASEDEP,') binutils`'TS (>= ${binutils:Version}), - ifenabled(`libgcc',`libdevdep(gcc`'PV-dev`',), ')${shlibs:Depends}, ${misc:Depends} + depifenabled(`libgcc',`libdevdep(gcc`'PV-dev`',), ')${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} -Suggests: ${gcc:multilib}, libdevdep(mudflap`'MF_SO`'PV-dev,,=), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), libdbgdep(gomp`'GOMP_SO-dbg,), libdbgdep(itm`'ITM_SO-dbg,), libdbgdep(atomic`'ATOMIC_SO-dbg,), libdbgdep(asan`'ASAN_SO-dbg,), libdbgdep(tsan`'TSAN_SO-dbg,), libdbgdep(backtrace`'BTRACE_SO-dbg,), libdbgdep(quadmath`'QMATH_SO-dbg,), libdbgdep(mudflap`'MF_SO-dbg,), ${dep:libcloog}, ${dep:gold} +Suggests: ${gcc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), libdbgdep(gomp`'GOMP_SO-dbg,), libdbgdep(itm`'ITM_SO-dbg,), libdbgdep(atomic`'ATOMIC_SO-dbg,), libdbgdep(asan`'ASAN_SO-dbg,), libdbgdep(tsan`'TSAN_SO-dbg,), libdbgdep(backtrace`'BTRACE_SO-dbg,), libdbgdep(quadmath`'QMATH_SO-dbg,), ${dep:libcloog}, ${dep:gold} Provides: c-compiler`'TS BUILT_USING`'dnl Description: GNU C compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') @@ -719,7 +720,6 @@ Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends} -Suggests: ${dep:libmudflapbiarch} BUILT_USING`'dnl Description: GNU C compiler (multilib files)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `') This is the GNU C compiler, a fairly portable optimizing compiler for C. @@ -836,185 +836,6 @@ ')`'dnl c++dev ')`'dnl c++ -ifenabled(`mudflap',` -ifenabled(`libmudf',` -Package: libmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') -ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same -Pre-Depends: multiarch-support -Breaks: ${multiarch:breaks} -')`Provides: libmudflap'MF_SO`-armel [armel], libmudflap'MF_SO`-armhf [armhf]') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') -ifdef(`TARGET',`dnl',ifdef(`MULTIARCH', `Multi-Arch: same -')`Provides: libmudflap'MF_SO`-dbg-armel [armel], libmudflap'MF_SO`-dbg-armhf [armhf]') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,,=), ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -Conflicts: ${confl:lib32} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (32bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,32,=), ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (32 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (64bit) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: lib64mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,64,=), ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (64 bit debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (n32) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libn32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,n32,=), ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (n32 debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -ifenabled(`libx32mudflap',` -Package: libx32mudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -Replaces: libmudflap0 (<< 4.1) -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (x32) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libx32mudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,x32,=), ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (x32 debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. -')`'dnl libx32mudflap - -ifenabled(`libhfmudflap',` -Package: libhfmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-armhf [biarchhf_archs]') -Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (hard float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libhfmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,hf,=), ${misc:Depends} -ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-dbg-armhf [biarchhf_archs]') -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (hard float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. -')`'dnl libhfmudflap - -ifenabled(`libsfmudflap',` -Package: libsfmudflap`'MF_SO`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') -Section: ifdef(`TARGET',`devel',`libs') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} -ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-armel [biarchsf_archs]') -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (soft float) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - -Package: libsfmudflap`'MF_SO-dbg`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs') -Section: debug -Priority: extra -Depends: BASEDEP, libdep(mudflap`'MF_SO,sf,=), ${misc:Depends} -ifdef(`TARGET',`dnl',`Conflicts: libmudflap`'MF_SO`'-dbg-armel [biarchsf_archs]') -BUILT_USING`'dnl -Description: GCC mudflap shared support libraries (soft float debug symbols) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. -')`'dnl libsfmudflap -')`'dnl libmudf - -Package: libmudflap`'MF_SO`'PV-dev`'LS -Architecture: ifdef(`TARGET',`CROSS_ARCH',`any') -Section: ifdef(`TARGET',`devel',`libdevel') -Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, libdevdep(mudflap`'MF_SO,,>=,${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends} -Suggests: ${sug:libmudflapdev} -Conflicts: libmudflap0-dev -BUILT_USING`'dnl -Description: GCC mudflap support libraries (development files) - The libmudflap libraries are used by GCC for instrumenting pointer and array - dereferencing operations. - . - This package contains the headers and the static libraries. -')`'dnl mudflap - ifdef(`TARGET', `', ` ifenabled(`ssp',` Package: libssp`'SSP_SO`'LS @@ -3160,6 +2981,7 @@ Priority: ifdef(`TARGET',`extra',`PRI(optional)') Depends: BASEDEP, gcj`'PV-jre-headless`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends} Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime +Replaces: gcj-4.8-jre-headless`'TS (<< 4.8.2-2) BUILT_USING`'dnl Description: Java runtime environment using GIJ/Classpath GIJ is a Java bytecode interpreter, not limited to interpreting bytecode. @@ -3180,7 +3002,7 @@ Depends: SOFTBASEDEP, libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends} Recommends: gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}) Suggests: libdbgdep(gcj`'GCJ_SO-dbg,), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}) -Replaces: gij-4.4 (<< 4.4.0-1) +Replaces: gij-4.4 (<< 4.4.0-1), gcj-4.8-jre-headless`'TS (<< 4.8.2-5) BUILT_USING`'dnl Description: Java runtime library for use with gcj This is the runtime that goes along with the gcj front end to @@ -4094,7 +3916,7 @@ Package: gcc`'PV-soft-float Architecture: arm armel armhf Priority: PRI(optional) -Depends: BASEDEP, ifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends} +Depends: BASEDEP, depifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends} Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float BUILT_USING`'dnl Description: GCC soft-floating-point gcc libraries (ARM) diff -Nru gcc-4.8-4.8.1/debian/libmudflap.copyright gcc-4.8-4.8.2/debian/libmudflap.copyright --- gcc-4.8-4.8.1/debian/libmudflap.copyright 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/libmudflap.copyright 1970-01-01 00:00:00.000000000 +0000 @@ -1,30 +0,0 @@ -This package was debianized by Matthias Klose on -Mon, 5 Jul 2004 21:29:57 +0200 - -Mudflap is part of GCC. - -Authors: Frank Ch. Eigler , Graydon Hoare - -Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2, or (at your option) any later -version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file into combinations with other programs, -and to distribute those combinations without any restriction coming -from the use of this file. (The General Public License restrictions -do apply in other respects; for example, they cover modification of -the file, and distribution when not linked into a combine -executable.) - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -On Debian GNU/Linux systems, the complete text of the GNU General -Public License can be found in `/usr/share/common-licenses/GPL'. diff -Nru gcc-4.8-4.8.1/debian/libmudflapMF.postinst gcc-4.8-4.8.2/debian/libmudflapMF.postinst --- gcc-4.8-4.8.1/debian/libmudflapMF.postinst 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/libmudflapMF.postinst 1970-01-01 00:00:00.000000000 +0000 @@ -1,12 +0,0 @@ -#! /bin/sh - -set -e - -case "$1" in configure) - if [ -d /usr/share/doc/libmudflap@MF@ ] && [ ! -h /usr/share/doc/libmudflap@MF@ ]; then - rm -rf /usr/share/doc/libmudflap@MF@ - ln -s gcc-@BV@-base /usr/share/doc/libmudflap@MF@ - fi -esac - -#DEBHELPER# diff -Nru gcc-4.8-4.8.1/debian/patches/arm-fix-add-pattern.diff gcc-4.8-4.8.2/debian/patches/arm-fix-add-pattern.diff --- gcc-4.8-4.8.1/debian/patches/arm-fix-add-pattern.diff 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/arm-fix-add-pattern.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,42 +0,0 @@ -# DP: [ARM] Fix bug in add patterns due to commutativity modifier, -# DP: backport from trunk. - -2013-07-25 Kyrylo Tkachov - - * config/arm/arm.md (arm_addsi3, addsi3_carryin_, - addsi3_carryin_alt2_): Correct output template. - ---- a/src/gcc/config/arm/arm.md -+++ b/src/gcc/config/arm/arm.md -@@ -960,10 +960,10 @@ - "@ - add%?\\t%0, %0, %2 - add%?\\t%0, %1, %2 -- add%?\\t%0, %2 - add%?\\t%0, %1, %2 - add%?\\t%0, %1, %2 - add%?\\t%0, %1, %2 -+ add%?\\t%0, %1, %2 - add%?\\t%0, %2, %1 - addw%?\\t%0, %1, %2 - addw%?\\t%0, %1, %2 -@@ -1247,8 +1247,8 @@ - (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] - "TARGET_32BIT" - "@ -- adc%?\\t%0, %1 - adc%?\\t%0, %1, %2 -+ adc%?\\t%0, %1, %2 - sbc%?\\t%0, %1, #%B2" - [(set_attr "conds" "use") - (set_attr "predicable" "yes") -@@ -1264,8 +1264,8 @@ - (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))] - "TARGET_32BIT" - "@ -- adc%?\\t%0, %1 - adc%?\\t%0, %1, %2 -+ adc%?\\t%0, %1, %2 - sbc%?\\t%0, %1, #%B2" - [(set_attr "conds" "use") - (set_attr "predicable" "yes") diff -Nru gcc-4.8-4.8.1/debian/patches/disable-gdc-tests.diff gcc-4.8-4.8.2/debian/patches/disable-gdc-tests.diff --- gcc-4.8-4.8.1/debian/patches/disable-gdc-tests.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/disable-gdc-tests.diff 2013-11-29 20:02:23.000000000 +0000 @@ -0,0 +1,13 @@ +--- a/src/gcc/d/Make-lang.in ++++ b/src/gcc/d/Make-lang.in +@@ -358,8 +358,8 @@ + # entry point. We feed the former to the latter here. + check-d: check-gdc + # List of targets that can use the generic check- rule and its // variant. +-lang_checks += check-gdc +-lang_checks_parallelized += check-gdc ++#lang_checks += check-gdc ++#lang_checks_parallelized += check-gdc + # For description see comment above check_gcc_parallelize in gcc/Makefile.in. + check_gdc_parallelize = d_do_test.exp=runnable/* + diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-aarch64-frame-down.diff gcc-4.8-4.8.2/debian/patches/gcc-aarch64-frame-down.diff --- gcc-4.8-4.8.1/debian/patches/gcc-aarch64-frame-down.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-aarch64-frame-down.diff 2013-11-29 20:02:23.000000000 +0000 @@ -0,0 +1,56 @@ +gcc/ + +2013-11-13 Christophe Lyon + + * config/aarch64/aarch64.h (FRAME_GROWS_DOWNWARD): Define to 1. + * config/aarch64/aarch64.c (aarch64_initial_elimination_offset): + Update offset calculations. + +--- a/src/gcc/config/aarch64/aarch64.c ++++ b/src/gcc/config/aarch64/aarch64.c +@@ -2010,7 +2010,7 @@ + Establish the stack frame by decreasing the stack pointer with a + properly calculated size and, if necessary, create a frame record + filled with the values of LR and previous frame pointer. The +- current FP is also set up is it is in use. */ ++ current FP is also set up if it is in use. */ + + void + aarch64_expand_prologue (void) +@@ -4143,7 +4143,7 @@ + return offset - crtl->outgoing_args_size; + + if (from == FRAME_POINTER_REGNUM) +- return cfun->machine->frame.saved_regs_size; ++ return cfun->machine->frame.saved_regs_size + get_frame_size (); + } + + if (to == STACK_POINTER_REGNUM) +@@ -4152,6 +4152,7 @@ + { + HOST_WIDE_INT elim = crtl->outgoing_args_size + + cfun->machine->frame.saved_regs_size ++ + get_frame_size () + - cfun->machine->frame.fp_lr_offset; + elim = AARCH64_ROUND_UP (elim, STACK_BOUNDARY / BITS_PER_UNIT); + return elim; +--- a/src/gcc/config/aarch64/aarch64.h ++++ b/src/gcc/config/aarch64/aarch64.h +@@ -443,7 +443,7 @@ + #define INDEX_REG_CLASS CORE_REGS + #define BASE_REG_CLASS POINTER_REGS + +-/* Register pairs used to eliminate unneeded registers that point intoi ++/* Register pairs used to eliminate unneeded registers that point into + the stack frame. */ + #define ELIMINABLE_REGS \ + { \ +@@ -484,7 +484,7 @@ + /* Stack layout; function entry, exit and calling. */ + #define STACK_GROWS_DOWNWARD 1 + +-#define FRAME_GROWS_DOWNWARD 0 ++#define FRAME_GROWS_DOWNWARD 1 + + #define STARTING_FRAME_OFFSET 0 + diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-as-needed.diff gcc-4.8-4.8.2/debian/patches/gcc-as-needed.diff --- gcc-4.8-4.8.1/debian/patches/gcc-as-needed.diff 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-as-needed.diff 2013-11-29 20:02:23.000000000 +0000 @@ -132,6 +132,26 @@ %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ SUBTARGET_EXTRA_LINK_SPEC +--- a/src/gcc/config/mips/gnu-user.h ++++ b/src/gcc/config/mips/gnu-user.h +@@ -56,6 +56,7 @@ + #undef GNU_USER_TARGET_LINK_SPEC + #define GNU_USER_TARGET_LINK_SPEC \ + "%(endian_spec) \ ++ -as-needed \ + %{shared:-shared} \ + %{!shared: \ + %{!static: \ +--- a/src/gcc/config/mips/gnu-user64.h ++++ b/src/gcc/config/mips/gnu-user64.h +@@ -34,6 +34,7 @@ + #define GNU_USER_TARGET_LINK_SPEC "\ + %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ + %{shared} \ ++ -as-needed \ + %(endian_spec) \ + %{!shared: \ + %{!static: \ --- a/src/libjava/Makefile.am +++ b/src/libjava/Makefile.am @@ -625,7 +625,7 @@ diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-base-version.diff gcc-4.8-4.8.2/debian/patches/gcc-base-version.diff --- gcc-4.8-4.8.1/debian/patches/gcc-base-version.diff 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-base-version.diff 2013-11-29 20:02:23.000000000 +0000 @@ -5,14 +5,14 @@ --- a/src/gcc/BASE-VER +++ b/src/gcc/BASE-VER @@ -1 +1 @@ --4.8.1 +-4.8.2 +4.8 Index: b/src/gcc/FULL-VER =================================================================== --- /dev/null +++ b/src/gcc/FULL-VER @@ -0,0 +1 @@ -+4.8.1 ++4.8.2 Index: b/src/gcc/Makefile.in =================================================================== --- a/src/gcc/Makefile.in diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-linaro-doc.diff gcc-4.8-4.8.2/debian/patches/gcc-linaro-doc.diff --- gcc-4.8-4.8.1/debian/patches/gcc-linaro-doc.diff 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-linaro-doc.diff 2013-11-29 20:02:23.000000000 +0000 @@ -1,4 +1,4 @@ -# DP: Changes for the Linaro 4.8-2013.09 release (documentation). +# DP: Changes for the Linaro 4.8-2013.11 release (documentation). --- a/src/gcc/doc/tm.texi +++ b/src/gcc/doc/tm.texi @@ -54,7 +54,16 @@ @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol -@@ -11263,8 +11265,8 @@ +@@ -10966,6 +10968,8 @@ + the following: + + @table @samp ++@item crc ++Enable CRC extension. + @item crypto + Enable Crypto extension. This implies Advanced SIMD is enabled. + @item fp +@@ -11263,8 +11267,8 @@ @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @@ -65,7 +74,7 @@ @samp{cortex-m1}, @samp{cortex-m0}, @samp{cortex-m0plus}, -@@ -11527,6 +11529,17 @@ +@@ -11527,6 +11531,17 @@ preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be defined. diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-linaro.diff gcc-4.8-4.8.2/debian/patches/gcc-linaro.diff --- gcc-4.8-4.8.1/debian/patches/gcc-linaro.diff 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-linaro.diff 2013-11-29 20:02:23.000000000 +0000 @@ -1,12 +1,16 @@ -# DP: Changes for the Linaro 4.8-2013.09 release. +# DP: Changes for the Linaro 4.8-2013.11 release. -LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@202157 \ - svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@202502 \ +LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@204657 \ + svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@204811 \ | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ --- a/src/libitm/ChangeLog.linaro +++ b/src/libitm/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -36,7 +40,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgomp/ChangeLog.linaro +++ b/src/libgomp/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -82,7 +90,11 @@ use omp_lib --- a/src/libquadmath/ChangeLog.linaro +++ b/src/libquadmath/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -125,7 +137,11 @@ current_++; --- a/src/libsanitizer/ChangeLog.linaro +++ b/src/libsanitizer/ChangeLog.linaro -@@ -0,0 +1,42 @@ +@@ -0,0 +1,46 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -181,7 +197,11 @@ ;; --- a/src/zlib/ChangeLog.linaro +++ b/src/zlib/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -211,7 +231,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libstdc++-v3/ChangeLog.linaro +++ b/src/libstdc++-v3/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -241,7 +265,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/intl/ChangeLog.linaro +++ b/src/intl/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -271,7 +299,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/ChangeLog.linaro +++ b/src/ChangeLog.linaro -@@ -0,0 +1,37 @@ +@@ -0,0 +1,41 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -311,7 +343,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libmudflap/ChangeLog.linaro +++ b/src/libmudflap/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -341,7 +377,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/boehm-gc/ChangeLog.linaro +++ b/src/boehm-gc/ChangeLog.linaro -@@ -0,0 +1,40 @@ +@@ -0,0 +1,44 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -452,7 +492,11 @@ # define MACH_TYPE "ARM32" --- a/src/include/ChangeLog.linaro +++ b/src/include/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -482,7 +526,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libiberty/ChangeLog.linaro +++ b/src/libiberty/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -512,7 +560,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/lto-plugin/ChangeLog.linaro +++ b/src/lto-plugin/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -542,7 +594,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/regression/ChangeLog.linaro +++ b/src/contrib/regression/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -584,7 +640,11 @@ arm-linux-androideabi arm-uclinux_eabi arm-eabi \ --- a/src/contrib/ChangeLog.linaro +++ b/src/contrib/ChangeLog.linaro -@@ -0,0 +1,34 @@ +@@ -0,0 +1,38 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -621,7 +681,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/reghunt/ChangeLog.linaro +++ b/src/contrib/reghunt/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -651,7 +715,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libatomic/ChangeLog.linaro +++ b/src/libatomic/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -681,7 +749,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/config/ChangeLog.linaro +++ b/src/config/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -711,7 +783,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libbacktrace/ChangeLog.linaro +++ b/src/libbacktrace/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -741,7 +817,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/libltdl/ChangeLog.linaro +++ b/src/libjava/libltdl/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -771,7 +851,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/ChangeLog.linaro +++ b/src/libjava/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -801,7 +885,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/classpath/ChangeLog.linaro +++ b/src/libjava/classpath/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -831,7 +919,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gnattools/ChangeLog.linaro +++ b/src/gnattools/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -861,7 +953,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/maintainer-scripts/ChangeLog.linaro +++ b/src/maintainer-scripts/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -891,7 +987,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgcc/ChangeLog.linaro +++ b/src/libgcc/ChangeLog.linaro -@@ -0,0 +1,37 @@ +@@ -0,0 +1,41 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -944,7 +1044,11 @@ typedef int TItype __attribute__ ((mode (TI))); --- a/src/libgcc/config/libbid/ChangeLog.linaro +++ b/src/libgcc/config/libbid/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -974,7 +1078,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libdecnumber/ChangeLog.linaro +++ b/src/libdecnumber/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -1005,7 +1113,7 @@ --- a/src/gcc/LINARO-VERSION +++ b/src/gcc/LINARO-VERSION @@ -0,0 +1 @@ -+4.8-2013.09 ++4.8-2013.10-1~dev --- a/src/gcc/hooks.c +++ b/src/gcc/hooks.c @@ -147,6 +147,14 @@ @@ -1035,7 +1143,11 @@ HOST_WIDE_INT, --- a/src/gcc/c-family/ChangeLog.linaro +++ b/src/gcc/c-family/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -1065,7 +1177,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/java/ChangeLog.linaro +++ b/src/gcc/java/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -1095,7 +1211,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/c/ChangeLog.linaro +++ b/src/gcc/c/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -1185,6 +1305,18 @@ fi +@@ -25913,8 +25914,9 @@ + # ??? Once 2.11 is released, probably need to add first known working + # version to the per-target configury. + case "$cpu_type" in +- alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze | mips \ +- | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 | xtensa) ++ aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ ++ | mips | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 \ ++ | xtensa) + insn="nop" + ;; + ia64 | s390) --- a/src/gcc/gensupport.c +++ b/src/gcc/gensupport.c @@ -1717,6 +1717,21 @@ @@ -1211,7 +1343,7 @@ alternatives, max_operand); --- a/src/gcc/fold-const.c +++ b/src/gcc/fold-const.c -@@ -2457,9 +2457,13 @@ +@@ -2474,9 +2474,13 @@ } if (TREE_CODE (arg0) != TREE_CODE (arg1) @@ -1230,7 +1362,11 @@ return 0; --- a/src/gcc/objc/ChangeLog.linaro +++ b/src/gcc/objc/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -1260,7 +1396,231 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ChangeLog.linaro +++ b/src/gcc/ChangeLog.linaro -@@ -0,0 +1,2457 @@ +@@ -0,0 +1,2681 @@ ++2013-11-06 Christophe Lyon ++ ++ Revert backport from trunk r197526. ++ 2013-04-05 Greta Yorsh ++ ++ * config/arm/arm.md (negdi_extendsidi): New pattern. ++ (negdi_zero_extendsidi): Likewise. ++ ++2013-11-05 Zhenqiang Chen ++ ++ Backport from trunk r203267, r203603 and r204247. ++ 2013-10-08 Zhenqiang Chen ++ ++ PR target/58423 ++ * config/arm/arm.c (arm_emit_ldrd_pop): Attach ++ RTX_FRAME_RELATED_P on INSN. ++ ++ 2013-10-15 Matthew Gretton-Dann ++ Ramana Radhakrishnan ++ ++ * config/arm/t-aprofile: New file. ++ * config.gcc: Handle --with-multilib-list option. ++ ++ 2013-10-31 Zhenqiang Chen ++ ++ * lower-subreg.c (resolve_simple_move): Copy REG_INC note. ++ ++2013-10-17 Christophe Lyon ++ ++ Backport from trunk r200956 ++ 2013-07-15 Marcus Shawcroft ++ ++ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): ++ Define SYMBOL_TINY_GOT, update comment. ++ * config/aarch64/aarch64.c ++ (aarch64_load_symref_appropriately): Handle SYMBOL_TINY_GOT. ++ (aarch64_expand_mov_immediate): Likewise. ++ (aarch64_print_operand): Likewise. ++ (aarch64_classify_symbol): Likewise. ++ * config/aarch64/aarch64.md (UNSPEC_GOTTINYPIC): Define. ++ (ldr_got_tiny): Define. ++ ++2013-10-16 Christophe Lyon ++ ++ * LINARO-VERSION: Bump version. ++ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ ++2013-10-09 Christophe Lyon ++ ++ Backport from trunk r198526,198527,200020,200595. ++ 2013-05-02 Ian Bolton ++ ++ * config/aarch64/aarch64.md (*and_one_cmpl3_compare0): ++ New pattern. ++ (*and_one_cmplsi3_compare0_uxtw): Likewise. ++ (*and_one_cmpl_3_compare0): Likewise. ++ (*and_one_cmpl_si3_compare0_uxtw): Likewise. ++ ++ 2013-05-02 Ian Bolton ++ ++ * config/aarch64/aarch64.md (movsi_aarch64): Only allow to/from ++ S reg when fp attribute set. ++ (movdi_aarch64): Only allow to/from D reg when fp attribute set. ++ ++ 2013-06-12 Sofiane Naci ++ ++ * config/aarch64/aarch64-simd.md (aarch64_combine): convert to split. ++ (aarch64_simd_combine): New instruction expansion. ++ * config/aarch64/aarch64-protos.h (aarch64_split_simd_combine): New ++ function prototype. ++ * config/aarch64/aarch64.c (aarch64_split_combine): New function. ++ * config/aarch64/iterators.md (Vdbl): Add entry for DF. ++ ++ 2013-07-02 Ian Bolton ++ ++ * config/aarch64/aarch64.md (*extr_insv_reg): New pattern. ++ ++2013-10-09 Christophe Lyon ++ ++ Backport from trunk r201879. ++ 2013-08-20 Matthew Gretton-Dann ++ ++ * config/arm/linux-elf.h (MULTILIB_DEFAULTS): Remove definition. ++ * config/arm/t-linux-eabi (MULTILIB_OPTIONS): Document association ++ with MULTLIB_DEFAULTS. ++ ++2013-10-09 Christophe Lyon ++ ++ Backport from trunk r201871. ++ 2013-08-20 Pavel Chupin ++ ++ Fix LIB_SPEC for systems without libpthread. ++ ++ * config/gnu-user.h: Introduce GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC. ++ * config/arm/linux-eabi.h: Use GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC ++ for Android. ++ * config/i386/linux-common.h: Likewise. ++ * config/mips/linux-common.h: Likewise. ++ ++2013-10-08 Christophe Lyon ++ ++ Backport from trunk r202702. ++ 2013-09-18 Richard Earnshaw ++ ++ * arm.c (arm_get_frame_offsets): Validate architecture supports ++ LDRD/STRD before accepting the tuning preference. ++ (arm_expand_prologue): Likewise. ++ (arm_expand_epilogue): Likewise. ++ ++2013-10-04 Venkataramanan.Kumar ++ ++ Backport from trunk r203028. ++ 2013-09-30 Venkataramanan Kumar ++ ++ * config/aarch64/aarch64.h (MCOUNT_NAME): Define. ++ (NO_PROFILE_COUNTERS): Likewise. ++ (PROFILE_HOOK): Likewise. ++ (FUNCTION_PROFILER): Likewise. ++ * config/aarch64/aarch64.c (aarch64_function_profiler): Remove. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r201923,201927. ++ 2013-08-22 Julian Brown ++ ++ * configure.ac: Add aarch64 to list of arches which use "nop" in ++ debug_line test. ++ * configure: Regenerate. ++ ++ 2013-08-22 Paolo Carlini ++ ++ * configure.ac: Add backslashes missing from the last change. ++ * configure: Regenerate. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202023,202108. ++ 2013-08-27 Tejas Belagod ++ ++ * config/aarch64/arm_neon.h: Replace all inline asm implementations ++ of vget_low_* with implementations in terms of other intrinsics. ++ ++ 2013-08-30 Tejas Belagod ++ ++ * config/aarch64/arm_neon.h (__AARCH64_UINT64_C, __AARCH64_INT64_C): New ++ arm_neon.h's internal macros to specify 64-bit constants. Avoid using ++ stdint.h's macros. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r201260,202400. ++ 2013-07-26 Kyrylo Tkachov ++ Richard Earnshaw ++ ++ * combine.c (simplify_comparison): Re-canonicalize operands ++ where appropriate. ++ * config/arm/arm.md (movcond_addsi): New splitter. ++ ++ 2013-09-09 Kyrylo Tkachov ++ ++ * config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for ++ comparison with negated operand. ++ * config/aarch64/aarch64.md (compare_neg): Match canonical ++ RTL form. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202164. ++ 2013-09-02 Bin Cheng ++ ++ * tree-ssa-loop-ivopts.c (set_autoinc_for_original_candidates): ++ Find auto-increment use both before and after candidate. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202279. ++ 2013-09-05 Richard Earnshaw ++ ++ * arm.c (thumb2_emit_strd_push): Rewrite to use pre-decrement on ++ initial store. ++ * thumb2.md (thumb2_storewb_parisi): New pattern. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202275. ++ 2013-09-05 Yufeng Zhang ++ ++ * config/aarch64/aarch64-option-extensions.def: Add ++ AARCH64_OPT_EXTENSION of 'crc'. ++ * config/aarch64/aarch64.h (AARCH64_FL_CRC): New define. ++ (AARCH64_ISA_CRC): Ditto. ++ * doc/invoke.texi (-march and -mcpu feature modifiers): Add ++ description of the CRC extension. ++ ++2013-10-01 Christophe Lyon ++ ++ Backport from trunk r201250. ++ 2013-07-25 Kyrylo Tkachov ++ ++ * config/arm/arm.md (arm_addsi3, addsi3_carryin_, ++ addsi3_carryin_alt2_): Correct output template. ++ ++2013-10-01 Kugan Vivekanandarajah ++ ++ Backport from trunk r203059,203116. ++ 2013-10-01 Kugan Vivekanandarajah ++ ++ PR target/58578 ++ Revert ++ 2013-04-05 Greta Yorsh ++ * config/arm/arm.md (arm_ashldi3_1bit): define_insn into ++ define_insn_and_split. ++ (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. ++ (shiftsi3_compare): New pattern. ++ (rrx): New pattern. ++ * config/arm/unspecs.md (UNSPEC_RRX): New. ++ ++2013-09-11 Christophe Lyon ++ ++ * LINARO-VERSION: Bump version. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -3882,26 +4242,210 @@ + p[3] = b; +} +/* { dg-final { scan-assembler "strd" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-1.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-1.c -@@ -0,0 +1,17 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ -+ -+signed long long extendsidi_negsi (signed int x) +--- a/src/gcc/testsuite/gcc.target/arm/lp1243022.c ++++ b/src/gcc/testsuite/gcc.target/arm/lp1243022.c +@@ -0,0 +1,201 @@ ++/* { dg-do compile { target arm_thumb2 } } */ ++/* { dg-options "-O2 -fdump-rtl-subreg2" } */ ++ ++/* { dg-final { scan-rtl-dump "REG_INC" "subreg2" } } */ ++/* { dg-final { cleanup-rtl-dump "subreg2" } } */ ++struct device; ++typedef unsigned int __u32; ++typedef unsigned long long u64; ++typedef __u32 __le32; ++typedef u64 dma_addr_t; ++typedef unsigned gfp_t; ++int dev_warn (const struct device *dev, const char *fmt, ...); ++struct usb_bus ++{ ++ struct device *controller; ++}; ++struct usb_hcd ++{ ++ struct usb_bus self; ++}; ++struct xhci_generic_trb ++{ ++ __le32 field[4]; ++}; ++union xhci_trb ++{ ++ struct xhci_generic_trb generic; ++}; ++struct xhci_segment ++{ ++ union xhci_trb *trbs; ++ dma_addr_t dma; ++}; ++struct xhci_ring ++{ ++ struct xhci_segment *first_seg; ++}; ++struct xhci_hcd ++{ ++ struct xhci_ring *cmd_ring; ++ struct xhci_ring *event_ring; ++}; ++struct usb_hcd *xhci_to_hcd (struct xhci_hcd *xhci) +{ -+ return -x; +} -+ -+/* -+Expected output: -+ rsb r0, r0, #0 -+ mov r1, r0, asr #31 -+*/ -+/* { dg-final { scan-assembler-times "rsb" 1 { target { arm_nothumb } } } } */ -+/* { dg-final { scan-assembler-times "negs\\t" 1 { target { ! { arm_nothumb } } } } } */ -+/* { dg-final { scan-assembler-times "asr" 1 } } */ ++dma_addr_t xhci_trb_virt_to_dma (struct xhci_segment * seg, ++ union xhci_trb * trb); ++struct xhci_segment *trb_in_td (struct xhci_segment *start_seg, ++ dma_addr_t suspect_dma); ++xhci_test_trb_in_td (struct xhci_hcd *xhci, struct xhci_segment *input_seg, ++ union xhci_trb *start_trb, union xhci_trb *end_trb, ++ dma_addr_t input_dma, struct xhci_segment *result_seg, ++ char *test_name, int test_number) ++{ ++ unsigned long long start_dma; ++ unsigned long long end_dma; ++ struct xhci_segment *seg; ++ start_dma = xhci_trb_virt_to_dma (input_seg, start_trb); ++ end_dma = xhci_trb_virt_to_dma (input_seg, end_trb); ++ { ++ dev_warn (xhci_to_hcd (xhci)->self.controller, ++ "%d\n", test_number); ++ dev_warn (xhci_to_hcd (xhci)->self.controller, ++ "Expected seg %p, got seg %p\n", result_seg, seg); ++ } ++} ++xhci_check_trb_in_td_math (struct xhci_hcd *xhci, gfp_t mem_flags) ++{ ++ struct ++ { ++ dma_addr_t input_dma; ++ struct xhci_segment *result_seg; ++ } ++ simple_test_vector[] = ++ { ++ { ++ 0, ((void *) 0) ++ } ++ , ++ { ++ xhci->event_ring->first_seg->dma - 16, ((void *) 0)} ++ , ++ { ++ xhci->event_ring->first_seg->dma - 1, ((void *) 0)} ++ , ++ { ++ xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg} ++ , ++ { ++ xhci->event_ring->first_seg->dma + (64 - 1) * 16, ++ xhci->event_ring->first_seg ++ } ++ , ++ { ++ xhci->event_ring->first_seg->dma + (64 - 1) * 16 + 1, ((void *) 0)} ++ , ++ { ++ xhci->event_ring->first_seg->dma + (64) * 16, ((void *) 0)} ++ , ++ { ++ (dma_addr_t) (~0), ((void *) 0) ++ } ++ }; ++ struct ++ { ++ struct xhci_segment *input_seg; ++ union xhci_trb *start_trb; ++ union xhci_trb *end_trb; ++ dma_addr_t input_dma; ++ struct xhci_segment *result_seg; ++ } ++ complex_test_vector[] = ++ { ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ xhci->event_ring->first_seg->trbs,.end_trb = ++ &xhci->event_ring->first_seg->trbs[64 - 1],.input_dma = ++ xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ xhci->event_ring->first_seg->trbs,.end_trb = ++ &xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma = ++ xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ xhci->cmd_ring->first_seg->trbs,.end_trb = ++ &xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma = ++ xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ &xhci->event_ring->first_seg->trbs[0],.end_trb = ++ &xhci->event_ring->first_seg->trbs[3],.input_dma = ++ xhci->event_ring->first_seg->dma + 4 * 16,.result_seg = ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ &xhci->event_ring->first_seg->trbs[3],.end_trb = ++ &xhci->event_ring->first_seg->trbs[6],.input_dma = ++ xhci->event_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb = ++ &xhci->event_ring->first_seg->trbs[1],.input_dma = ++ xhci->event_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb = ++ &xhci->event_ring->first_seg->trbs[1],.input_dma = ++ xhci->event_ring->first_seg->dma + (64 - 4) * 16,.result_seg = ++ ((void *) 0), ++ } ++ , ++ { ++ .input_seg = xhci->event_ring->first_seg,.start_trb = ++ &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb = ++ &xhci->event_ring->first_seg->trbs[1],.input_dma = ++ xhci->cmd_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0), ++ } ++ }; ++ unsigned int num_tests; ++ int i, ret; ++ num_tests = ++ (sizeof (simple_test_vector) / sizeof ((simple_test_vector)[0]) + ++ (sizeof (struct ++ { ++ } ++ ))); ++ for (i = 0; i < num_tests; i++) ++ { ++ ret = ++ xhci_test_trb_in_td (xhci, xhci->event_ring->first_seg, ++ xhci->event_ring->first_seg->trbs, ++ &xhci->event_ring->first_seg->trbs[64 - 1], ++ simple_test_vector[i].input_dma, ++ simple_test_vector[i].result_seg, "Simple", i); ++ if (ret < 0) ++ return ret; ++ } ++ for (i = 0; i < num_tests; i++) ++ { ++ ret = ++ xhci_test_trb_in_td (xhci, complex_test_vector[i].input_seg, ++ complex_test_vector[i].start_trb, ++ complex_test_vector[i].end_trb, ++ complex_test_vector[i].input_dma, ++ complex_test_vector[i].result_seg, "Complex", i); ++ if (ret < 0) ++ return ret; ++ } ++} --- a/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c +++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c @@ -0,0 +1,10 @@ @@ -3999,25 +4543,6 @@ +} + +/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-2.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-2.c -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ -+ -+signed long long zero_extendsidi_negsi (unsigned int x) -+{ -+ return -x; -+} -+/* -+Expected output: -+ rsb r0, r0, #0 -+ mov r1, #0 -+*/ -+/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */ -+/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */ -+/* { dg-final { scan-assembler-times "mov" 1 } } */ --- a/src/gcc/testsuite/gcc.target/arm/vselvcsf.c +++ b/src/gcc/testsuite/gcc.target/arm/vselvcsf.c @@ -0,0 +1,12 @@ @@ -4188,26 +4713,6 @@ +} + +/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-3.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-3.c -@@ -0,0 +1,17 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ -+ -+signed long long negdi_zero_extendsidi (unsigned int x) -+{ -+ return -((signed long long) x); -+} -+/* -+Expected output: -+ rsbs r0, r0, #0 -+ sbc r1, r1, r1 -+*/ -+/* { dg-final { scan-assembler-times "rsb" 1 } } */ -+/* { dg-final { scan-assembler-times "sbc" 1 } } */ -+/* { dg-final { scan-assembler-times "mov" 0 } } */ -+/* { dg-final { scan-assembler-times "rsc" 0 } } */ --- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c +++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c @@ -0,0 +1,10 @@ @@ -4305,6 +4810,28 @@ +} + +/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c ++++ b/src/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-ivopts-details" } */ ++/* { dg-skip-if "" { arm_thumb1 } } */ ++ ++extern char *__ctype_ptr__; ++ ++unsigned char * foo(unsigned char *ReadPtr) ++{ ++ ++ unsigned char c; ++ ++ while (!(((__ctype_ptr__+sizeof(""[*ReadPtr]))[(int)(*ReadPtr)])&04) == (!(0))) ++ ReadPtr++; ++ ++ return ReadPtr; ++} ++ ++/* { dg-final { scan-tree-dump-times "original biv" 2 "ivopts"} } */ ++/* { dg-final { cleanup-tree-dump "ivopts" } } */ --- a/src/gcc/testsuite/gcc.target/arm/vselvsdf.c +++ b/src/gcc/testsuite/gcc.target/arm/vselvsdf.c @@ -0,0 +1,12 @@ @@ -4371,25 +4898,14 @@ +} + +/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-4.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-4.c -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ -+ -+signed long long negdi_extendsidi (signed int x) -+{ -+ return -((signed long long) x); -+} -+/* -+Expected output: -+ rsbs r0, r0, #0 -+ mov r1, r0, asr #31 -+*/ -+/* { dg-final { scan-assembler-times "rsb" 1 } } */ -+/* { dg-final { scan-assembler-times "asr" 1 } } */ -+/* { dg-final { scan-assembler-times "rsc" 0 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c +@@ -15,4 +15,4 @@ + + /* { dg-final { scan-assembler-times "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" 2 } } */ + /* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +-/* { dg-final { scan-assembler "vbsl\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ --- a/src/gcc/testsuite/gcc.target/arm/vselltdf.c +++ b/src/gcc/testsuite/gcc.target/arm/vselltdf.c @@ -0,0 +1,13 @@ @@ -4476,6 +4992,14 @@ +} + +/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c +@@ -16,4 +16,4 @@ + /* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ + /* { dg-final { scan-assembler "vcge\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ + /* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +-/* { dg-final { scan-assembler "vbsl\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ --- a/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c +++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c @@ -0,0 +1,10 @@ @@ -4569,6 +5093,71 @@ +} + +/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr58578.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr58578.c +@@ -0,0 +1,54 @@ ++ ++/* PR target/58578 */ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ ++ ++#include ++ ++typedef struct { ++ long _prec; ++ int _flag; ++ long _exp; ++} __my_st_t; ++ ++typedef __my_st_t *__my_st_ptr; ++ ++int ++_test_fn (__my_st_ptr y, const __my_st_ptr xt) ++{ ++ int inexact; ++ if (xt->_exp != -2147483647L) ++ { ++ (y->_flag = xt->_flag); ++ } ++ ++ do { ++ __my_st_ptr _y = y; ++ long _err1 = -2 * xt->_exp; ++ long _err2 = 2; ++ if (0 < _err1) ++ { ++ unsigned long _err = (unsigned long) _err1 + _err2; ++ if (__builtin_expect(!!(_err > _y->_prec + 1), 0)) ++ return 2; ++ return 3; ++ } ++ } while (0); ++ ++ return 0; ++} ++ ++int main () ++{ ++ __my_st_t x, y; ++ long pz; ++ int inex; ++ ++ x._prec = 914; ++ y._exp = 18; ++ if (_test_fn (&x, &y)) ++ { ++ abort(); ++ } ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c +@@ -14,4 +14,4 @@ + } + + /* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +-/* { dg-final { scan-assembler "vbit\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ --- a/src/gcc/testsuite/gcc.target/arm/pr57637.c +++ b/src/gcc/testsuite/gcc.target/arm/pr57637.c @@ -0,0 +1,206 @@ @@ -4778,6 +5367,94 @@ + __builtin_abort (); + return 0; +} +--- a/src/gcc/testsuite/gcc.target/aarch64/insv_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/insv_2.c +@@ -0,0 +1,85 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_big_endian } */ ++ ++extern void abort (void); ++ ++typedef struct bitfield ++{ ++ unsigned short eight: 8; ++ unsigned short four: 4; ++ unsigned short five: 5; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++} bitfield; ++ ++bitfield ++bfi1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 56, 8" } } */ ++ a.eight = 3; ++ return a; ++} ++ ++bitfield ++bfi2 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 43, 5" } } */ ++ a.five = 7; ++ return a; ++} ++ ++bitfield ++movk (bitfield a) ++{ ++ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 16" } } */ ++ a.sixteen = 7531; ++ return a; ++} ++ ++bitfield ++set1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 272678883688448" } } */ ++ a.five = 0x1f; ++ return a; ++} ++ ++bitfield ++set0 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -272678883688449" } } */ ++ a.five = 0; ++ return a; ++} ++ ++ ++int ++main (int argc, char** argv) ++{ ++ static bitfield a; ++ bitfield b = bfi1 (a); ++ bitfield c = bfi2 (b); ++ bitfield d = movk (c); ++ ++ if (d.eight != 3) ++ abort (); ++ ++ if (d.five != 7) ++ abort (); ++ ++ if (d.sixteen != 7531) ++ abort (); ++ ++ d = set1 (d); ++ if (d.five != 0x1f) ++ abort (); ++ ++ d = set0 (d); ++ if (d.five != 0) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/vrecps.c +++ b/src/gcc/testsuite/gcc.target/aarch64/vrecps.c @@ -0,0 +1,144 @@ @@ -5814,6 +6491,116 @@ +} + +/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/bics_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bics_1.c +@@ -0,0 +1,107 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++ ++extern void abort (void); ++ ++int ++bics_si_test1 (int a, int b, int c) ++{ ++ int d = a & ~b; ++ ++ /* { dg-final { scan-assembler-times "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++bics_si_test2 (int a, int b, int c) ++{ ++ int d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++typedef long long s64; ++ ++s64 ++bics_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~b; ++ ++ /* { dg-final { scan-assembler-times "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++bics_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++main () ++{ ++ int x; ++ s64 y; ++ ++ x = bics_si_test1 (29, ~4, 5); ++ if (x != ((29 & 4) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test1 (5, ~2, 20); ++ if (x != 25) ++ abort (); ++ ++ x = bics_si_test2 (35, ~4, 5); ++ if (x != ((35 & ~(~4 << 3)) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test2 (96, ~2, 20); ++ if (x != 116) ++ abort (); ++ ++ y = bics_di_test1 (0x130000029ll, ++ ~0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test1 (0x5000500050005ll, ++ ~0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025ll) ++ abort (); ++ ++ y = bics_di_test2 (0x130000029ll, ++ ~0x064000008ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & ~(~0x064000008ll << 3)) ++ + ~0x064000008ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test2 (0x130002900ll, ++ ~0x088000008ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c +++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c @@ -0,0 +1,117 @@ @@ -6919,6 +7706,120 @@ +} + +/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/bics_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bics_2.c +@@ -0,0 +1,111 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++ ++extern void abort (void); ++ ++int ++bics_si_test1 (int a, int b, int c) ++{ ++ int d = a & ~b; ++ ++ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++bics_si_test2 (int a, int b, int c) ++{ ++ int d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++typedef long long s64; ++ ++s64 ++bics_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~b; ++ ++ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++bics_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++main () ++{ ++ int x; ++ s64 y; ++ ++ x = bics_si_test1 (29, ~4, 5); ++ if (x != ((29 & 4) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test1 (5, ~2, 20); ++ if (x != 25) ++ abort (); ++ ++ x = bics_si_test2 (35, ~4, 5); ++ if (x != ((35 & ~(~4 << 3)) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test2 (96, ~2, 20); ++ if (x != 116) ++ abort (); ++ ++ y = bics_di_test1 (0x130000029ll, ++ ~0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test1 (0x5000500050005ll, ++ ~0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025ll) ++ abort (); ++ ++ y = bics_di_test2 (0x130000029ll, ++ ~0x064000008ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & ~(~0x064000008ll << 3)) ++ + ~0x064000008ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test2 (0x130002900ll, ++ ~0x088000008ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x @@ -0,0 +1,37 @@ @@ -7402,6 +8303,42 @@ - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/cmn-neg.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/cmn-neg.c +@@ -0,0 +1,33 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps" } */ ++ ++extern void abort (void); ++ ++void __attribute__ ((noinline)) ++foo_s32 (int a, int b) ++{ ++ if (a < -b) ++ abort (); ++} ++/* { dg-final { scan-assembler "cmn\tw\[0-9\]" } } */ ++ ++void __attribute__ ((noinline)) ++foo_s64 (long long a, long long b) ++{ ++ if (a < -b) ++ abort (); ++} ++/* { dg-final { scan-assembler "cmn\tx\[0-9\]" } } */ ++ ++ ++int ++main (void) ++{ ++ int a = 30; ++ int b = 42; ++ foo_s32 (a, b); ++ foo_s64 (a, b); ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c @@ -1,43 +1,7 @@ @@ -7895,6 +8832,49 @@ +{ + return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); +} +--- a/src/gcc/testsuite/gcc.target/aarch64/bfxil_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bfxil_1.c +@@ -0,0 +1,40 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_little_endian } */ ++ ++extern void abort (void); ++ ++typedef struct bitfield ++{ ++ unsigned short eight1: 8; ++ unsigned short four: 4; ++ unsigned short eight2: 8; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++} bitfield; ++ ++bitfield ++bfxil (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 16, 8" } } */ ++ a.eight1 = a.eight2; ++ return a; ++} ++ ++int ++main (void) ++{ ++ static bitfield a; ++ bitfield b; ++ ++ a.eight1 = 9; ++ a.eight2 = 57; ++ b = bfxil (a); ++ ++ if (b.eight1 != a.eight2) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x +++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x @@ -0,0 +1,37 @@ @@ -8022,13 +9002,6 @@ +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c -@@ -11,3 +11,4 @@ - /* { dg-final { scan-assembler "fdiv\\tv" } } */ - /* { dg-final { scan-assembler "fneg\\tv" } } */ - /* { dg-final { scan-assembler "fabs\\tv" } } */ -+/* { dg-final { scan-assembler "fabd\\tv" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c +++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c @@ -2,12 +2,13 @@ @@ -8046,6 +9019,13 @@ /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c +@@ -11,3 +11,4 @@ + /* { dg-final { scan-assembler "fdiv\\tv" } } */ + /* { dg-final { scan-assembler "fneg\\tv" } } */ + /* { dg-final { scan-assembler "fabs\\tv" } } */ ++/* { dg-final { scan-assembler "fabd\\tv" } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/adds1.c +++ b/src/gcc/testsuite/gcc.target/aarch64/adds1.c @@ -0,0 +1,149 @@ @@ -8200,9 +9180,10 @@ +/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/insv_1.c +++ b/src/gcc/testsuite/gcc.target/aarch64/insv_1.c -@@ -0,0 +1,84 @@ -+/* { dg-do run } */ +@@ -0,0 +1,85 @@ ++/* { dg-do run { target aarch64*-*-* } } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_little_endian } */ + +extern void abort (void); + @@ -9128,6 +10109,51 @@ /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/bfxil_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bfxil_2.c +@@ -0,0 +1,42 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_big_endian } */ ++ ++extern void abort (void); ++ ++typedef struct bitfield ++{ ++ unsigned short eight1: 8; ++ unsigned short four: 4; ++ unsigned short eight2: 8; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++ unsigned short eight3: 8; ++ unsigned short eight4: 8; ++} bitfield; ++ ++bitfield ++bfxil (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 40, 8" } } */ ++ a.eight4 = a.eight2; ++ return a; ++} ++ ++int ++main (void) ++{ ++ static bitfield a; ++ bitfield b; ++ ++ a.eight4 = 9; ++ a.eight2 = 57; ++ b = bfxil (a); ++ ++ if (b.eight4 != a.eight2) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x +++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x @@ -7,13 +7,23 @@ @@ -9554,7 +10580,21 @@ /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ --- a/src/gcc/testsuite/lib/target-supports.exp +++ b/src/gcc/testsuite/lib/target-supports.exp -@@ -2012,6 +2012,7 @@ +@@ -487,13 +487,6 @@ + return 0 + } + +- # We don't yet support profiling for AArch64. +- if { [istarget aarch64*-*-*] +- && ([lindex $test_what 1] == "-p" +- || [lindex $test_what 1] == "-pg") } { +- return 0 +- } +- + # cygwin does not support -p. + if { [istarget *-*-cygwin*] && $test_what == "-p" } { + return 0 +@@ -2012,6 +2005,7 @@ || ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*]) || [istarget x86_64-*-*] @@ -9562,7 +10602,23 @@ || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok])} { set et_vect_uintfloat_cvt_saved 1 -@@ -2147,22 +2148,6 @@ +@@ -2078,6 +2072,15 @@ + }] + } + ++# Return 1 if this is a AArch64 target supporting little endian ++proc check_effective_target_aarch64_little_endian { } { ++ return [check_no_compiler_messages aarch64_little_endian assembly { ++ #if !defined(__aarch64__) || defined(__AARCH64EB__) ++ #error FOO ++ #endif ++ }] ++} ++ + # Return 1 is this is an arm target using 32-bit instructions + proc check_effective_target_arm32 { } { + return [check_no_compiler_messages arm32 assembly { +@@ -2147,22 +2150,6 @@ } } @@ -9585,7 +10641,7 @@ # Return 1 if this is an ARM target supporting -mfpu=vfp # -mfloat-abi=hard. Some multilibs may be incompatible with these # options. -@@ -2226,7 +2211,8 @@ +@@ -2226,7 +2213,8 @@ if { ! [check_effective_target_arm_v8_neon_ok] } { return "$flags" } @@ -9595,7 +10651,7 @@ } # Add the options needed for NEON. We need either -mfloat-abi=softfp -@@ -2270,6 +2256,79 @@ +@@ -2270,6 +2258,79 @@ check_effective_target_arm_neon_ok_nocache] } @@ -9675,7 +10731,7 @@ # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4 # -mfloat-abi=softfp or equivalent options. Some multilibs may be # incompatible with these options. Also set et_arm_neonv2_flags to the -@@ -2509,6 +2568,24 @@ +@@ -2509,6 +2570,24 @@ } [add_options_for_arm_neonv2 ""]] } @@ -9700,7 +10756,7 @@ # Return 1 if this is a ARM target with NEON enabled. proc check_effective_target_arm_neon { } { -@@ -4591,6 +4668,33 @@ +@@ -4591,6 +4670,33 @@ return 0 } @@ -9736,7 +10792,80 @@ proc check_effective_target_vxworks_kernel { } { --- a/src/gcc/testsuite/ChangeLog.linaro +++ b/src/gcc/testsuite/ChangeLog.linaro -@@ -0,0 +1,639 @@ +@@ -0,0 +1,712 @@ ++2013-11-06 Christophe Lyon ++ ++ Revert backport from trunk r197526. ++ 2013-04-05 Greta Yorsh ++ ++ * gcc.target/arm/negdi-1.c: New test. ++ * gcc.target/arm/negdi-2.c: Likewise. ++ * gcc.target/arm/negdi-3.c: Likewise. ++ * gcc.target/arm/negdi-4.c: Likewise. ++ ++2013-11-05 Zhenqiang Chen ++ ++ Backport from trunk r204247. ++ 2013-10-31 Zhenqiang Chen ++ ++ * gcc.target/arm/lp1243022.c: New test. ++ ++2013-11-04 Kugan Vivekanandarajah ++ ++ Backport from trunk r204336 ++ 2013-11-03 Kugan Vivekanandarajah ++ ++ * gcc.target/arm/neon-vcond-gt.c: Scan for vbsl or vbit or vbif. ++ * gcc.target/arm/neon-vcond-ltgt.c: Scan for vbsl or vbit or vbif. ++ * gcc.target/arm/neon-vcond-unordered.c: Scan for vbsl or vbit or ++ vbif. ++ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ ++2013-10-09 Christophe Lyon ++ ++ Backport from trunk r198526,200595,200597. ++ 2013-05-02 Ian Bolton ++ ++ * gcc.target/aarch64/bics_1.c: New test. ++ * gcc.target/aarch64/bics_2.c: Likewise. ++ ++ 2013-07-02 Ian Bolton ++ ++ * gcc.target/aarch64/bfxil_1.c: New test. ++ * gcc.target/aarch64/bfxil_2.c: Likewise. ++ ++ 2013-07-02 Ian Bolton ++ ++ * gcc.target/config/aarch64/insv_1.c: Update to show it doesn't work ++ on big endian. ++ * gcc.target/config/aarch64/insv_2.c: New test for big endian. ++ * lib/target-supports.exp: Define aarch64_little_endian. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202400. ++ 2013-09-09 Kyrylo Tkachov ++ ++ * gcc.target/aarch64/cmn-neg.c: New test. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202164. ++ 2013-09-02 Bin Cheng ++ ++ * gcc.target/arm/ivopts-orig_biv-inc.c: New testcase. ++ ++2013-10-01 Kugan Vivekanandarajah ++ ++ Backport from trunk r203059,203116. ++ 2013-10-01 Kugan Vivekanandarajah ++ ++ PR Target/58578 ++ * gcc.target/arm/pr58578.c: New test. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10376,17 +11505,6 @@ + * gcc.target/aarch64/vect-fp-compile.c: Check for fabd + instruction in assembly. + * gcc.target/aarch64/vect-fp.x: Add fabd test function. ---- a/src/gcc/testsuite/gcc.dg/pr57518.c -+++ b/src/gcc/testsuite/gcc.dg/pr57518.c -@@ -2,7 +2,7 @@ - - /* { dg-do compile } */ - /* { dg-options "-O2 -fdump-rtl-ira" } */ --/* { dg-final { scan-rtl-dump-not "REG_EQUIV.*mem.*\"ip\"" "ira" } } */ -+/* { dg-final { scan-rtl-dump-not "REG_EQUIV\[^\n\]*mem\[^\n\]*\"ip\"" "ira" } } */ - - char ip[10]; - int total; --- a/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c +++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c @@ -0,0 +1,11 @@ @@ -10668,7 +11786,11 @@ /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*null-deref-1.c:15|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ --- a/src/gcc/objcp/ChangeLog.linaro +++ b/src/gcc/objcp/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10698,7 +11820,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/cp/ChangeLog.linaro +++ b/src/gcc/cp/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10726,6 +11852,53 @@ +2013-04-09 Matthew Gretton-Dann + + * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/tree-ssa-loop-ivopts.c ++++ b/src/gcc/tree-ssa-loop-ivopts.c +@@ -4827,22 +4827,36 @@ + for (i = 0; i < n_iv_cands (data); i++) + { + struct iv_cand *cand = iv_cand (data, i); +- struct iv_use *closest = NULL; ++ struct iv_use *closest_before = NULL; ++ struct iv_use *closest_after = NULL; + if (cand->pos != IP_ORIGINAL) + continue; ++ + for (j = 0; j < n_iv_uses (data); j++) + { + struct iv_use *use = iv_use (data, j); + unsigned uid = gimple_uid (use->stmt); +- if (gimple_bb (use->stmt) != gimple_bb (cand->incremented_at) +- || uid > gimple_uid (cand->incremented_at)) ++ ++ if (gimple_bb (use->stmt) != gimple_bb (cand->incremented_at)) + continue; +- if (closest == NULL || uid > gimple_uid (closest->stmt)) +- closest = use; ++ ++ if (uid < gimple_uid (cand->incremented_at) ++ && (closest_before == NULL ++ || uid > gimple_uid (closest_before->stmt))) ++ closest_before = use; ++ ++ if (uid > gimple_uid (cand->incremented_at) ++ && (closest_after == NULL ++ || uid < gimple_uid (closest_after->stmt))) ++ closest_after = use; + } +- if (closest == NULL || !autoinc_possible_for_pair (data, closest, cand)) +- continue; +- cand->ainc_use = closest; ++ ++ if (closest_before != NULL ++ && autoinc_possible_for_pair (data, closest_before, cand)) ++ cand->ainc_use = closest_before; ++ else if (closest_after != NULL ++ && autoinc_possible_for_pair (data, closest_after, cand)) ++ cand->ainc_use = closest_after; + } + } + --- a/src/gcc/rtl.def +++ b/src/gcc/rtl.def @@ -937,8 +937,9 @@ @@ -10742,7 +11915,11 @@ DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will --- a/src/gcc/go/ChangeLog.linaro +++ b/src/gcc/go/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10772,7 +11949,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ada/ChangeLog.linaro +++ b/src/gcc/ada/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10813,7 +11994,11 @@ --- a/src/gcc/fortran/ChangeLog.linaro +++ b/src/gcc/fortran/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10852,6 +12037,18 @@ ACX_BUGURL([http://gcc.gnu.org/bugs.html]) # Sanity check enable_languages in case someone does not run the toplevel +@@ -4179,8 +4179,9 @@ + # ??? Once 2.11 is released, probably need to add first known working + # version to the per-target configury. + case "$cpu_type" in +- alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze | mips \ +- | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 | xtensa) ++ aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ ++ | mips | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 \ ++ | xtensa) + insn="nop" + ;; + ia64 | s390) --- a/src/gcc/function.c +++ b/src/gcc/function.c @@ -5509,22 +5509,45 @@ @@ -10924,6 +12121,46 @@ union section; typedef union section section; struct gcc_options; +--- a/src/gcc/lower-subreg.c ++++ b/src/gcc/lower-subreg.c +@@ -966,7 +966,20 @@ + rtx reg; + + reg = gen_reg_rtx (orig_mode); ++ ++#ifdef AUTO_INC_DEC ++ { ++ rtx move = emit_move_insn (reg, src); ++ if (MEM_P (src)) ++ { ++ rtx note = find_reg_note (insn, REG_INC, NULL_RTX); ++ if (note) ++ add_reg_note (move, REG_INC, XEXP (note, 0)); ++ } ++ } ++#else + emit_move_insn (reg, src); ++#endif + src = reg; + } + +@@ -1056,6 +1069,16 @@ + mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0); + minsn = emit_move_insn (real_dest, mdest); + ++#ifdef AUTO_INC_DEC ++ if (MEM_P (real_dest) ++ && !(resolve_reg_p (real_dest) || resolve_subreg_p (real_dest))) ++ { ++ rtx note = find_reg_note (insn, REG_INC, NULL_RTX); ++ if (note) ++ add_reg_note (minsn, REG_INC, XEXP (note, 0)); ++ } ++#endif ++ + smove = single_set (minsn); + gcc_assert (smove != NULL_RTX); + --- a/src/gcc/gimple-fold.c +++ b/src/gcc/gimple-fold.c @@ -1143,6 +1143,8 @@ @@ -10937,7 +12174,11 @@ return changed; --- a/src/gcc/lto/ChangeLog.linaro +++ b/src/gcc/lto/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10967,7 +12208,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/po/ChangeLog.linaro +++ b/src/gcc/po/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -10995,6 +12240,22 @@ +2013-04-09 Matthew Gretton-Dann + + * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/combine.c ++++ b/src/gcc/combine.c +@@ -11989,6 +11989,13 @@ + } + } + ++ /* We may have changed the comparison operands. Re-canonicalize. */ ++ if (swap_commutative_operands_p (op0, op1)) ++ { ++ tem = op0, op0 = op1, op1 = tem; ++ code = swap_condition (code); ++ } ++ + /* If this machine only supports a subset of valid comparisons, see if we + can convert an unsupported one into a supported one. */ + target_canonicalize_comparison (&code, &op0, &op1, 0); --- a/src/gcc/config.gcc +++ b/src/gcc/config.gcc @@ -329,6 +329,7 @@ @@ -11038,6 +12299,50 @@ default_use_cxa_atexit=yes tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/bpabi.h" tmake_file="arm/t-arm arm/t-arm-elf" +@@ -3295,6 +3284,43 @@ + if test "x$with_arch" != x && test "x$with_cpu" != x; then + echo "Warning: --with-arch overrides --with-cpu=$with_cpu" 1>&2 + fi ++ ++ # Add extra multilibs ++ if test "x$with_multilib_list" != x; then ++ arm_multilibs=`echo $with_multilib_list | sed -e 's/,/ /g'` ++ for arm_multilib in ${arm_multilibs}; do ++ case ${arm_multilib} in ++ aprofile) ++ # Note that arm/t-aprofile is a ++ # stand-alone make file fragment to be ++ # used only with itself. We do not ++ # specifically use the ++ # TM_MULTILIB_OPTION framework because ++ # this shorthand is more ++ # pragmatic. Additionally it is only ++ # designed to work without any ++ # with-cpu, with-arch with-mode ++ # with-fpu or with-float options. ++ if test "x$with_arch" != x \ ++ || test "x$with_cpu" != x \ ++ || test "x$with_float" != x \ ++ || test "x$with_fpu" != x \ ++ || test "x$with_mode" != x ; then ++ echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode with --with-multilib-list=aprofile" 1>&2 ++ exit 1 ++ fi ++ tmake_file="${tmake_file} arm/t-aprofile" ++ break ++ ;; ++ default) ++ ;; ++ *) ++ echo "Error: --with-multilib-list=${with_multilib_list} not supported." 1>&2 ++ exit 1 ++ ;; ++ esac ++ done ++ fi + ;; + + fr*-*-*linux*) --- a/src/gcc/gimple.h +++ b/src/gcc/gimple.h @@ -130,7 +130,7 @@ @@ -11060,6 +12365,37 @@ /* Data structure definitions for GIMPLE tuples. NOTE: word markers are for 64 bit hosts. */ +--- a/src/gcc/config/i386/linux-common.h ++++ b/src/gcc/config/i386/linux-common.h +@@ -40,7 +40,7 @@ + #undef LIB_SPEC + #define LIB_SPEC \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LIB_SPEC, \ +- GNU_USER_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC " " ANDROID_LIB_SPEC) + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ +--- a/src/gcc/config/gnu-user.h ++++ b/src/gcc/config/gnu-user.h +@@ -73,10 +73,14 @@ + #undef CPLUSPLUS_CPP_SPEC + #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" + ++#define GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC \ ++ "%{shared:-lc} \ ++ %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" ++ + #define GNU_USER_TARGET_LIB_SPEC \ +- "%{pthread:-lpthread} \ +- %{shared:-lc} \ +- %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" ++ "%{pthread:-lpthread} " \ ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC ++ + #undef LIB_SPEC + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + --- a/src/gcc/config/aarch64/aarch64-simd.md +++ b/src/gcc/config/aarch64/aarch64-simd.md @@ -21,7 +21,7 @@ @@ -12341,7 +13677,43 @@ "TARGET_SIMD" { aarch64_simd_lane_bounds (operands[2], 0, 1); -@@ -2861,28 +3213,6 @@ +@@ -1944,16 +2296,30 @@ + (set_attr "simd_mode" "")] + ) + +-(define_insn "aarch64_combine" ++(define_insn_and_split "aarch64_combine" + [(set (match_operand: 0 "register_operand" "=&w") + (vec_concat: (match_operand:VDC 1 "register_operand" "w") + (match_operand:VDC 2 "register_operand" "w")))] + "TARGET_SIMD" +- "mov\\t%0.d[0], %1.d[0]\;ins\\t%0.d[1], %2.d[0]" +- [(set_attr "simd_type" "simd_ins") +- (set_attr "simd_mode" "")] +-) ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++{ ++ aarch64_split_simd_combine (operands[0], operands[1], operands[2]); ++ DONE; ++}) + ++(define_expand "aarch64_simd_combine" ++ [(set (match_operand: 0 "register_operand" "=&w") ++ (vec_concat: (match_operand:VDC 1 "register_operand" "w") ++ (match_operand:VDC 2 "register_operand" "w")))] ++ "TARGET_SIMD" ++ { ++ emit_insn (gen_move_lo_quad_ (operands[0], operands[1])); ++ emit_insn (gen_move_hi_quad_ (operands[0], operands[2])); ++ DONE; ++ }) ++ + ;; l. + + (define_insn "aarch64_l2_internal" +@@ -2861,28 +3227,6 @@ (set_attr "simd_mode" "")] ) @@ -12370,7 +13742,7 @@ ;; vshll_n (define_insn "aarch64_shll_n" -@@ -2927,28 +3257,6 @@ +@@ -2927,28 +3271,6 @@ (set_attr "simd_mode" "")] ) @@ -12399,7 +13771,7 @@ ;; vrshr_n (define_insn "aarch64_shr_n" -@@ -3034,52 +3342,180 @@ +@@ -3034,52 +3356,180 @@ ) @@ -12603,7 +13975,7 @@ ;; addp (define_insn "aarch64_addp" -@@ -3105,30 +3541,6 @@ +@@ -3105,30 +3555,6 @@ (set_attr "simd_mode" "DI")] ) @@ -12634,7 +14006,7 @@ ;; sqrt (define_insn "sqrt2" -@@ -3140,16 +3552,6 @@ +@@ -3140,16 +3566,6 @@ (set_attr "simd_mode" "")] ) @@ -12651,7 +14023,7 @@ ;; Patterns for vector struct loads and stores. (define_insn "vec_load_lanesoi" -@@ -3736,3 +4138,25 @@ +@@ -3736,3 +4152,25 @@ "ld1r\\t{%0.}, %1" [(set_attr "simd_type" "simd_load1r") (set_attr "simd_mode" "")]) @@ -12740,7 +14112,17 @@ --- a/src/gcc/config/aarch64/arm_neon.h +++ b/src/gcc/config/aarch64/arm_neon.h -@@ -446,7 +446,66 @@ +@@ -29,6 +29,9 @@ + + #include + ++#define __AARCH64_UINT64_C(__C) ((uint64_t) __C) ++#define __AARCH64_INT64_C(__C) ((int64_t) __C) ++ + typedef __builtin_aarch64_simd_qi int8x8_t + __attribute__ ((__vector_size__ (8))); + typedef __builtin_aarch64_simd_hi int16x4_t +@@ -446,7 +449,66 @@ poly16x8_t val[4]; } poly16x8x4_t; @@ -12807,7 +14189,7 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vadd_s8 (int8x8_t __a, int8x8_t __b) { -@@ -2307,155 +2366,156 @@ +@@ -2307,155 +2369,156 @@ return (poly16x4_t) __a; } @@ -13030,7 +14412,93 @@ __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) vreinterpret_p8_s8 (int8x8_t __a) { -@@ -4468,160 +4528,6 @@ +@@ -3805,6 +3868,85 @@ + return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a); + } + ++#define __GET_LOW(__TYPE) \ ++ uint64x2_t tmp = vreinterpretq_u64_##__TYPE (__a); \ ++ uint64_t lo = vgetq_lane_u64 (tmp, 0); \ ++ return vreinterpret_##__TYPE##_u64 (lo); ++ ++__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) ++vget_low_f32 (float32x4_t __a) ++{ ++ __GET_LOW (f32); ++} ++ ++__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) ++vget_low_f64 (float64x2_t __a) ++{ ++ return vgetq_lane_f64 (__a, 0); ++} ++ ++__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) ++vget_low_p8 (poly8x16_t __a) ++{ ++ __GET_LOW (p8); ++} ++ ++__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) ++vget_low_p16 (poly16x8_t __a) ++{ ++ __GET_LOW (p16); ++} ++ ++__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) ++vget_low_s8 (int8x16_t __a) ++{ ++ __GET_LOW (s8); ++} ++ ++__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) ++vget_low_s16 (int16x8_t __a) ++{ ++ __GET_LOW (s16); ++} ++ ++__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) ++vget_low_s32 (int32x4_t __a) ++{ ++ __GET_LOW (s32); ++} ++ ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vget_low_s64 (int64x2_t __a) ++{ ++ return vgetq_lane_s64 (__a, 0); ++} ++ ++__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) ++vget_low_u8 (uint8x16_t __a) ++{ ++ __GET_LOW (u8); ++} ++ ++__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) ++vget_low_u16 (uint16x8_t __a) ++{ ++ __GET_LOW (u16); ++} ++ ++__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) ++vget_low_u32 (uint32x4_t __a) ++{ ++ __GET_LOW (u32); ++} ++ ++__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) ++vget_low_u64 (uint64x2_t __a) ++{ ++ return vgetq_lane_u64 (__a, 0); ++} ++ ++#undef __GET_LOW ++ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vcombine_s8 (int8x8_t __a, int8x8_t __b) + { +@@ -4468,160 +4610,6 @@ return result; } @@ -13191,7 +14659,7 @@ __extension__ static __inline int16_t __attribute__ ((__always_inline__)) vaddlv_s8 (int8x8_t a) { -@@ -4732,116 +4638,6 @@ +@@ -4732,116 +4720,6 @@ return result; } @@ -13308,7 +14776,7 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c) { -@@ -5095,358 +4891,6 @@ +@@ -5095,358 +4973,6 @@ return result; } @@ -13667,7 +15135,7 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vcls_s8 (int8x8_t a) { -@@ -5513,50 +4957,6 @@ +@@ -5513,50 +5039,6 @@ return result; } @@ -13718,7 +15186,7 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vclz_s8 (int8x8_t a) { -@@ -5915,100 +5315,12 @@ +@@ -5915,100 +5397,12 @@ /* vcvt_f32_f16 not supported */ @@ -13819,7 +15287,7 @@ #define vcvt_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6057,160 +5369,6 @@ +@@ -6057,160 +5451,6 @@ result; \ }) @@ -13980,7 +15448,7 @@ #define vcvtd_n_f64_s64(a, b) \ __extension__ \ ({ \ -@@ -6259,402 +5417,6 @@ +@@ -6259,402 +5499,6 @@ result; \ }) @@ -14350,161 +15818,294 @@ -__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vcvtq_f32_u32 (uint32x4_t a) -{ -- float32x4_t result; -- __asm__ ("ucvtf %0.4s, %1.4s" +- float32x4_t result; +- __asm__ ("ucvtf %0.4s, %1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +-vcvtq_f64_s64 (int64x2_t a) +-{ +- float64x2_t result; +- __asm__ ("scvtf %0.2d, %1.2d" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +-vcvtq_f64_u64 (uint64x2_t a) +-{ +- float64x2_t result; +- __asm__ ("ucvtf %0.2d, %1.2d" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- + #define vcvtq_n_f32_s32(a, b) \ + __extension__ \ + ({ \ +@@ -6751,72 +5595,6 @@ + result; \ + }) + +-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +-vcvtq_s32_f32 (float32x4_t a) +-{ +- int32x4_t result; +- __asm__ ("fcvtzs %0.4s, %1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +-vcvtq_s64_f64 (float64x2_t a) +-{ +- int64x2_t result; +- __asm__ ("fcvtzs %0.2d, %1.2d" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) +-vcvtq_u32_f32 (float32x4_t a) +-{ +- uint32x4_t result; +- __asm__ ("fcvtzu %0.4s, %1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) +-vcvtq_u64_f64 (float64x2_t a) +-{ +- uint64x2_t result; +- __asm__ ("fcvtzu %0.2d, %1.2d" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +-vcvts_f64_s32 (int32_t a) +-{ +- int32_t result; +- __asm__ ("scvtf %s0,%s1" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) +-vcvts_f64_u32 (uint32_t a) +-{ +- uint32_t result; +- __asm__ ("ucvtf %s0,%s1" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- + #define vcvts_n_f32_s32(a, b) \ + __extension__ \ + ({ \ +@@ -6865,28 +5643,6 @@ + result; \ + }) + +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vcvts_s64_f64 (float32_t a) +-{ +- float32_t result; +- __asm__ ("fcvtzs %s0,%s1" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vcvts_u64_f64 (float32_t a) +-{ +- float32_t result; +- __asm__ ("fcvtzu %s0,%s1" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) + vcvtx_f32_f64 (float64x2_t a) + { +@@ -8110,151 +6866,7 @@ + return result; + } + +-#define vget_lane_f64(a, b) \ +- __extension__ \ +- ({ \ +- float64x1_t a_ = (a); \ +- float64_t result; \ +- __asm__ ("umov %x0, %1.d[%2]" \ +- : "=r"(result) \ +- : "w"(a_), "i"(b) \ +- : /* No clobbers */); \ +- result; \ +- }) +- +-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +-vget_low_f32 (float32x4_t a) +-{ +- float32x2_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) +-vget_low_f64 (float64x2_t a) +-{ +- float64x1_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) --vcvtq_f64_s64 (int64x2_t a) +-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +-vget_low_p8 (poly8x16_t a) -{ -- float64x2_t result; -- __asm__ ("scvtf %0.2d, %1.2d" +- poly8x8_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) --vcvtq_f64_u64 (uint64x2_t a) +-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +-vget_low_p16 (poly16x8_t a) -{ -- float64x2_t result; -- __asm__ ("ucvtf %0.2d, %1.2d" +- poly16x4_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - - #define vcvtq_n_f32_s32(a, b) \ - __extension__ \ - ({ \ -@@ -6751,72 +5513,6 @@ - result; \ - }) - --__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) --vcvtq_s32_f32 (float32x4_t a) + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +-vget_low_s8 (int8x16_t a) -{ -- int32x4_t result; -- __asm__ ("fcvtzs %0.4s, %1.4s" +- int8x8_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) --vcvtq_s64_f64 (float64x2_t a) +-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +-vget_low_s16 (int16x8_t a) -{ -- int64x2_t result; -- __asm__ ("fcvtzs %0.2d, %1.2d" +- int16x4_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) --vcvtq_u32_f32 (float32x4_t a) +-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +-vget_low_s32 (int32x4_t a) -{ -- uint32x4_t result; -- __asm__ ("fcvtzu %0.4s, %1.4s" +- int32x2_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) --vcvtq_u64_f64 (float64x2_t a) +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vget_low_s64 (int64x2_t a) -{ -- uint64x2_t result; -- __asm__ ("fcvtzu %0.2d, %1.2d" +- int64x1_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline int32_t __attribute__ ((__always_inline__)) --vcvts_f64_s32 (int32_t a) +-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +-vget_low_u8 (uint8x16_t a) -{ -- int32_t result; -- __asm__ ("scvtf %s0,%s1" +- uint8x8_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline uint32_t __attribute__ ((__always_inline__)) --vcvts_f64_u32 (uint32_t a) +-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +-vget_low_u16 (uint16x8_t a) -{ -- uint32_t result; -- __asm__ ("ucvtf %s0,%s1" +- uint16x4_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - - #define vcvts_n_f32_s32(a, b) \ - __extension__ \ - ({ \ -@@ -6865,28 +5561,6 @@ - result; \ - }) - --__extension__ static __inline float32_t __attribute__ ((__always_inline__)) --vcvts_s64_f64 (float32_t a) +-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +-vget_low_u32 (uint32x4_t a) -{ -- float32_t result; -- __asm__ ("fcvtzs %s0,%s1" +- uint32x2_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - --__extension__ static __inline float32_t __attribute__ ((__always_inline__)) --vcvts_u64_f64 (float32_t a) +-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +-vget_low_u64 (uint64x2_t a) -{ -- float32_t result; -- __asm__ ("fcvtzu %s0,%s1" +- uint64x1_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" - : "=w"(result) - : "w"(a) - : /* No clobbers */); - return result; -} - - __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) - vcvtx_f32_f64 (float64x2_t a) - { -@@ -8110,18 +6784,6 @@ - return result; - } - --#define vget_lane_f64(a, b) \ -- __extension__ \ -- ({ \ -- float64x1_t a_ = (a); \ -- float64_t result; \ -- __asm__ ("umov %x0, %1.d[%2]" \ -- : "=r"(result) \ -- : "w"(a_), "i"(b) \ -- : /* No clobbers */); \ -- result; \ -- }) -- - __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) - vget_low_f32 (float32x4_t a) +-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) + vhsub_s8 (int8x8_t a, int8x8_t b) { -@@ -8962,303 +7624,6 @@ + int8x8_t result; +@@ -8962,303 +7574,6 @@ result; \ }) @@ -14808,7 +16409,322 @@ #define vmla_lane_f32(a, b, c, d) \ __extension__ \ ({ \ -@@ -14292,17 +12657,6 @@ +@@ -11382,7 +9697,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vmovn_high_s16 (int8x8_t a, int16x8_t b) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.16b,%1.8h" + : "+w"(result) + : "w"(b) +@@ -11393,7 +9708,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vmovn_high_s32 (int16x4_t a, int32x4_t b) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.8h,%1.4s" + : "+w"(result) + : "w"(b) +@@ -11404,7 +9719,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vmovn_high_s64 (int32x2_t a, int64x2_t b) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.4s,%1.2d" + : "+w"(result) + : "w"(b) +@@ -11415,7 +9730,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vmovn_high_u16 (uint8x8_t a, uint16x8_t b) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.16b,%1.8h" + : "+w"(result) + : "w"(b) +@@ -11426,7 +9741,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vmovn_high_u32 (uint16x4_t a, uint32x4_t b) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.8h,%1.4s" + : "+w"(result) + : "w"(b) +@@ -11437,7 +9752,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vmovn_high_u64 (uint32x2_t a, uint64x2_t b) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.4s,%1.2d" + : "+w"(result) + : "w"(b) +@@ -13856,7 +12171,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vqmovn_high_s16 (int8x8_t a, int16x8_t b) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtn2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) +@@ -13867,7 +12182,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vqmovn_high_s32 (int16x4_t a, int32x4_t b) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtn2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) +@@ -13878,7 +12193,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqmovn_high_s64 (int32x2_t a, int64x2_t b) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtn2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) +@@ -13889,7 +12204,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vqmovn_high_u16 (uint8x8_t a, uint16x8_t b) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("uqxtn2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) +@@ -13900,7 +12215,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vqmovn_high_u32 (uint16x4_t a, uint32x4_t b) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("uqxtn2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) +@@ -13911,7 +12226,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vqmovn_high_u64 (uint32x2_t a, uint64x2_t b) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("uqxtn2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) +@@ -13922,7 +12237,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vqmovun_high_s16 (uint8x8_t a, int16x8_t b) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtun2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) +@@ -13933,7 +12248,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vqmovun_high_s32 (uint16x4_t a, int32x4_t b) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtun2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) +@@ -13944,7 +12259,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vqmovun_high_s64 (uint32x2_t a, int64x2_t b) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtun2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) +@@ -14002,7 +12317,8 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14016,7 +12332,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14030,7 +12347,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14044,7 +12362,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14058,7 +12377,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14072,7 +12392,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14086,7 +12407,8 @@ + int16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14100,7 +12422,8 @@ + int32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14114,7 +12437,8 @@ + int64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14128,7 +12452,8 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14142,7 +12467,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14156,7 +12482,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14170,7 +12497,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14184,7 +12512,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14198,7 +12527,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14212,7 +12542,8 @@ + int16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrun2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14226,7 +12557,8 @@ + int32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrun2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14240,7 +12572,8 @@ + int64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrun2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14292,17 +12625,6 @@ return result; } @@ -14826,7 +16742,7 @@ __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vrecpe_u32 (uint32x2_t a) { -@@ -14314,39 +12668,6 @@ +@@ -14314,39 +12636,6 @@ return result; } @@ -14866,7 +16782,7 @@ __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vrecpeq_u32 (uint32x4_t a) { -@@ -14358,94 +12679,6 @@ +@@ -14358,94 +12647,6 @@ return result; } @@ -14961,7 +16877,7 @@ __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) vrev16_p8 (poly8x8_t a) { -@@ -14842,171 +13075,6 @@ +@@ -14842,178 +13043,14 @@ return result; } @@ -15133,7 +17049,234 @@ #define vrshrn_high_n_s16(a, b, c) \ __extension__ \ ({ \ -@@ -18309,86 +16377,6 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15027,7 +13064,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15041,7 +13079,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15055,7 +13094,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15069,7 +13109,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15083,7 +13124,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15320,7 +13362,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vrsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15331,7 +13373,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vrsubhn_high_s32 (int16x4_t a, int32x4_t b, int32x4_t c) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15342,7 +13384,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vrsubhn_high_s64 (int32x2_t a, int64x2_t b, int64x2_t c) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15353,7 +13395,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vrsubhn_high_u16 (uint8x8_t a, uint16x8_t b, uint16x8_t c) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15364,7 +13406,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vrsubhn_high_u32 (uint16x4_t a, uint32x4_t b, uint32x4_t c) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15375,7 +13417,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vrsubhn_high_u64 (uint32x2_t a, uint64x2_t b, uint64x2_t c) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15767,7 +13809,8 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15781,7 +13824,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15795,7 +13839,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15809,7 +13854,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15823,7 +13869,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15837,7 +13884,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -16289,7 +14337,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16300,7 +14348,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vsubhn_high_s32 (int16x4_t a, int32x4_t b, int32x4_t c) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16311,7 +14359,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vsubhn_high_s64 (int32x2_t a, int64x2_t b, int64x2_t c) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16322,7 +14370,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vsubhn_high_u16 (uint8x8_t a, uint16x8_t b, uint16x8_t c) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16333,7 +14381,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vsubhn_high_u32 (uint16x4_t a, uint32x4_t b, uint32x4_t c) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16344,7 +14392,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vsubhn_high_u64 (uint32x2_t a, uint64x2_t b, uint64x2_t c) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -18309,86 +16357,6 @@ return result; } @@ -15220,7 +17363,115 @@ __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) vpaddd_s64 (int64x2_t __a) { -@@ -19370,6 +17358,80 @@ +@@ -19022,7 +16990,7 @@ + vtbl1_s8 (int8x8_t tab, int8x8_t idx) + { + int8x8_t result; +- int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" + : "=w"(result) + : "w"(temp), "w"(idx) +@@ -19034,7 +17002,7 @@ + vtbl1_u8 (uint8x8_t tab, uint8x8_t idx) + { + uint8x8_t result; +- uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" + : "=w"(result) + : "w"(temp), "w"(idx) +@@ -19046,7 +17014,7 @@ + vtbl1_p8 (poly8x8_t tab, uint8x8_t idx) + { + poly8x8_t result; +- poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (UINT64_C (0x0))); ++ poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" + : "=w"(result) + : "w"(temp), "w"(idx) +@@ -19096,7 +17064,7 @@ + int8x8_t result; + int8x16x2_t temp; + temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" + "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" + : "=w"(result) +@@ -19111,7 +17079,7 @@ + uint8x8_t result; + uint8x16x2_t temp; + temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" + "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" + : "=w"(result) +@@ -19126,7 +17094,7 @@ + poly8x8_t result; + poly8x16x2_t temp; + temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" + "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" + : "=w"(result) +@@ -19185,7 +17153,7 @@ + { + int8x8_t result; + int8x8_t tmp1; +- int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("movi %0.8b, 8\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" + "tbl %1.8b, {%2.16b}, %3.8b\n\t" +@@ -19201,7 +17169,7 @@ + { + uint8x8_t result; + uint8x8_t tmp1; +- uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("movi %0.8b, 8\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" + "tbl %1.8b, {%2.16b}, %3.8b\n\t" +@@ -19217,7 +17185,7 @@ + { + poly8x8_t result; + poly8x8_t tmp1; +- poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (UINT64_C (0x0))); ++ poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("movi %0.8b, 8\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" + "tbl %1.8b, {%2.16b}, %3.8b\n\t" +@@ -19271,7 +17239,7 @@ + int8x8_t tmp1; + int8x16x2_t temp; + temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" + "movi %0.8b, 24\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" +@@ -19290,7 +17258,7 @@ + uint8x8_t tmp1; + uint8x16x2_t temp; + temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" + "movi %0.8b, 24\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" +@@ -19309,7 +17277,7 @@ + poly8x8_t tmp1; + poly8x16x2_t temp; + temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" + "movi %0.8b, 24\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" +@@ -19370,6 +17338,80 @@ /* Start of optimal implementations in approved order. */ @@ -15301,7 +17552,7 @@ /* vadd */ __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -@@ -19384,8 +17446,238 @@ +@@ -19384,8 +17426,238 @@ return __a + __b; } @@ -15541,7 +17792,7 @@ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vceq_p8 (poly8x8_t __a, poly8x8_t __b) { -@@ -19414,7 +17706,7 @@ +@@ -19414,7 +17686,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_s64 (int64x1_t __a, int64x1_t __b) { @@ -15550,7 +17801,7 @@ } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -19441,10 +17733,21 @@ +@@ -19441,10 +17713,21 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_u64 (uint64x1_t __a, uint64x1_t __b) { @@ -15574,7 +17825,7 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vceqq_p8 (poly8x16_t __a, poly8x16_t __b) { -@@ -19504,27 +17807,245 @@ +@@ -19504,27 +17787,245 @@ (int64x2_t) __b); } @@ -15824,7 +18075,7 @@ vcge_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgev8qi (__a, __b); -@@ -19545,38 +18066,56 @@ +@@ -19545,38 +18046,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_s64 (int64x1_t __a, int64x1_t __b) { @@ -15887,7 +18138,7 @@ vcgeq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgev16qi (__a, __b); -@@ -19603,53 +18142,270 @@ +@@ -19603,53 +18122,270 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -16167,7 +18418,7 @@ vcgt_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__a, __b); -@@ -19670,38 +18426,56 @@ +@@ -19670,38 +18406,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_s64 (int64x1_t __a, int64x1_t __b) { @@ -16230,7 +18481,7 @@ vcgtq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__a, __b); -@@ -19728,53 +18502,270 @@ +@@ -19728,53 +18482,270 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -16510,7 +18761,7 @@ vcle_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgev8qi (__b, __a); -@@ -19795,38 +18786,56 @@ +@@ -19795,38 +18766,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_s64 (int64x1_t __a, int64x1_t __b) { @@ -16573,7 +18824,7 @@ vcleq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgev16qi (__b, __a); -@@ -19853,46 +18862,213 @@ +@@ -19853,46 +18842,213 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -16794,7 +19045,7 @@ vclt_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__b, __a); -@@ -19913,38 +19089,56 @@ +@@ -19913,38 +19069,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_s64 (int64x1_t __a, int64x1_t __b) { @@ -16857,7 +19108,7 @@ vcltq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__b, __a); -@@ -19971,91 +19165,664 @@ +@@ -19971,91 +19145,664 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -17536,7 +19787,7 @@ } /* vld1 */ -@@ -21088,7 +20855,7 @@ +@@ -21088,7 +20835,7 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmax_f32 (float32x2_t __a, float32x2_t __b) { @@ -17545,7 +19796,7 @@ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -21133,13 +20900,13 @@ +@@ -21133,13 +20880,13 @@ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmaxq_f32 (float32x4_t __a, float32x4_t __b) { @@ -17561,7 +19812,7 @@ } __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -@@ -21181,12 +20948,150 @@ +@@ -21181,12 +20928,150 @@ (int32x4_t) __b); } @@ -17714,7 +19965,7 @@ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -21231,13 +21136,13 @@ +@@ -21231,13 +21116,13 @@ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vminq_f32 (float32x4_t __a, float32x4_t __b) { @@ -17730,7 +19981,7 @@ } __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -@@ -21279,6 +21184,144 @@ +@@ -21279,6 +21164,144 @@ (int32x4_t) __b); } @@ -17875,7 +20126,61 @@ /* vmla */ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -@@ -22795,6 +22838,223 @@ +@@ -21430,7 +21453,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d) + { +- int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (INT64_C (0))); ++ int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __tmp, __d); + } + +@@ -21481,7 +21504,7 @@ + __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) + vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d) + { +- int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (INT64_C (0))); ++ int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __tmp, __d); + } + +@@ -21558,7 +21581,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d) + { +- int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (INT64_C (0))); ++ int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __tmp, __d); + } + +@@ -21609,7 +21632,7 @@ + __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) + vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d) + { +- int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (INT64_C (0))); ++ int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __tmp, __d); + } + +@@ -21734,7 +21757,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, int const __c) + { +- int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0))); ++ int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmull_lanev4hi (__a, __tmp, __c); + } + +@@ -21783,7 +21806,7 @@ + __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) + vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, int const __c) + { +- int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0))); ++ int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmull_lanev2si (__a, __tmp, __c); + } + +@@ -22795,6 +22818,223 @@ return (uint64x1_t) __builtin_aarch64_uqsubdi (__a, __b); } @@ -18099,7 +20404,7 @@ /* vrshl */ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -23138,109 +23398,109 @@ +@@ -23138,109 +23378,109 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vshl_n_s8 (int8x8_t __a, const int __b) { @@ -18227,7 +20532,7 @@ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -23428,109 +23688,109 @@ +@@ -23428,109 +23668,109 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vshr_n_s8 (int8x8_t __a, const int __b) { @@ -18355,7 +20660,475 @@ } /* vsli */ -@@ -25159,7 +25419,7 @@ +@@ -24153,8 +24393,8 @@ + { + __builtin_aarch64_simd_oi __o; + int64x2x2_t temp; +- temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (INT64_C (0))); +- temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (INT64_C (0))); ++ temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1); + __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o); +@@ -24165,8 +24405,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint64x2x2_t temp; +- temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (UINT64_C (0))); +- temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (UINT64_C (0))); ++ temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1); + __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o); +@@ -24177,8 +24417,8 @@ + { + __builtin_aarch64_simd_oi __o; + float64x2x2_t temp; +- temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (UINT64_C (0))); +- temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (UINT64_C (0))); ++ temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1); + __builtin_aarch64_st2df ((__builtin_aarch64_simd_df *) __a, __o); +@@ -24189,8 +24429,8 @@ + { + __builtin_aarch64_simd_oi __o; + int8x16x2_t temp; +- temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (INT64_C (0))); +- temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (INT64_C (0))); ++ temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1); + __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o); +@@ -24201,8 +24441,8 @@ + { + __builtin_aarch64_simd_oi __o; + poly8x16x2_t temp; +- temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (UINT64_C (0))); +- temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (UINT64_C (0))); ++ temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1); + __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o); +@@ -24213,8 +24453,8 @@ + { + __builtin_aarch64_simd_oi __o; + int16x8x2_t temp; +- temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (INT64_C (0))); +- temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (INT64_C (0))); ++ temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1); + __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o); +@@ -24225,8 +24465,8 @@ + { + __builtin_aarch64_simd_oi __o; + poly16x8x2_t temp; +- temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (UINT64_C (0))); +- temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (UINT64_C (0))); ++ temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1); + __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o); +@@ -24237,8 +24477,8 @@ + { + __builtin_aarch64_simd_oi __o; + int32x4x2_t temp; +- temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (INT64_C (0))); +- temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (INT64_C (0))); ++ temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1); + __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o); +@@ -24249,8 +24489,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint8x16x2_t temp; +- temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (UINT64_C (0))); +- temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (UINT64_C (0))); ++ temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1); + __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o); +@@ -24261,8 +24501,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint16x8x2_t temp; +- temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (UINT64_C (0))); +- temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (UINT64_C (0))); ++ temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1); + __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o); +@@ -24273,8 +24513,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint32x4x2_t temp; +- temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (UINT64_C (0))); +- temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (UINT64_C (0))); ++ temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1); + __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o); +@@ -24285,8 +24525,8 @@ + { + __builtin_aarch64_simd_oi __o; + float32x4x2_t temp; +- temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (UINT64_C (0))); +- temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (UINT64_C (0))); ++ temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1); + __builtin_aarch64_st2v2sf ((__builtin_aarch64_simd_sf *) __a, __o); +@@ -24405,9 +24645,9 @@ + { + __builtin_aarch64_simd_ci __o; + int64x2x3_t temp; +- temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (INT64_C (0))); +- temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (INT64_C (0))); +- temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (INT64_C (0))); ++ temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24419,9 +24659,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint64x2x3_t temp; +- temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (UINT64_C (0))); +- temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (UINT64_C (0))); +- temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (UINT64_C (0))); ++ temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24433,9 +24673,9 @@ + { + __builtin_aarch64_simd_ci __o; + float64x2x3_t temp; +- temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (UINT64_C (0))); +- temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (UINT64_C (0))); +- temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (UINT64_C (0))); ++ temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2); +@@ -24447,9 +24687,9 @@ + { + __builtin_aarch64_simd_ci __o; + int8x16x3_t temp; +- temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (INT64_C (0))); +- temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (INT64_C (0))); +- temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (INT64_C (0))); ++ temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24461,9 +24701,9 @@ + { + __builtin_aarch64_simd_ci __o; + poly8x16x3_t temp; +- temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (UINT64_C (0))); +- temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (UINT64_C (0))); +- temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (UINT64_C (0))); ++ temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24475,9 +24715,9 @@ + { + __builtin_aarch64_simd_ci __o; + int16x8x3_t temp; +- temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (INT64_C (0))); +- temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (INT64_C (0))); +- temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (INT64_C (0))); ++ temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24489,9 +24729,9 @@ + { + __builtin_aarch64_simd_ci __o; + poly16x8x3_t temp; +- temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (UINT64_C (0))); +- temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (UINT64_C (0))); +- temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (UINT64_C (0))); ++ temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24503,9 +24743,9 @@ + { + __builtin_aarch64_simd_ci __o; + int32x4x3_t temp; +- temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (INT64_C (0))); +- temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (INT64_C (0))); +- temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (INT64_C (0))); ++ temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24517,9 +24757,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint8x16x3_t temp; +- temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (UINT64_C (0))); +- temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (UINT64_C (0))); +- temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (UINT64_C (0))); ++ temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24531,9 +24771,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint16x8x3_t temp; +- temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (UINT64_C (0))); +- temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (UINT64_C (0))); +- temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (UINT64_C (0))); ++ temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24545,9 +24785,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint32x4x3_t temp; +- temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (UINT64_C (0))); +- temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (UINT64_C (0))); +- temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (UINT64_C (0))); ++ temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24559,9 +24799,9 @@ + { + __builtin_aarch64_simd_ci __o; + float32x4x3_t temp; +- temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (UINT64_C (0))); +- temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (UINT64_C (0))); +- temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (UINT64_C (0))); ++ temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2); +@@ -24693,10 +24933,10 @@ + { + __builtin_aarch64_simd_xi __o; + int64x2x4_t temp; +- temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (INT64_C (0))); +- temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (INT64_C (0))); +- temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (INT64_C (0))); +- temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (INT64_C (0))); ++ temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24709,10 +24949,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint64x2x4_t temp; +- temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (UINT64_C (0))); +- temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (UINT64_C (0))); +- temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (UINT64_C (0))); +- temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (UINT64_C (0))); ++ temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24725,10 +24965,10 @@ + { + __builtin_aarch64_simd_xi __o; + float64x2x4_t temp; +- temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (UINT64_C (0))); +- temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (UINT64_C (0))); +- temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (UINT64_C (0))); +- temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (UINT64_C (0))); ++ temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[2], 2); +@@ -24741,10 +24981,10 @@ + { + __builtin_aarch64_simd_xi __o; + int8x16x4_t temp; +- temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (INT64_C (0))); +- temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (INT64_C (0))); +- temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (INT64_C (0))); +- temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (INT64_C (0))); ++ temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24757,10 +24997,10 @@ + { + __builtin_aarch64_simd_xi __o; + poly8x16x4_t temp; +- temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (UINT64_C (0))); +- temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (UINT64_C (0))); +- temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (UINT64_C (0))); +- temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (UINT64_C (0))); ++ temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24773,10 +25013,10 @@ + { + __builtin_aarch64_simd_xi __o; + int16x8x4_t temp; +- temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (INT64_C (0))); +- temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (INT64_C (0))); +- temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (INT64_C (0))); +- temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (INT64_C (0))); ++ temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24789,10 +25029,10 @@ + { + __builtin_aarch64_simd_xi __o; + poly16x8x4_t temp; +- temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (UINT64_C (0))); +- temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (UINT64_C (0))); +- temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (UINT64_C (0))); +- temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (UINT64_C (0))); ++ temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24805,10 +25045,10 @@ + { + __builtin_aarch64_simd_xi __o; + int32x4x4_t temp; +- temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (INT64_C (0))); +- temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (INT64_C (0))); +- temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (INT64_C (0))); +- temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (INT64_C (0))); ++ temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24821,10 +25061,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint8x16x4_t temp; +- temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (UINT64_C (0))); +- temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (UINT64_C (0))); +- temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (UINT64_C (0))); +- temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (UINT64_C (0))); ++ temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24837,10 +25077,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint16x8x4_t temp; +- temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (UINT64_C (0))); +- temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (UINT64_C (0))); +- temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (UINT64_C (0))); +- temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (UINT64_C (0))); ++ temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24853,10 +25093,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint32x4x4_t temp; +- temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (UINT64_C (0))); +- temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (UINT64_C (0))); +- temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (UINT64_C (0))); +- temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (UINT64_C (0))); ++ temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24869,10 +25109,10 @@ + { + __builtin_aarch64_simd_xi __o; + float32x4x4_t temp; +- temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (UINT64_C (0))); +- temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (UINT64_C (0))); +- temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (UINT64_C (0))); +- temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (UINT64_C (0))); ++ temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[2], 2); +@@ -25159,7 +25399,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_s64 (int64x1_t __a, int64x1_t __b) { @@ -18364,7 +21137,7 @@ } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -25186,8 +25446,7 @@ +@@ -25186,8 +25426,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_u64 (uint64x1_t __a, uint64x1_t __b) { @@ -18374,7 +21147,7 @@ } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -25245,14 +25504,13 @@ +@@ -25245,14 +25484,13 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtstd_s64 (int64x1_t __a, int64x1_t __b) { @@ -18391,7 +21164,7 @@ } /* vuqadd */ -@@ -25371,4 +25629,31 @@ +@@ -25371,4 +25609,31 @@ /* End of optimal implementations in approved order. */ @@ -18425,7 +21198,7 @@ #endif --- a/src/gcc/config/aarch64/aarch64.md +++ b/src/gcc/config/aarch64/aarch64.md -@@ -68,9 +68,13 @@ +@@ -68,14 +68,19 @@ (define_c_enum "unspec" [ UNSPEC_CASESI UNSPEC_CLS @@ -18439,7 +21212,13 @@ UNSPEC_FRINTP UNSPEC_FRINTX UNSPEC_FRINTZ -@@ -230,6 +234,9 @@ + UNSPEC_GOTSMALLPIC + UNSPEC_GOTSMALLTLS ++ UNSPEC_GOTTINYPIC + UNSPEC_LD2 + UNSPEC_LD3 + UNSPEC_LD4 +@@ -230,6 +235,9 @@ fmovf2i,\ fmovi2f,\ fmul,\ @@ -18449,7 +21228,7 @@ frint,\ fsqrt,\ load_acq,\ -@@ -763,19 +770,41 @@ +@@ -763,19 +771,41 @@ ) (define_insn "*mov_aarch64" @@ -18502,7 +21281,7 @@ (set_attr "mode" "") (set_attr "simd_mode" "")] ) -@@ -797,26 +826,28 @@ +@@ -797,26 +827,28 @@ ) (define_insn "*movsi_aarch64" @@ -18526,7 +21305,7 @@ + [(set_attr "v8type" "move,alu,load1,load1,store1,store1,fmov,fmov,fmov") (set_attr "mode" "SI") - (set_attr "fp" "*,*,*,*,yes,yes,yes")] -+ (set_attr "fp" "*,*,*,*,*,*,yes,yes,yes")] ++ (set_attr "fp" "*,*,*,yes,*,yes,yes,yes,yes")] ) (define_insn "*movdi_aarch64" @@ -18537,7 +21316,7 @@ "(register_operand (operands[0], DImode) || aarch64_reg_or_zero (operands[1], DImode))" "@ -@@ -825,17 +856,19 @@ +@@ -825,17 +857,19 @@ mov\\t%x0, %1 mov\\t%x0, %1 ldr\\t%x0, %1 @@ -18555,12 +21334,12 @@ (set_attr "mode" "DI") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,yes")] -+ (set_attr "fp" "*,*,*,*,*,*,*,*,*,*,yes,yes,yes,*") ++ (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") + (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] ) (define_insn "insv_imm" -@@ -843,9 +876,8 @@ +@@ -843,9 +877,8 @@ (const_int 16) (match_operand:GPI 1 "const_int_operand" "n")) (match_operand:GPI 2 "const_int_operand" "n"))] @@ -18572,7 +21351,7 @@ "movk\\t%0, %X2, lsl %1" [(set_attr "v8type" "movk") (set_attr "mode" "")] -@@ -982,9 +1014,9 @@ +@@ -982,9 +1015,9 @@ || register_operand (operands[1], TFmode))" "@ orr\\t%0.16b, %1.16b, %1.16b @@ -18585,7 +21364,7 @@ movi\\t%0.2d, #0 fmov\\t%s0, wzr ldr\\t%q0, %1 -@@ -998,6 +1030,17 @@ +@@ -998,6 +1031,17 @@ (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")] ) @@ -18603,7 +21382,7 @@ ;; Operands 1 and 3 are tied together by the final condition; so we allow ;; fairly lax checking on the second memory operation. (define_insn "load_pair" -@@ -1150,13 +1193,14 @@ +@@ -1150,13 +1194,14 @@ ) (define_insn "*zero_extend2_aarch64" @@ -18622,7 +21401,7 @@ (set_attr "mode" "")] ) -@@ -1287,6 +1331,112 @@ +@@ -1287,6 +1332,112 @@ (set_attr "mode" "SI")] ) @@ -18735,7 +21514,25 @@ (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ -@@ -1791,6 +1941,34 @@ +@@ -1302,12 +1453,12 @@ + ) + + (define_insn "*compare_neg" +- [(set (reg:CC CC_REGNUM) +- (compare:CC +- (match_operand:GPI 0 "register_operand" "r") +- (neg:GPI (match_operand:GPI 1 "register_operand" "r"))))] ++ [(set (reg:CC_SWP CC_REGNUM) ++ (compare:CC_SWP ++ (neg:GPI (match_operand:GPI 0 "register_operand" "r")) ++ (match_operand:GPI 1 "register_operand" "r")))] + "" +- "cmn\\t%0, %1" ++ "cmn\\t%1, %0" + [(set_attr "v8type" "alus") + (set_attr "mode" "")] + ) +@@ -1791,6 +1942,34 @@ (set_attr "mode" "SI")] ) @@ -18770,7 +21567,7 @@ (define_insn "*sub_uxt_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "r") -@@ -1825,6 +2003,38 @@ +@@ -1825,6 +2004,38 @@ (set_attr "mode" "SI")] ) @@ -18809,7 +21606,7 @@ (define_insn "neg2" [(set (match_operand:GPI 0 "register_operand" "=r") (neg:GPI (match_operand:GPI 1 "register_operand" "r")))] -@@ -1844,6 +2054,27 @@ +@@ -1844,6 +2055,27 @@ (set_attr "mode" "SI")] ) @@ -18837,7 +21634,7 @@ (define_insn "*neg2_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r")) -@@ -1869,6 +2100,21 @@ +@@ -1869,6 +2101,21 @@ (set_attr "mode" "SI")] ) @@ -18859,7 +21656,7 @@ (define_insn "*neg__2" [(set (match_operand:GPI 0 "register_operand" "=r") (neg:GPI (ASHIFT:GPI -@@ -2158,6 +2404,18 @@ +@@ -2158,6 +2405,18 @@ (set_attr "mode" "")] ) @@ -18878,7 +21675,7 @@ ;; ------------------------------------------------------------------- ;; Store-flag and conditional select insns -@@ -2211,7 +2469,7 @@ +@@ -2211,7 +2470,7 @@ (set_attr "mode" "SI")] ) @@ -18887,7 +21684,7 @@ [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] -@@ -2434,6 +2692,69 @@ +@@ -2434,6 +2693,69 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "SI")]) @@ -18957,7 +21754,87 @@ (define_insn "*_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI -@@ -2704,6 +3025,62 @@ +@@ -2485,6 +2807,35 @@ + [(set_attr "v8type" "logic") + (set_attr "mode" "")]) + ++(define_insn "*and_one_cmpl3_compare0" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:GPI (not:GPI ++ (match_operand:GPI 1 "register_operand" "r")) ++ (match_operand:GPI 2 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:GPI 0 "register_operand" "=r") ++ (and:GPI (not:GPI (match_dup 1)) (match_dup 2)))] ++ "" ++ "bics\\t%0, %2, %1" ++ [(set_attr "v8type" "logics") ++ (set_attr "mode" "")]) ++ ++;; zero_extend version of above ++(define_insn "*and_one_cmplsi3_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:SI (not:SI ++ (match_operand:SI 1 "register_operand" "r")) ++ (match_operand:SI 2 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))] ++ "" ++ "bics\\t%w0, %w2, %w1" ++ [(set_attr "v8type" "logics") ++ (set_attr "mode" "SI")]) ++ + (define_insn "*_one_cmpl_3" + [(set (match_operand:GPI 0 "register_operand" "=r") + (LOGICAL:GPI (not:GPI +@@ -2497,6 +2848,43 @@ + [(set_attr "v8type" "logic_shift") + (set_attr "mode" "")]) + ++(define_insn "*and_one_cmpl_3_compare0" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:GPI (not:GPI ++ (SHIFT:GPI ++ (match_operand:GPI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_" "n"))) ++ (match_operand:GPI 3 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:GPI 0 "register_operand" "=r") ++ (and:GPI (not:GPI ++ (SHIFT:GPI ++ (match_dup 1) (match_dup 2))) (match_dup 3)))] ++ "" ++ "bics\\t%0, %3, %1, %2" ++ [(set_attr "v8type" "logics_shift") ++ (set_attr "mode" "")]) ++ ++;; zero_extend version of above ++(define_insn "*and_one_cmpl_si3_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:SI (not:SI ++ (SHIFT:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_si" "n"))) ++ (match_operand:SI 3 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (and:SI ++ (not:SI ++ (SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup 3))))] ++ "" ++ "bics\\t%w0, %w3, %w1, %2" ++ [(set_attr "v8type" "logics_shift") ++ (set_attr "mode" "SI")]) ++ + (define_insn "clz2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (clz:GPI (match_operand:GPI 1 "register_operand" "r")))] +@@ -2704,6 +3092,62 @@ (set_attr "mode" "")] ) @@ -19020,7 +21897,7 @@ (define_insn "*_ashl" [(set (match_operand:GPI 0 "register_operand" "=r") (ANY_EXTEND:GPI -@@ -2770,6 +3147,50 @@ +@@ -2770,6 +3214,65 @@ (set_attr "mode" "")] ) @@ -19068,10 +21945,25 @@ + (set_attr "mode" "")] +) + ++(define_insn "*extr_insv_lower_reg" ++ [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") ++ (match_operand 1 "const_int_operand" "n") ++ (const_int 0)) ++ (zero_extract:GPI (match_operand:GPI 2 "register_operand" "+r") ++ (match_dup 1) ++ (match_operand 3 "const_int_operand" "n")))] ++ "!(UINTVAL (operands[1]) == 0 ++ || (UINTVAL (operands[3]) + UINTVAL (operands[1]) ++ > GET_MODE_BITSIZE (mode)))" ++ "bfxil\\t%0, %2, %3, %1" ++ [(set_attr "v8type" "bfm") ++ (set_attr "mode" "")] ++) ++ (define_insn "*_shft_" [(set (match_operand:GPI 0 "register_operand" "=r") (ashift:GPI (ANY_EXTEND:GPI -@@ -3090,6 +3511,27 @@ +@@ -3090,6 +3593,27 @@ (set_attr "mode" "")] ) @@ -19099,7 +21991,7 @@ ;; ------------------------------------------------------------------- ;; Reload support ;; ------------------------------------------------------------------- -@@ -3146,9 +3588,9 @@ +@@ -3146,9 +3670,9 @@ ;; after or during reload as we don't want these patterns to start ;; kicking in during the combiner. @@ -19111,7 +22003,7 @@ "reload_completed || reload_in_progress" "fmov\\t%x0, %d1" [(set_attr "v8type" "fmovf2i") -@@ -3156,10 +3598,10 @@ +@@ -3156,10 +3680,10 @@ (set_attr "length" "4") ]) @@ -19124,7 +22016,7 @@ (const_int 64))))] "reload_completed || reload_in_progress" "fmov\\t%x0, %1.d[1]" -@@ -3168,24 +3610,22 @@ +@@ -3168,24 +3692,22 @@ (set_attr "length" "4") ]) @@ -19155,7 +22047,7 @@ [(set_attr "v8type" "fmovi2f") (set_attr "mode" "DI") (set_attr "length" "4") -@@ -3197,7 +3637,6 @@ +@@ -3197,7 +3719,6 @@ (truncate:DI (match_operand:TI 1 "register_operand" "w"))))] "reload_completed || reload_in_progress" "fmov\\t%d0, %d1" @@ -19163,6 +22055,30 @@ [(set_attr "v8type" "fmovi2f") (set_attr "mode" "DI") (set_attr "length" "4") +@@ -3231,6 +3752,16 @@ + (set_attr "mode" "DI")] + ) + ++(define_insn "ldr_got_tiny" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "S")] ++ UNSPEC_GOTTINYPIC))] ++ "" ++ "ldr\\t%0, %L1" ++ [(set_attr "v8type" "load1") ++ (set_attr "mode" "DI")] ++) ++ + (define_insn "aarch64_load_tp_hard" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_TLS))] +--- a/src/gcc/config/aarch64/aarch64-option-extensions.def ++++ b/src/gcc/config/aarch64/aarch64-option-extensions.def +@@ -35,3 +35,4 @@ + AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, AARCH64_FL_FPSIMD | AARCH64_FL_CRYPTO) + AARCH64_OPT_EXTENSION("simd", AARCH64_FL_FPSIMD, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO) + AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO | AARCH64_FL_FPSIMD, AARCH64_FL_CRYPTO) ++AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, AARCH64_FL_CRC) --- a/src/gcc/config/aarch64/aarch64-builtins.c +++ b/src/gcc/config/aarch64/aarch64-builtins.c @@ -30,6 +30,7 @@ @@ -19747,7 +22663,7 @@ + --- a/src/gcc/config/aarch64/aarch64-protos.h +++ b/src/gcc/config/aarch64/aarch64-protos.h -@@ -68,6 +68,13 @@ +@@ -68,6 +68,24 @@ Each of of these represents a thread-local symbol, and corresponds to the thread local storage relocation operator for the symbol being referred to. @@ -19758,18 +22674,30 @@ + + ADR x0, foo + ++ SYMBOL_TINY_GOT ++ ++ Generate symbol accesses via the GOT using a single PC relative ++ instruction. To compute the address of symbol foo, we generate: ++ ++ ldr t0, :got:foo ++ ++ The value of foo can subsequently read using: ++ ++ ldrb t0, [t0] ++ SYMBOL_FORCE_TO_MEM : Global variables are addressed using constant pool. All variable addresses are spilled into constant pools. The constant pools themselves are addressed using PC -@@ -81,6 +88,7 @@ +@@ -81,6 +99,8 @@ SYMBOL_SMALL_TLSDESC, SYMBOL_SMALL_GOTTPREL, SYMBOL_SMALL_TPREL, + SYMBOL_TINY_ABSOLUTE, ++ SYMBOL_TINY_GOT, SYMBOL_FORCE_TO_MEM }; -@@ -126,35 +134,66 @@ +@@ -126,35 +146,66 @@ const int FP2FP; }; @@ -19838,7 +22766,7 @@ bool aarch64_uimm12_shift (HOST_WIDE_INT); const char *aarch64_output_casesi (rtx *); enum aarch64_symbol_type aarch64_classify_symbol (rtx, -@@ -165,9 +204,6 @@ +@@ -165,9 +216,6 @@ int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode); int aarch64_hard_regno_nregs (unsigned, enum machine_mode); int aarch64_simd_attr_length_move (rtx); @@ -19848,7 +22776,7 @@ int aarch64_uxt_size (int, HOST_WIDE_INT); rtx aarch64_final_eh_return_addr (void); rtx aarch64_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); -@@ -177,6 +213,7 @@ +@@ -177,6 +225,7 @@ bool aarch64_simd_mem_operand_p (rtx); rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool); rtx aarch64_tls_get_addr (void); @@ -19856,16 +22784,18 @@ unsigned aarch64_dbx_register_number (unsigned); unsigned aarch64_trampoline_size (void); void aarch64_asm_output_labelref (FILE *, const char *); -@@ -216,6 +253,8 @@ +@@ -216,6 +265,10 @@ bool aarch64_split_128bit_move_p (rtx, rtx); ++void aarch64_split_simd_combine (rtx, rtx, rtx); ++ +void aarch64_split_simd_move (rtx, rtx); + /* Check for a legitimate floating point constant for FMOV. */ bool aarch64_float_const_representable_p (rtx); -@@ -249,6 +288,4 @@ +@@ -249,6 +302,4 @@ extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); extern bool aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); @@ -20545,7 +23475,18 @@ emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm)); emit_insn (gen_ldr_got_small (dest, tmp_reg, imm)); return; -@@ -604,49 +636,85 @@ +@@ -581,6 +613,10 @@ + return; + } + ++ case SYMBOL_TINY_GOT: ++ emit_insn (gen_ldr_got_tiny (dest, imm)); ++ return; ++ + default: + gcc_unreachable (); + } +@@ -604,49 +640,85 @@ { rtx low_dst; @@ -20660,10 +23601,53 @@ } bool -@@ -656,11 +724,56 @@ +@@ -656,11 +728,99 @@ || ! (FP_REGNUM_P (REGNO (dst)) && FP_REGNUM_P (REGNO (src)))); } ++/* Split a complex SIMD combine. */ ++ ++void ++aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2) ++{ ++ enum machine_mode src_mode = GET_MODE (src1); ++ enum machine_mode dst_mode = GET_MODE (dst); ++ ++ gcc_assert (VECTOR_MODE_P (dst_mode)); ++ ++ if (REG_P (dst) && REG_P (src1) && REG_P (src2)) ++ { ++ rtx (*gen) (rtx, rtx, rtx); ++ ++ switch (src_mode) ++ { ++ case V8QImode: ++ gen = gen_aarch64_simd_combinev8qi; ++ break; ++ case V4HImode: ++ gen = gen_aarch64_simd_combinev4hi; ++ break; ++ case V2SImode: ++ gen = gen_aarch64_simd_combinev2si; ++ break; ++ case V2SFmode: ++ gen = gen_aarch64_simd_combinev2sf; ++ break; ++ case DImode: ++ gen = gen_aarch64_simd_combinedi; ++ break; ++ case DFmode: ++ gen = gen_aarch64_simd_combinedf; ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ emit_insn (gen (dst, src1, src2)); ++ return; ++ } ++} ++ +/* Split a complex SIMD move. */ + +void @@ -20719,7 +23703,7 @@ else { x = aarch64_emit_move (x, value); -@@ -672,15 +785,16 @@ +@@ -672,15 +832,16 @@ static rtx aarch64_add_offset (enum machine_mode mode, rtx temp, rtx reg, HOST_WIDE_INT offset) { @@ -20739,7 +23723,7 @@ } return plus_constant (mode, reg, offset); } -@@ -719,7 +833,7 @@ +@@ -719,7 +880,7 @@ && targetm.cannot_force_const_mem (mode, imm)) { gcc_assert(can_create_pseudo_p ()); @@ -20748,7 +23732,11 @@ base = aarch64_add_offset (mode, NULL, base, INTVAL (offset)); aarch64_emit_move (dest, base); return; -@@ -736,7 +850,7 @@ +@@ -733,10 +894,11 @@ + case SYMBOL_SMALL_TLSDESC: + case SYMBOL_SMALL_GOTTPREL: + case SYMBOL_SMALL_GOT: ++ case SYMBOL_TINY_GOT: if (offset != const0_rtx) { gcc_assert(can_create_pseudo_p ()); @@ -20757,7 +23745,7 @@ base = aarch64_add_offset (mode, NULL, base, INTVAL (offset)); aarch64_emit_move (dest, base); return; -@@ -745,6 +859,7 @@ +@@ -745,6 +907,7 @@ case SYMBOL_SMALL_TPREL: case SYMBOL_SMALL_ABSOLUTE: @@ -20765,7 +23753,7 @@ aarch64_load_symref_appropriately (dest, imm, sty); return; -@@ -2553,12 +2668,14 @@ +@@ -2553,12 +2716,14 @@ aarch64_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) { rtx base, offset; @@ -20781,7 +23769,7 @@ return aarch64_tls_referenced_p (x); } -@@ -2996,10 +3113,13 @@ +@@ -2996,10 +3161,13 @@ /* Classify the base of symbolic expression X, given that X appears in context CONTEXT. */ @@ -20797,7 +23785,7 @@ split_const (x, &x, &offset); return aarch64_classify_symbol (x, context); } -@@ -3087,7 +3207,8 @@ +@@ -3087,17 +3255,19 @@ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) && y == const0_rtx && (code == EQ || code == NE || code == LT || code == GE) @@ -20806,8 +23794,21 @@ + || GET_CODE (x) == NEG)) return CC_NZmode; - /* A compare with a shifted operand. Because of canonicalization, -@@ -3282,26 +3403,6 @@ +- /* A compare with a shifted operand. Because of canonicalization, ++ /* A compare with a shifted or negated operand. Because of canonicalization, + the comparison will have to be swapped when we emit the assembly + code. */ + if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) + && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG) + && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT + || GET_CODE (x) == LSHIFTRT +- || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)) ++ || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND ++ || GET_CODE (x) == NEG)) + return CC_SWPmode; + + /* A compare of a mode narrower than SI mode against zero can be done +@@ -3282,26 +3452,6 @@ asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]); break; @@ -20834,7 +23835,7 @@ case 'm': /* Print a condition (eq, ne, etc). */ -@@ -3349,7 +3450,7 @@ +@@ -3349,7 +3499,7 @@ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); return; } @@ -20843,7 +23844,7 @@ break; case 'S': -@@ -3362,18 +3463,17 @@ +@@ -3362,18 +3512,17 @@ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); return; } @@ -20865,7 +23866,7 @@ break; case 'w': -@@ -3383,20 +3483,19 @@ +@@ -3383,20 +3532,19 @@ if (x == const0_rtx || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x))) { @@ -20889,7 +23890,43 @@ break; } -@@ -4601,6 +4700,101 @@ +@@ -3504,6 +3652,10 @@ + asm_fprintf (asm_out_file, ":tprel:"); + break; + ++ case SYMBOL_TINY_GOT: ++ gcc_unreachable (); ++ break; ++ + default: + break; + } +@@ -3533,6 +3685,10 @@ + asm_fprintf (asm_out_file, ":tprel_lo12_nc:"); + break; + ++ case SYMBOL_TINY_GOT: ++ asm_fprintf (asm_out_file, ":got:"); ++ break; ++ + default: + break; + } +@@ -3647,13 +3803,6 @@ + output_addr_const (f, x); + } + +-void +-aarch64_function_profiler (FILE *f ATTRIBUTE_UNUSED, +- int labelno ATTRIBUTE_UNUSED) +-{ +- sorry ("function profiling"); +-} +- + bool + aarch64_label_mentioned_p (rtx x) + { +@@ -4601,6 +4750,101 @@ return aarch64_tune_params->memmov_cost; } @@ -20991,7 +24028,7 @@ static void initialize_aarch64_code_model (void); /* Parse the architecture extension string. */ -@@ -4956,6 +5150,7 @@ +@@ -4956,6 +5200,7 @@ /* Return the method that should be used to access SYMBOL_REF or LABEL_REF X in context CONTEXT. */ @@ -20999,7 +24036,7 @@ enum aarch64_symbol_type aarch64_classify_symbol (rtx x, enum aarch64_symbol_context context ATTRIBUTE_UNUSED) -@@ -4969,6 +5164,8 @@ +@@ -4969,6 +5214,8 @@ case AARCH64_CMODEL_TINY_PIC: case AARCH64_CMODEL_TINY: @@ -21008,7 +24045,7 @@ case AARCH64_CMODEL_SMALL_PIC: case AARCH64_CMODEL_SMALL: return SYMBOL_SMALL_ABSOLUTE; -@@ -4978,71 +5175,47 @@ +@@ -4978,71 +5225,47 @@ } } @@ -21054,7 +24091,7 @@ - case AARCH64_CMODEL_SMALL_PIC: + case AARCH64_CMODEL_TINY_PIC: + if (!aarch64_symbol_binds_local_p (x)) -+ return SYMBOL_SMALL_GOT; ++ return SYMBOL_TINY_GOT; + return SYMBOL_TINY_ABSOLUTE; - if (CONSTANT_POOL_ADDRESS_P (x)) @@ -21105,7 +24142,7 @@ aarch64_constant_address_p (rtx x) { return (CONSTANT_P (x) && memory_address_p (DImode, x)); -@@ -5092,8 +5265,7 @@ +@@ -5092,8 +5315,7 @@ /* This could probably go away because we now decompose CONST_INTs according to expand_mov_immediate. */ if ((GET_CODE (x) == CONST_VECTOR @@ -21115,7 +24152,7 @@ || CONST_INT_P (x) || aarch64_valid_floating_const (mode, x)) return !targetm.cannot_force_const_mem (mode, x); -@@ -5924,32 +6096,57 @@ +@@ -5924,32 +6146,57 @@ return false; } @@ -21193,7 +24230,7 @@ /* Return the bitmask of possible vector sizes for the vectorizer to iterate over. */ static unsigned int -@@ -6037,7 +6234,7 @@ +@@ -6037,7 +6284,7 @@ } /* Return the equivalent letter for size. */ @@ -21202,7 +24239,7 @@ sizetochar (int size) { switch (size) -@@ -6084,15 +6281,10 @@ +@@ -6084,15 +6331,10 @@ return aarch64_float_const_representable_p (x0); } @@ -21222,7 +24259,7 @@ { #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \ matches = 1; \ -@@ -6103,7 +6295,6 @@ +@@ -6103,7 +6345,6 @@ { \ immtype = (CLASS); \ elsize = (ELSIZE); \ @@ -21230,7 +24267,7 @@ eshift = (SHIFT); \ emvn = (NEG); \ break; \ -@@ -6112,36 +6303,25 @@ +@@ -6112,36 +6353,25 @@ unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); unsigned char bytes[16]; @@ -21278,7 +24315,7 @@ } /* Splat vector constant out into a byte vector. */ -@@ -6215,16 +6395,16 @@ +@@ -6215,16 +6445,16 @@ CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1], 8, 1); CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] @@ -21299,7 +24336,7 @@ CHECK (1, 8, 16, bytes[i] == bytes[0], 0, 0); -@@ -6233,31 +6413,20 @@ +@@ -6233,31 +6463,20 @@ } while (0); @@ -21341,7 +24378,7 @@ /* Un-invert bytes of recognized vector, if necessary. */ if (invmask != 0) for (i = 0; i < idx; i++) -@@ -6272,68 +6441,27 @@ +@@ -6272,68 +6491,27 @@ imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) << (i * BITS_PER_UNIT); @@ -21422,7 +24459,7 @@ static bool aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT minval, -@@ -6395,6 +6523,25 @@ +@@ -6395,6 +6573,25 @@ return true; } @@ -21448,7 +24485,7 @@ /* Return a const_int vector of VAL. */ rtx aarch64_simd_gen_const_vector_dup (enum machine_mode mode, int val) -@@ -6409,6 +6556,19 @@ +@@ -6409,6 +6606,19 @@ return gen_rtx_CONST_VECTOR (mode, v); } @@ -21468,7 +24505,7 @@ /* Construct and return a PARALLEL RTX vector. */ rtx aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high) -@@ -6634,8 +6794,7 @@ +@@ -6634,8 +6844,7 @@ gcc_unreachable (); if (const_vec != NULL_RTX @@ -21478,7 +24515,7 @@ /* Load using MOVI/MVNI. */ return const_vec; else if ((const_dup = aarch64_simd_dup_constant (vals)) != NULL_RTX) -@@ -7193,49 +7352,80 @@ +@@ -7193,49 +7402,80 @@ } char* @@ -21582,7 +24619,7 @@ /* Split operands into moves from op[1] + op[2] into op[0]. */ void -@@ -7860,6 +8050,9 @@ +@@ -7860,6 +8100,9 @@ #undef TARGET_EXPAND_BUILTIN_VA_START #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start @@ -21592,7 +24629,7 @@ #undef TARGET_FUNCTION_ARG #define TARGET_FUNCTION_ARG aarch64_function_arg -@@ -7881,6 +8074,9 @@ +@@ -7881,6 +8124,9 @@ #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required @@ -21602,7 +24639,7 @@ #undef TARGET_GIMPLIFY_VA_ARG_EXPR #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr -@@ -7960,6 +8156,13 @@ +@@ -7960,6 +8206,13 @@ #undef TARGET_ARRAY_MODE_SUPPORTED_P #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p @@ -21712,7 +24749,17 @@ ;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") -@@ -435,6 +446,15 @@ +@@ -380,7 +391,8 @@ + ;; Double modes of vector modes (lower case). + (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") + (V2SI "v4si") (V2SF "v4sf") +- (SI "v2si") (DI "v2di")]) ++ (SI "v2si") (DI "v2di") ++ (DF "v2df")]) + + ;; Narrowed modes for VDN. + (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") +@@ -435,6 +447,15 @@ (V2SF "s") (V4SF "s") (V2DF "d")]) @@ -21728,7 +24775,7 @@ ;; Double vector types for ALLX. (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) -@@ -444,7 +464,8 @@ +@@ -444,7 +465,8 @@ (V2SI "V2SI") (V4SI "V4SI") (DI "DI") (V2DI "V2DI") (V2SF "V2SI") (V4SF "V4SI") @@ -21738,7 +24785,7 @@ ;; Lower case mode of results of comparison operations. (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") -@@ -452,7 +473,8 @@ +@@ -452,7 +474,8 @@ (V2SI "v2si") (V4SI "v4si") (DI "di") (V2DI "v2di") (V2SF "v2si") (V4SF "v4si") @@ -21748,7 +24795,7 @@ ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") -@@ -528,9 +550,14 @@ +@@ -528,9 +551,14 @@ ;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix]) @@ -21763,7 +24810,7 @@ ;; Code iterator for variants of vector max and min. (define_code_iterator ADDSUB [plus minus]) -@@ -543,6 +570,15 @@ +@@ -543,6 +571,15 @@ ;; Code iterator for signed variants of vector saturating binary ops. (define_code_iterator SBINQOPS [ss_plus ss_minus]) @@ -21779,7 +24826,7 @@ ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- -@@ -555,6 +591,10 @@ +@@ -555,6 +592,10 @@ (zero_extend "zero_extend") (sign_extract "extv") (zero_extract "extzv") @@ -21790,7 +24837,7 @@ (and "and") (ior "ior") (xor "xor") -@@ -571,12 +611,37 @@ +@@ -571,12 +612,37 @@ (eq "eq") (ne "ne") (lt "lt") @@ -21829,7 +24876,7 @@ (ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")]) -@@ -601,7 +666,9 @@ +@@ -601,7 +667,9 @@ (define_code_attr su [(sign_extend "s") (zero_extend "u") (sign_extract "s") (zero_extract "u") (fix "s") (unsigned_fix "u") @@ -21840,7 +24887,7 @@ ;; Emit cbz/cbnz depending on comparison type. (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) -@@ -610,10 +677,10 @@ +@@ -610,10 +678,10 @@ (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) ;; Max/min attributes. @@ -21855,7 +24902,7 @@ ;; MLA/MLS attributes. (define_code_attr as [(ss_plus "a") (ss_minus "s")]) -@@ -635,8 +702,11 @@ +@@ -635,8 +703,11 @@ (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV UNSPEC_SMAXV UNSPEC_SMINV]) @@ -21868,7 +24915,7 @@ (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD UNSPEC_SRHADD UNSPEC_URHADD UNSPEC_SHSUB UNSPEC_UHSUB -@@ -649,7 +719,7 @@ +@@ -649,7 +720,7 @@ (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) @@ -21877,7 +24924,7 @@ (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) -@@ -680,35 +750,44 @@ +@@ -680,35 +751,44 @@ UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) @@ -21938,7 +24985,7 @@ (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") -@@ -719,6 +798,7 @@ +@@ -719,6 +799,7 @@ (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") @@ -21946,7 +24993,7 @@ (UNSPEC_SSLI "s") (UNSPEC_USLI "u") (UNSPEC_SSRI "s") (UNSPEC_USRI "u") (UNSPEC_USRA "u") (UNSPEC_SSRA "s") -@@ -768,12 +848,6 @@ +@@ -768,12 +849,6 @@ (UNSPEC_RADDHN2 "add") (UNSPEC_RSUBHN2 "sub")]) @@ -21959,7 +25006,7 @@ (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) -@@ -783,15 +857,18 @@ +@@ -783,15 +858,18 @@ (UNSPEC_FRINTM "floor") (UNSPEC_FRINTI "nearbyint") (UNSPEC_FRINTX "rint") @@ -21981,7 +25028,7 @@ (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") -@@ -800,3 +877,5 @@ +@@ -800,3 +878,5 @@ (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) @@ -21989,7 +25036,23 @@ +(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) --- a/src/gcc/config/aarch64/aarch64.h +++ b/src/gcc/config/aarch64/aarch64.h -@@ -521,12 +521,6 @@ +@@ -151,6 +151,7 @@ + #define AARCH64_FL_FP (1 << 1) /* Has FP. */ + #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ + #define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ ++#define AARCH64_FL_CRC (1 << 4) /* Has CRC. */ + + /* Has FP and SIMD. */ + #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) +@@ -163,6 +164,7 @@ + + /* Macros to test ISA flags. */ + extern unsigned long aarch64_isa_flags; ++#define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) + #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) + #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) + #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) +@@ -521,12 +523,6 @@ #endif @@ -22002,7 +25065,7 @@ enum arm_pcs { ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ -@@ -534,11 +528,7 @@ +@@ -534,11 +530,7 @@ }; @@ -22014,7 +25077,7 @@ #ifndef ARM_DEFAULT_PCS #define ARM_DEFAULT_PCS ARM_PCS_AAPCS64 -@@ -709,6 +699,8 @@ +@@ -709,6 +701,8 @@ #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) @@ -22023,6 +25086,32 @@ #define REVERSE_CONDITION(CODE, MODE) \ (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ ? reverse_condition_maybe_unordered (CODE) \ +@@ -758,9 +752,23 @@ + #define PRINT_OPERAND_ADDRESS(STREAM, X) \ + aarch64_print_operand_address (STREAM, X) + +-#define FUNCTION_PROFILER(STREAM, LABELNO) \ +- aarch64_function_profiler (STREAM, LABELNO) ++#define MCOUNT_NAME "_mcount" + ++#define NO_PROFILE_COUNTERS 1 ++ ++/* Emit rtl for profiling. Output assembler code to FILE ++ to call "_mcount" for profiling a function entry. */ ++#define PROFILE_HOOK(LABEL) \ ++{ \ ++ rtx fun,lr; \ ++ lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ ++ fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ ++ emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ ++} ++ ++/* All the work done in PROFILE_HOOK, but still required. */ ++#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) ++ + /* For some reason, the Linux headers think they know how to define + these macros. They don't!!! */ + #undef ASM_APP_ON --- a/src/gcc/config/arm/arm1020e.md +++ b/src/gcc/config/arm/arm1020e.md @@ -66,13 +66,14 @@ @@ -22274,6 +25363,20 @@ "a_e*5,a_m,a_w") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/linux-elf.h ++++ b/src/gcc/config/arm/linux-elf.h +@@ -44,9 +44,9 @@ + + #define SUBTARGET_EXTRA_LINK_SPEC " -m " TARGET_LINKER_EMULATION " -p" + ++/* We do not have any MULTILIB_OPTIONS specified, so there are no ++ MULTILIB_DEFAULTS. */ + #undef MULTILIB_DEFAULTS +-#define MULTILIB_DEFAULTS \ +- { "marm", "mlittle-endian", "mfloat-abi=hard", "mno-thumb-interwork" } + + /* Now we define the strings used to build the spec file. */ + #undef LIB_SPEC --- a/src/gcc/config/arm/arm1136jfs.md +++ b/src/gcc/config/arm/arm1136jfs.md @@ -75,13 +75,14 @@ @@ -22776,7 +25879,29 @@ ) (define_insn "tls_load_dot_plus_four" -@@ -233,57 +361,170 @@ +@@ -223,6 +351,21 @@ + (set_attr "neg_pool_range" "*,*,*,250")] + ) + ++(define_insn "*thumb2_storewb_pairsi" ++ [(set (match_operand:SI 0 "register_operand" "=&kr") ++ (plus:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "const_int_operand" "n"))) ++ (set (mem:SI (plus:SI (match_dup 0) (match_dup 2))) ++ (match_operand:SI 3 "register_operand" "r")) ++ (set (mem:SI (plus:SI (match_dup 0) ++ (match_operand:SI 5 "const_int_operand" "n"))) ++ (match_operand:SI 4 "register_operand" "r"))] ++ "TARGET_THUMB2 ++ && INTVAL (operands[5]) == INTVAL (operands[2]) + 4" ++ "strd\\t%3, %4, [%0, %2]!" ++ [(set_attr "type" "store2")] ++) ++ + (define_insn "*thumb2_cmpsi_neg_shiftsi" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 0 "s_register_operand" "r") +@@ -233,57 +376,170 @@ "cmn%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") @@ -22965,7 +26090,7 @@ (set_attr "conds" "use")] ) -@@ -333,28 +574,74 @@ +@@ -333,28 +589,74 @@ ;; addresses will have the thumb bit set correctly. @@ -23052,7 +26177,7 @@ ) (define_insn "*thumb2_cond_move" -@@ -384,13 +671,20 @@ +@@ -384,13 +686,20 @@ output_asm_insn (\"it\\t%D4\", operands); break; case 2: @@ -23075,7 +26200,7 @@ if (which_alternative != 1) output_asm_insn (\"mov%d4\\t%0, %2\", operands); return \"\"; -@@ -407,7 +701,7 @@ +@@ -407,7 +716,7 @@ (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) (clobber (reg:CC CC_REGNUM))] @@ -23084,7 +26209,7 @@ "* if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) return \"%i5\\t%0, %1, %2, lsr #31\"; -@@ -436,9 +730,78 @@ +@@ -436,9 +745,78 @@ (set_attr "length" "14")] ) @@ -23165,7 +26290,7 @@ (match_operator:SI 4 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) -@@ -448,8 +811,16 @@ +@@ -448,8 +826,16 @@ output_asm_insn (\"cmp\\t%2, %3\", operands); if (which_alternative != 0) { @@ -23184,7 +26309,7 @@ } else output_asm_insn (\"it\\t%d4\", operands); -@@ -459,37 +830,82 @@ +@@ -459,37 +845,82 @@ (set_attr "length" "10,14")] ) @@ -23282,7 +26407,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "* -@@ -544,12 +960,18 @@ +@@ -544,12 +975,18 @@ output_asm_insn (\"it\\t%d5\", operands); break; case 2: @@ -23303,7 +26428,7 @@ output_asm_insn (\"mov%d5\\t%0, %1\", operands); if (which_alternative != 1) output_asm_insn (\"mov%D5\\t%0, %2\", operands); -@@ -570,8 +992,9 @@ +@@ -570,8 +1007,9 @@ "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" @@ -23314,7 +26439,7 @@ (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) -@@ -583,8 +1006,9 @@ +@@ -583,8 +1021,9 @@ "@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" @@ -23325,7 +26450,7 @@ (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) -@@ -596,8 +1020,9 @@ +@@ -596,8 +1035,9 @@ "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" @@ -23336,7 +26461,7 @@ (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) -@@ -688,8 +1113,8 @@ +@@ -688,8 +1128,8 @@ (set_attr "shift" "1") (set_attr "length" "2") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -23347,7 +26472,7 @@ ) (define_insn "*thumb2_mov_shortim" -@@ -811,7 +1236,7 @@ +@@ -811,7 +1251,7 @@ " [(set_attr "conds" "set") (set_attr "length" "2,2,4,4") @@ -23356,7 +26481,7 @@ ) (define_insn "*thumb2_mulsi_short" -@@ -823,7 +1248,7 @@ +@@ -823,7 +1263,7 @@ "mul%!\\t%0, %2, %0" [(set_attr "predicable" "yes") (set_attr "length" "2") @@ -23365,7 +26490,7 @@ (define_insn "*thumb2_mulsi_short_compare0" [(set (reg:CC_NOOV CC_REGNUM) -@@ -836,7 +1261,7 @@ +@@ -836,7 +1276,7 @@ "TARGET_THUMB2 && optimize_size" "muls\\t%0, %2, %0" [(set_attr "length" "2") @@ -23374,7 +26499,7 @@ (define_insn "*thumb2_mulsi_short_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) -@@ -848,7 +1273,7 @@ +@@ -848,7 +1288,7 @@ "TARGET_THUMB2 && optimize_size" "muls\\t%0, %2, %0" [(set_attr "length" "2") @@ -23383,7 +26508,7 @@ (define_insn "*thumb2_cbz" [(set (pc) (if_then_else -@@ -922,7 +1347,8 @@ +@@ -922,7 +1362,8 @@ (match_operand:SI 1 "s_register_operand" "r")))] "TARGET_THUMB2" "orn%?\\t%0, %1, %2" @@ -23393,7 +26518,7 @@ ) (define_insn "*orsi_not_shiftsi_si" -@@ -934,8 +1360,9 @@ +@@ -934,8 +1375,9 @@ "TARGET_THUMB2" "orn%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") @@ -24196,10 +27321,179 @@ switch (GET_CODE (XEXP (operands[0], 0))) { -@@ -16409,6 +16913,148 @@ - return; +@@ -16289,124 +16793,308 @@ + } } +-/* Generate and emit a pattern that will be recognized as STRD pattern. If even +- number of registers are being pushed, multiple STRD patterns are created for +- all register pairs. If odd number of registers are pushed, emit a +- combination of STRDs and STR for the prologue saves. */ ++/* Generate and emit a sequence of insns equivalent to PUSH, but using ++ STR and STRD. If an even number of registers are being pushed, one ++ or more STRD patterns are created for each register pair. If an ++ odd number of registers are pushed, emit an initial STR followed by ++ as many STRD instructions as are needed. This works best when the ++ stack is initially 64-bit aligned (the normal case), since it ++ ensures that each STRD is also 64-bit aligned. */ + static void + thumb2_emit_strd_push (unsigned long saved_regs_mask) + { + int num_regs = 0; +- int i, j; ++ int i; ++ int regno; + rtx par = NULL_RTX; +- rtx insn = NULL_RTX; + rtx dwarf = NULL_RTX; +- rtx tmp, reg, tmp1; ++ rtx tmp; ++ bool first = true; + ++ num_regs = bit_count (saved_regs_mask); ++ ++ /* Must be at least one register to save, and can't save SP or PC. */ ++ gcc_assert (num_regs > 0 && num_regs <= 14); ++ gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); ++ gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); ++ ++ /* Create sequence for DWARF info. All the frame-related data for ++ debugging is held in this wrapper. */ ++ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1)); ++ ++ /* Describe the stack adjustment. */ ++ tmp = gen_rtx_SET (VOIDmode, ++ stack_pointer_rtx, ++ plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, 0) = tmp; ++ ++ /* Find the first register. */ ++ for (regno = 0; (saved_regs_mask & (1 << regno)) == 0; regno++) ++ ; ++ ++ i = 0; ++ ++ /* If there's an odd number of registers to push. Start off by ++ pushing a single register. This ensures that subsequent strd ++ operations are dword aligned (assuming that SP was originally ++ 64-bit aligned). */ ++ if ((num_regs & 1) != 0) ++ { ++ rtx reg, mem, insn; ++ ++ reg = gen_rtx_REG (SImode, regno); ++ if (num_regs == 1) ++ mem = gen_frame_mem (Pmode, gen_rtx_PRE_DEC (Pmode, ++ stack_pointer_rtx)); ++ else ++ mem = gen_frame_mem (Pmode, ++ gen_rtx_PRE_MODIFY ++ (Pmode, stack_pointer_rtx, ++ plus_constant (Pmode, stack_pointer_rtx, ++ -4 * num_regs))); ++ ++ tmp = gen_rtx_SET (VOIDmode, mem, reg); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ insn = emit_insn (tmp); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); ++ tmp = gen_rtx_SET (VOIDmode, gen_frame_mem (Pmode, stack_pointer_rtx), ++ reg); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ i++; ++ regno++; ++ XVECEXP (dwarf, 0, i) = tmp; ++ first = false; ++ } ++ ++ while (i < num_regs) ++ if (saved_regs_mask & (1 << regno)) ++ { ++ rtx reg1, reg2, mem1, mem2; ++ rtx tmp0, tmp1, tmp2; ++ int regno2; ++ ++ /* Find the register to pair with this one. */ ++ for (regno2 = regno + 1; (saved_regs_mask & (1 << regno2)) == 0; ++ regno2++) ++ ; ++ ++ reg1 = gen_rtx_REG (SImode, regno); ++ reg2 = gen_rtx_REG (SImode, regno2); ++ ++ if (first) ++ { ++ rtx insn; ++ ++ first = false; ++ mem1 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ -4 * num_regs)); ++ mem2 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ -4 * (num_regs - 1))); ++ tmp0 = gen_rtx_SET (VOIDmode, stack_pointer_rtx, ++ plus_constant (Pmode, stack_pointer_rtx, ++ -4 * (num_regs))); ++ tmp1 = gen_rtx_SET (VOIDmode, mem1, reg1); ++ tmp2 = gen_rtx_SET (VOIDmode, mem2, reg2); ++ RTX_FRAME_RELATED_P (tmp0) = 1; ++ RTX_FRAME_RELATED_P (tmp1) = 1; ++ RTX_FRAME_RELATED_P (tmp2) = 1; ++ par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); ++ XVECEXP (par, 0, 0) = tmp0; ++ XVECEXP (par, 0, 1) = tmp1; ++ XVECEXP (par, 0, 2) = tmp2; ++ insn = emit_insn (par); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); ++ } ++ else ++ { ++ mem1 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * i)); ++ mem2 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * (i + 1))); ++ tmp1 = gen_rtx_SET (VOIDmode, mem1, reg1); ++ tmp2 = gen_rtx_SET (VOIDmode, mem2, reg2); ++ RTX_FRAME_RELATED_P (tmp1) = 1; ++ RTX_FRAME_RELATED_P (tmp2) = 1; ++ par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); ++ XVECEXP (par, 0, 0) = tmp1; ++ XVECEXP (par, 0, 1) = tmp2; ++ emit_insn (par); ++ } ++ ++ /* Create unwind information. This is an approximation. */ ++ tmp1 = gen_rtx_SET (VOIDmode, ++ gen_frame_mem (Pmode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * i)), ++ reg1); ++ tmp2 = gen_rtx_SET (VOIDmode, ++ gen_frame_mem (Pmode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * (i + 1))), ++ reg2); ++ ++ RTX_FRAME_RELATED_P (tmp1) = 1; ++ RTX_FRAME_RELATED_P (tmp2) = 1; ++ XVECEXP (dwarf, 0, i + 1) = tmp1; ++ XVECEXP (dwarf, 0, i + 2) = tmp2; ++ i += 2; ++ regno = regno2 + 1; ++ } ++ else ++ regno++; ++ ++ return; ++} ++ +/* STRD in ARM mode requires consecutive registers. This function emits STRD + whenever possible, otherwise it emits single-word stores. The first store + also allocates stack space for all saved registers, using writeback with @@ -24220,30 +27514,62 @@ + /* TODO: A more efficient code can be emitted by changing the + layout, e.g., first push all pairs that can use STRD to keep the + stack aligned, and then push all other registers. */ -+ for (i = 0; i <= LAST_ARM_REGNUM; i++) -+ if (saved_regs_mask & (1 << i)) -+ num_regs++; -+ + for (i = 0; i <= LAST_ARM_REGNUM; i++) + if (saved_regs_mask & (1 << i)) + num_regs++; + +- gcc_assert (num_regs && num_regs <= 16); + gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); + gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); + gcc_assert (num_regs > 0); -+ -+ /* Create sequence for DWARF info. */ -+ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1)); -+ + +- /* Pre-decrement the stack pointer, based on there being num_regs 4-byte +- registers to push. */ +- tmp = gen_rtx_SET (VOIDmode, +- stack_pointer_rtx, +- plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); +- RTX_FRAME_RELATED_P (tmp) = 1; +- insn = emit_insn (tmp); +- + /* Create sequence for DWARF info. */ + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1)); + +- /* RTLs cannot be shared, hence create new copy for dwarf. */ +- tmp1 = gen_rtx_SET (VOIDmode, + /* For dwarf info, we generate explicit stack update. */ + tmp = gen_rtx_SET (VOIDmode, -+ stack_pointer_rtx, -+ plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); + stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); +- RTX_FRAME_RELATED_P (tmp1) = 1; +- XVECEXP (dwarf, 0, 0) = tmp1; + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ + +- gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); +- gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); +- +- /* Var j iterates over all the registers to gather all the registers in +- saved_regs_mask. Var i gives index of register R_j in stack frame. +- A PARALLEL RTX of register-pair is created here, so that pattern for +- STRD can be matched. If num_regs is odd, 1st register will be pushed +- using STR and remaining registers will be pushed with STRD in pairs. +- If num_regs is even, all registers are pushed with STRD in pairs. +- Hence, skip first element for odd num_regs. */ +- for (i = num_regs - 1, j = LAST_ARM_REGNUM; i >= (num_regs % 2); j--) + /* Save registers. */ + offset = - 4 * num_regs; + j = 0; + while (j <= LAST_ARM_REGNUM) -+ if (saved_regs_mask & (1 << j)) -+ { + if (saved_regs_mask & (1 << j)) + { +- /* Create RTX for store. New RTX is created for dwarf as +- they are not sharable. */ +- reg = gen_rtx_REG (SImode, j); +- tmp = gen_rtx_SET (SImode, +- gen_frame_mem +- (SImode, +- plus_constant (Pmode, stack_pointer_rtx, 4 * i)), +- reg); + if ((j % 2 == 0) + && (saved_regs_mask & (1 << (j + 1)))) + { @@ -24264,15 +27590,35 @@ + offset)); + else + mem = gen_frame_mem (DImode, stack_pointer_rtx); -+ + +- tmp1 = gen_rtx_SET (SImode, +- gen_frame_mem +- (SImode, +- plus_constant (Pmode, stack_pointer_rtx, 4 * i)), +- reg); +- RTX_FRAME_RELATED_P (tmp) = 1; +- RTX_FRAME_RELATED_P (tmp1) = 1; + tmp = gen_rtx_SET (DImode, mem, gen_rtx_REG (DImode, j)); + RTX_FRAME_RELATED_P (tmp) = 1; + tmp = emit_insn (tmp); -+ + +- if (((i - (num_regs % 2)) % 2) == 1) +- /* When (i - (num_regs % 2)) is odd, the RTX to be emitted is yet to +- be created. Hence create it first. The STRD pattern we are +- generating is : +- [ (SET (MEM (PLUS (SP) (NUM))) (reg_t1)) +- (SET (MEM (PLUS (SP) (NUM + 4))) (reg_t2)) ] +- where the target registers need not be consecutive. */ +- par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); + /* Record the first store insn. */ + if (dwarf_index == 1) + insn = tmp; -+ + +- /* Register R_j is added in PARALLEL RTX. If (i - (num_regs % 2)) is +- even, the reg_j is added as 0th element and if it is odd, reg_i is +- added as 1st element of STRD pattern shown above. */ +- XVECEXP (par, 0, ((i - (num_regs % 2)) % 2)) = tmp; +- XVECEXP (dwarf, 0, (i + 1)) = tmp1; + /* Generate dwarf info. */ + mem = gen_frame_mem (SImode, + plus_constant (Pmode, @@ -24281,7 +27627,12 @@ + tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ + +- if (((i - (num_regs % 2)) % 2) == 0) +- /* When (i - (num_regs % 2)) is even, RTXs for both the registers +- to be loaded are generated in above given STRD pattern, and the +- pattern can be emitted now. */ +- emit_insn (par); + mem = gen_frame_mem (SImode, + plus_constant (Pmode, + stack_pointer_rtx, @@ -24289,7 +27640,9 @@ + tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j + 1)); + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ + +- i--; +- } + offset += 8; + j += 2; + } @@ -24311,15 +27664,26 @@ + offset)); + else + mem = gen_frame_mem (SImode, stack_pointer_rtx); -+ + +- if ((num_regs % 2) == 1) +- { +- /* If odd number of registers are pushed, generate STR pattern to store +- lone register. */ +- for (; (saved_regs_mask & (1 << j)) == 0; j--); + tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); + RTX_FRAME_RELATED_P (tmp) = 1; + tmp = emit_insn (tmp); -+ + +- tmp1 = gen_frame_mem (SImode, plus_constant (Pmode, +- stack_pointer_rtx, 4 * i)); +- reg = gen_rtx_REG (SImode, j); +- tmp = gen_rtx_SET (SImode, tmp1, reg); +- RTX_FRAME_RELATED_P (tmp) = 1; + /* Record the first store insn. */ + if (dwarf_index == 1) + insn = tmp; -+ + +- emit_insn (tmp); + /* Generate dwarf info. */ + mem = gen_frame_mem (SImode, + plus_constant(Pmode, @@ -24328,24 +27692,31 @@ + tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ + +- tmp1 = gen_rtx_SET (SImode, +- gen_frame_mem +- (SImode, +- plus_constant (Pmode, stack_pointer_rtx, 4 * i)), +- reg); +- RTX_FRAME_RELATED_P (tmp1) = 1; +- XVECEXP (dwarf, 0, (i + 1)) = tmp1; +- } + offset += 4; + j += 1; + } + } + else + j++; -+ + + /* Attach dwarf info to the first insn we generate. */ + gcc_assert (insn != NULL_RTX); -+ add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); -+ RTX_FRAME_RELATED_P (insn) = 1; -+} -+ + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); + RTX_FRAME_RELATED_P (insn) = 1; +- return; + } + /* Generate and emit an insn that we will recognize as a push_multi. - Unfortunately, since this insn does not reflect very well the actual - semantics of the operation, we need to annotate the insn for the benefit -@@ -16551,6 +17197,19 @@ +@@ -16551,6 +17239,19 @@ return par; } @@ -24365,7 +27736,7 @@ /* Generate and emit an insn pattern that we will recognize as a pop_multi. SAVED_REGS_MASK shows which registers need to be restored. -@@ -16608,6 +17267,17 @@ +@@ -16608,6 +17309,17 @@ if (saved_regs_mask & (1 << i)) { reg = gen_rtx_REG (SImode, i); @@ -24383,7 +27754,7 @@ tmp = gen_rtx_SET (VOIDmode, reg, gen_frame_mem -@@ -16630,6 +17300,9 @@ +@@ -16630,6 +17342,9 @@ par = emit_insn (par); REG_NOTES (par) = dwarf; @@ -24393,7 +27764,7 @@ } /* Generate and emit an insn pattern that we will recognize as a pop_multi -@@ -16700,6 +17373,9 @@ +@@ -16700,6 +17415,9 @@ par = emit_insn (par); REG_NOTES (par) = dwarf; @@ -24403,7 +27774,7 @@ } /* Generate and emit a pattern that will be recognized as LDRD pattern. If even -@@ -16775,6 +17451,7 @@ +@@ -16775,6 +17493,7 @@ pattern can be emitted now. */ par = emit_insn (par); REG_NOTES (par) = dwarf; @@ -24411,7 +27782,7 @@ } i++; -@@ -16791,7 +17468,12 @@ +@@ -16791,7 +17510,12 @@ stack_pointer_rtx, plus_constant (Pmode, stack_pointer_rtx, 4 * i)); RTX_FRAME_RELATED_P (tmp) = 1; @@ -24425,7 +27796,7 @@ dwarf = NULL_RTX; -@@ -16825,9 +17507,11 @@ +@@ -16825,9 +17549,11 @@ else { par = emit_insn (tmp); @@ -24438,7 +27809,7 @@ } else if ((num_regs % 2) == 1 && return_in_pc) { -@@ -16839,6 +17523,129 @@ +@@ -16839,6 +17565,132 @@ return; } @@ -24484,8 +27855,8 @@ + mem = gen_frame_mem (DImode, stack_pointer_rtx); + + tmp = gen_rtx_SET (DImode, gen_rtx_REG (DImode, j), mem); -+ RTX_FRAME_RELATED_P (tmp) = 1; + tmp = emit_insn (tmp); ++ RTX_FRAME_RELATED_P (tmp) = 1; + + /* Generate dwarf info. */ + @@ -24513,8 +27884,8 @@ + mem = gen_frame_mem (SImode, stack_pointer_rtx); + + tmp = gen_rtx_SET (SImode, gen_rtx_REG (SImode, j), mem); -+ RTX_FRAME_RELATED_P (tmp) = 1; + tmp = emit_insn (tmp); ++ RTX_FRAME_RELATED_P (tmp) = 1; + + /* Generate dwarf info. */ + REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, @@ -24538,8 +27909,9 @@ + plus_constant (Pmode, + stack_pointer_rtx, + offset)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ emit_insn (tmp); ++ tmp = emit_insn (tmp); ++ arm_add_cfa_adjust_cfa_note (tmp, offset, ++ stack_pointer_rtx, stack_pointer_rtx); + offset = 0; + } + @@ -24562,13 +27934,15 @@ + gen_rtx_REG (SImode, PC_REGNUM), + NULL_RTX); + REG_NOTES (par) = dwarf; ++ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD, ++ stack_pointer_rtx, stack_pointer_rtx); + } +} + /* Calculate the size of the return value that is passed in registers. */ static unsigned arm_size_return_regs (void) -@@ -16863,11 +17670,27 @@ +@@ -16863,11 +17715,27 @@ || df_regs_ever_live_p (LR_REGNUM)); } @@ -24597,7 +27971,7 @@ { edge_iterator ei; edge e; -@@ -16881,7 +17704,8 @@ +@@ -16881,7 +17749,8 @@ if (!CALL_P (call)) call = prev_nonnote_nondebug_insn (call); gcc_assert (CALL_P (call) && SIBLING_CALL_P (call)); @@ -24607,7 +27981,7 @@ return true; } return false; -@@ -17048,9 +17872,10 @@ +@@ -17048,9 +17917,11 @@ /* If it is safe to use r3, then do so. This sometimes generates better code on Thumb-2 by avoiding the need to use 32-bit push/pop instructions. */ @@ -24616,11 +27990,12 @@ && arm_size_return_regs () <= 12 - && (offsets->saved_regs_mask & (1 << 3)) == 0) + && (offsets->saved_regs_mask & (1 << 3)) == 0 -+ && (TARGET_THUMB2 || !current_tune->prefer_ldrd_strd)) ++ && (TARGET_THUMB2 ++ || !(TARGET_LDRD && current_tune->prefer_ldrd_strd))) { reg = 3; } -@@ -17482,6 +18307,12 @@ +@@ -17483,6 +18354,12 @@ { thumb2_emit_strd_push (live_regs_mask); } @@ -24633,7 +28008,7 @@ else { insn = emit_multi_reg_push (live_regs_mask); -@@ -18759,7 +19590,14 @@ +@@ -18760,7 +19637,14 @@ enum arm_cond_code code; int n; int mask; @@ -24648,7 +28023,7 @@ /* Remove the previous insn from the count of insns to be output. */ if (arm_condexec_count) arm_condexec_count--; -@@ -18801,9 +19639,9 @@ +@@ -18802,9 +19686,9 @@ /* ??? Recognize conditional jumps, and combine them with IT blocks. */ if (GET_CODE (body) != COND_EXEC) break; @@ -24660,7 +28035,7 @@ break; predicate = COND_EXEC_TEST (body); -@@ -19361,6 +20199,7 @@ +@@ -19362,6 +20246,7 @@ typedef enum { T_V8QI, T_V4HI, @@ -24668,7 +28043,7 @@ T_V2SI, T_V2SF, T_DI, -@@ -19378,14 +20217,15 @@ +@@ -19379,14 +20264,15 @@ #define TYPE_MODE_BIT(X) (1 << (X)) #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \ @@ -24686,7 +28061,7 @@ #define v2si_UP T_V2SI #define v2sf_UP T_V2SF #define di_UP T_DI -@@ -19421,6 +20261,8 @@ +@@ -19422,6 +20308,8 @@ NEON_SCALARMULH, NEON_SCALARMAC, NEON_CONVERT, @@ -24695,7 +28070,7 @@ NEON_FIXCONV, NEON_SELECT, NEON_RESULTPAIR, -@@ -19481,7 +20323,8 @@ +@@ -19482,7 +20370,8 @@ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ {#N, NEON_##T, UP (J), CF (N, J), 0} @@ -24705,7 +28080,7 @@ instruction variant, i.e. equivalent to that which would be specified after the assembler mnemonic, which usually refers to the last vector operand. (Signed/unsigned/polynomial types are not differentiated between though, and -@@ -19491,196 +20334,7 @@ +@@ -19492,196 +20381,7 @@ static neon_builtin_datum neon_builtin_data[] = { @@ -24903,7 +28278,7 @@ }; #undef CF -@@ -19695,9 +20349,36 @@ +@@ -19696,9 +20396,36 @@ #undef VAR9 #undef VAR10 @@ -24943,7 +28318,7 @@ enum arm_builtins { ARM_BUILTIN_GETWCGR0, -@@ -19946,11 +20627,25 @@ +@@ -19947,11 +20674,25 @@ ARM_BUILTIN_WMERGE, @@ -24971,7 +28346,7 @@ static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX]; static void -@@ -19961,6 +20656,7 @@ +@@ -19962,6 +20703,7 @@ tree neon_intQI_type_node; tree neon_intHI_type_node; @@ -24979,7 +28354,7 @@ tree neon_polyQI_type_node; tree neon_polyHI_type_node; tree neon_intSI_type_node; -@@ -19987,6 +20683,7 @@ +@@ -19988,6 +20730,7 @@ tree V8QI_type_node; tree V4HI_type_node; @@ -24987,7 +28362,7 @@ tree V2SI_type_node; tree V2SF_type_node; tree V16QI_type_node; -@@ -20041,6 +20738,9 @@ +@@ -20042,6 +20785,9 @@ neon_float_type_node = make_node (REAL_TYPE); TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; layout_type (neon_float_type_node); @@ -24997,7 +28372,7 @@ /* Define typedefs which exactly correspond to the modes we are basing vector types on. If you change these names you'll need to change -@@ -20049,6 +20749,8 @@ +@@ -20050,6 +20796,8 @@ "__builtin_neon_qi"); (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, "__builtin_neon_hi"); @@ -25006,7 +28381,7 @@ (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, "__builtin_neon_si"); (*lang_hooks.types.register_builtin_type) (neon_float_type_node, -@@ -20090,6 +20792,8 @@ +@@ -20091,6 +20839,8 @@ build_vector_type_for_mode (neon_intQI_type_node, V8QImode); V4HI_type_node = build_vector_type_for_mode (neon_intHI_type_node, V4HImode); @@ -25015,7 +28390,7 @@ V2SI_type_node = build_vector_type_for_mode (neon_intSI_type_node, V2SImode); V2SF_type_node = -@@ -20212,7 +20916,7 @@ +@@ -20213,7 +20963,7 @@ neon_builtin_datum *d = &neon_builtin_data[i]; const char* const modenames[] = { @@ -25024,7 +28399,7 @@ "v16qi", "v8hi", "v4si", "v4sf", "v2di", "ti", "ei", "oi" }; -@@ -20415,8 +21119,9 @@ +@@ -20416,8 +21166,9 @@ case NEON_REINTERP: { /* We iterate over 5 doubleword types, then 5 quadword @@ -25036,7 +28411,7 @@ switch (insn_data[d->code].operand[0].mode) { case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; -@@ -20433,7 +21138,38 @@ +@@ -20434,7 +21185,38 @@ } } break; @@ -25075,7 +28450,7 @@ default: gcc_unreachable (); } -@@ -21430,6 +22166,8 @@ +@@ -21431,6 +22213,8 @@ case NEON_DUP: case NEON_RINT: case NEON_SPLIT: @@ -25084,7 +28459,7 @@ case NEON_REINTERP: return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); -@@ -21627,7 +22365,7 @@ +@@ -21628,7 +22412,7 @@ rtx op1; rtx op2; rtx pat; @@ -25093,7 +28468,7 @@ size_t i; enum machine_mode tmode; enum machine_mode mode0; -@@ -23344,7 +24082,7 @@ +@@ -23345,7 +24129,7 @@ all we really need to check here is if single register is to be returned, or multiple register return. */ void @@ -25102,7 +28477,7 @@ { int i, num_regs; unsigned long saved_regs_mask; -@@ -23357,7 +24095,7 @@ +@@ -23358,7 +24142,7 @@ if (saved_regs_mask & (1 << i)) num_regs++; @@ -25111,7 +28486,7 @@ { if (num_regs == 1) { -@@ -23635,6 +24373,7 @@ +@@ -23636,6 +24420,7 @@ if (frame_pointer_needed) { @@ -25119,7 +28494,7 @@ /* Restore stack pointer if necessary. */ if (TARGET_ARM) { -@@ -23645,9 +24384,12 @@ +@@ -23646,9 +24431,12 @@ /* Force out any pending memory operations that reference stacked data before stack de-allocation occurs. */ emit_insn (gen_blockage ()); @@ -25135,7 +28510,7 @@ /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not deleted. */ -@@ -23657,16 +24399,25 @@ +@@ -23658,16 +24446,25 @@ { /* In Thumb-2 mode, the frame pointer points to the last saved register. */ @@ -25167,7 +28542,7 @@ /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not deleted. */ emit_insn (gen_force_register_use (stack_pointer_rtx)); -@@ -23679,12 +24430,15 @@ +@@ -23680,12 +24477,15 @@ amount = offsets->outgoing_args - offsets->saved_regs; if (amount) { @@ -25186,7 +28561,7 @@ /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not deleted. */ emit_insn (gen_force_register_use (stack_pointer_rtx)); -@@ -23737,6 +24491,8 @@ +@@ -23738,6 +24538,8 @@ REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (V2SImode, i), NULL_RTX); @@ -25195,7 +28570,7 @@ } if (saved_regs_mask) -@@ -23784,6 +24540,9 @@ +@@ -23785,6 +24587,9 @@ REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (SImode, i), NULL_RTX); @@ -25205,7 +28580,7 @@ } } } -@@ -23794,6 +24553,8 @@ +@@ -23796,6 +24601,8 @@ { if (TARGET_THUMB2) thumb2_emit_ldrd_pop (saved_regs_mask); @@ -25214,7 +28589,7 @@ else arm_emit_multi_reg_pop (saved_regs_mask); } -@@ -23806,10 +24567,34 @@ +@@ -23808,10 +24615,34 @@ } if (crtl->args.pretend_args_size) @@ -25252,7 +28627,7 @@ if (!really_return) return; -@@ -25062,7 +25847,7 @@ +@@ -25064,7 +25895,7 @@ { /* Neon also supports V2SImode, etc. listed in the clause below. */ if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode @@ -25261,7 +28636,7 @@ return true; if ((TARGET_NEON || TARGET_IWMMXT) -@@ -25225,9 +26010,8 @@ +@@ -25227,9 +26058,8 @@ nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); @@ -25272,7 +28647,7 @@ return p; } -@@ -25477,9 +26261,17 @@ +@@ -25479,9 +26309,17 @@ handled_one = true; break; @@ -25291,7 +28666,7 @@ case REG_CFA_OFFSET: /* ??? Only handling here what we actually emit. */ gcc_unreachable (); -@@ -25877,6 +26669,7 @@ +@@ -25879,6 +26717,7 @@ case cortexa7: case cortexa8: case cortexa9: @@ -25299,7 +28674,7 @@ case fa726te: case marvell_pj4: return 2; -@@ -25905,6 +26698,7 @@ +@@ -25907,6 +26746,7 @@ { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, @@ -25307,7 +28682,7 @@ { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, -@@ -26003,6 +26797,60 @@ +@@ -26005,6 +26845,60 @@ return !TARGET_THUMB1; } @@ -25368,7 +28743,7 @@ /* The AAPCS sets the maximum alignment of a vector to 64 bits. */ static HOST_WIDE_INT arm_vector_alignment (const_tree type) -@@ -26233,40 +27081,72 @@ +@@ -26235,40 +27129,72 @@ emit_insn (gen_memory_barrier ()); } @@ -25458,7 +28833,7 @@ emit_insn (gen (bval, rval, mem)); } -@@ -26301,6 +27181,15 @@ +@@ -26303,6 +27229,15 @@ mod_f = operands[7]; mode = GET_MODE (mem); @@ -25474,7 +28849,7 @@ switch (mode) { case QImode: -@@ -26375,8 +27264,20 @@ +@@ -26377,8 +27312,20 @@ scratch = operands[7]; mode = GET_MODE (mem); @@ -25496,7 +28871,7 @@ label1 = NULL_RTX; if (!is_weak) { -@@ -26385,7 +27286,7 @@ +@@ -26387,7 +27334,7 @@ } label2 = gen_label_rtx (); @@ -25505,7 +28880,7 @@ cond = arm_gen_compare_reg (NE, rval, oldval, scratch); x = gen_rtx_NE (VOIDmode, cond, const0_rtx); -@@ -26393,7 +27294,7 @@ +@@ -26395,7 +27342,7 @@ gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); @@ -25514,7 +28889,7 @@ /* Weak or strong, we want EQ to be true for success, so that we match the flags that we got from the compare above. */ -@@ -26412,7 +27313,9 @@ +@@ -26414,7 +27361,9 @@ if (mod_f != MEMMODEL_RELAXED) emit_label (label2); @@ -25525,7 +28900,7 @@ if (mod_f == MEMMODEL_RELAXED) emit_label (label2); -@@ -26427,8 +27330,20 @@ +@@ -26429,8 +27378,20 @@ enum machine_mode wmode = (mode == DImode ? DImode : SImode); rtx label, x; @@ -25547,7 +28922,7 @@ label = gen_label_rtx (); emit_label (label); -@@ -26440,7 +27355,7 @@ +@@ -26442,7 +27403,7 @@ old_out = new_out; value = simplify_gen_subreg (wmode, value, mode, 0); @@ -25556,7 +28931,7 @@ switch (code) { -@@ -26488,12 +27403,15 @@ +@@ -26490,12 +27451,15 @@ break; } @@ -25574,7 +28949,7 @@ } #define MAX_VECT_LEN 16 -@@ -27433,4 +28351,12 @@ +@@ -27435,4 +28399,12 @@ } @@ -25587,6 +28962,186 @@ +} + #include "gt-arm.h" +--- a/src/gcc/config/arm/t-aprofile ++++ b/src/gcc/config/arm/t-aprofile +@@ -0,0 +1,177 @@ ++# Copyright (C) 2012-2013 Free Software Foundation, Inc. ++# ++# This file is part of GCC. ++# ++# GCC is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3, or (at your option) ++# any later version. ++# ++# GCC is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# This is a target makefile fragment that attempts to get ++# multilibs built for the range of CPU's, FPU's and ABI's that ++# are relevant for the A-profile architecture. It should ++# not be used in conjunction with another make file fragment and ++# assumes --with-arch, --with-cpu, --with-fpu, --with-float, --with-mode ++# have their default values during the configure step. We enforce ++# this during the top-level configury. ++ ++MULTILIB_OPTIONS = ++MULTILIB_DIRNAMES = ++MULTILIB_EXCEPTIONS = ++MULTILIB_MATCHES = ++MULTILIB_REUSE = ++ ++# We have the following hierachy: ++# ISA: A32 (.) or T32 (thumb) ++# Architecture: ARMv7-A (v7-a), ARMv7VE (v7ve), or ARMv8-A (v8-a). ++# FPU: VFPv3-D16 (fpv3), NEONv1 (simdv1), VFPv4-D16 (fpv4), ++# NEON-VFPV4 (simdvfpv4), NEON for ARMv8 (simdv8), or None (.). ++# Float-abi: Soft (.), softfp (softfp), or hard (hardfp). ++ ++# We use the option -mcpu=cortex-a7 because we do not yet have march=armv7ve ++# or march=armv7a+virt as a command line option for the compiler. ++MULTILIB_OPTIONS += mthumb ++MULTILIB_DIRNAMES += thumb ++ ++MULTILIB_OPTIONS += march=armv7-a/mcpu=cortex-a7/march=armv8-a ++MULTILIB_DIRNAMES += v7-a v7ve v8-a ++ ++MULTILIB_OPTIONS += mfpu=vfpv3-d16/mfpu=neon/mfpu=vfpv4-d16/mfpu=neon-vfpv4/mfpu=neon-fp-armv8 ++MULTILIB_DIRNAMES += fpv3 simdv1 fpv4 simdvfpv4 simdv8 ++ ++MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard ++MULTILIB_DIRNAMES += softfp hard ++ ++# We don't build no-float libraries with an FPU. ++MULTILIB_EXCEPTIONS += *mfpu=vfpv3-d16 ++MULTILIB_EXCEPTIONS += *mfpu=neon ++MULTILIB_EXCEPTIONS += *mfpu=vfpv4-d16 ++MULTILIB_EXCEPTIONS += *mfpu=neon-vfpv4 ++MULTILIB_EXCEPTIONS += *mfpu=neon-fp-armv8 ++ ++# We don't build libraries requiring an FPU at the CPU/Arch/ISA level. ++MULTILIB_EXCEPTIONS += mfloat-abi=* ++MULTILIB_EXCEPTIONS += mfpu=* ++MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=* ++MULTILIB_EXCEPTIONS += mthumb/mfpu=* ++MULTILIB_EXCEPTIONS += *march=armv7-a/mfloat-abi=* ++MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/mfloat-abi=* ++MULTILIB_EXCEPTIONS += *march=armv8-a/mfloat-abi=* ++ ++# Ensure the correct FPU variants apply to the correct base architectures. ++MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=vfpv3-d16* ++MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=neon/* ++MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=vfpv3-d16* ++MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=neon/* ++MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=vfpv4-d16* ++MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=neon-vfpv4* ++MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=vfpv4-d16* ++MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=neon-vfpv4* ++MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=neon-fp-armv8* ++MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=neon-fp-armv8* ++ ++# CPU Matches ++MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8 ++MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9 ++MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5 ++MULTILIB_MATCHES += mcpu?cortex-a7=mcpu?cortex-a15 ++MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53 ++ ++# FPU matches ++MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 ++MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16 ++MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16-d16 ++MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?vfpv4 ++MULTILIB_MATCHES += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8 ++ ++ ++# Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a. ++# So if new CPUs are added above at the newer architecture levels, ++# do something to map them below here. ++# We take the approach of mapping down to v7-a regardless of what ++# the fp option is if the integer architecture brings things down. ++# This applies to any similar combination at the v7ve and v8-a arch ++# levels. ++ ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp ++ ++ ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=mcpu.cortex-a7/mfpu.neon/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.neon/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv8-a/mfpu.neon/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv8-a/mfpu.neon/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp ++ ++ ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.softfp ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp ++ ++ ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.softfp ++ ++ ++ ++# And again for mthumb. ++ ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp ++ ++ ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.neon/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.neon/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp ++ ++ ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp ++ ++ ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.hard ++MULTILIB_REUSE += mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.softfp --- a/src/gcc/config/arm/arm.h +++ b/src/gcc/config/arm/arm.h @@ -183,6 +183,11 @@ @@ -26039,16 +29594,7 @@ +) --- a/src/gcc/config/arm/unspecs.md +++ b/src/gcc/config/arm/unspecs.md -@@ -83,6 +83,8 @@ - ; FPSCR rounding mode and signal inexactness. - UNSPEC_VRINTA ; Represent a float to integral float rounding - ; towards nearest, ties away from zero. -+ UNSPEC_RRX ; Rotate Right with Extend shifts register right -+ ; by one place, with Carry flag shifted into bit[31]. - ]) - - (define_c_enum "unspec" [ -@@ -139,6 +141,10 @@ +@@ -139,6 +139,10 @@ VUNSPEC_ATOMIC_OP ; Represent an atomic operation. VUNSPEC_LL ; Represent a load-register-exclusive. VUNSPEC_SC ; Represent a store-register-exclusive. @@ -26094,6 +29640,15 @@ #define CC1PLUS_SPEC \ LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC) +@@ -95,7 +99,7 @@ + #undef LIB_SPEC + #define LIB_SPEC \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LIB_SPEC, \ +- GNU_USER_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC " " ANDROID_LIB_SPEC) + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ --- a/src/gcc/config/arm/arm-cores.def +++ b/src/gcc/config/arm/arm-cores.def @@ -129,9 +129,11 @@ @@ -26786,13 +30341,24 @@ (set_attr "type" "fcmpd")] ) -@@ -1263,6 +1285,7 @@ +@@ -1264,6 +1264,7 @@ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " "vrint%?.\\t%0, %1" [(set_attr "predicable" "") + (set_attr "predicable_short_it" "no") + (set_attr "conds" "") (set_attr "type" "f_rint")] ) +--- a/src/gcc/config/arm/t-linux-eabi ++++ b/src/gcc/config/arm/t-linux-eabi +@@ -18,6 +18,8 @@ + + # We do not build a Thumb multilib for Linux because the definition of + # CLEAR_INSN_CACHE in linux-gas.h does not work in Thumb mode. ++# If you set MULTILIB_OPTIONS to a non-empty value you should also set ++# MULTILIB_DEFAULTS in linux-elf.h. + MULTILIB_OPTIONS = + MULTILIB_DIRNAMES = --- a/src/gcc/config/arm/neon.md +++ b/src/gcc/config/arm/neon.md @@ -30763,10 +34329,10 @@ "@ add%?\\t%0, %0, %2 add%?\\t%0, %1, %2 -+ add%?\\t%0, %2 add%?\\t%0, %1, %2 + add%?\\t%0, %1, %2 + add%?\\t%0, %1, %2 ++ add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 @@ -30912,8 +34478,8 @@ + (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] "TARGET_32BIT" "@ -+ adc%?\\t%0, %1 adc%?\\t%0, %1, %2 ++ adc%?\\t%0, %1, %2 sbc%?\\t%0, %1, #%B2" - [(set_attr "conds" "use")] + [(set_attr "conds" "use") @@ -30934,8 +34500,8 @@ + (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))] "TARGET_32BIT" "@ -+ adc%?\\t%0, %1 adc%?\\t%0, %1, %2 ++ adc%?\\t%0, %1, %2 sbc%?\\t%0, %1, #%B2" - [(set_attr "conds" "use")] + [(set_attr "conds" "use") @@ -32448,36 +36014,7 @@ ;; Shift and rotation insns -@@ -3533,13 +4165,26 @@ - " - ) - --(define_insn "arm_ashldi3_1bit" -+(define_insn_and_split "arm_ashldi3_1bit" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") - (const_int 1))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" -- "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" -+ "#" ; "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (ashift:SI (match_dup 1) (const_int 1)) -+ (const_int 0))) -+ (set (match_dup 0) (ashift:SI (match_dup 1) (const_int 1)))]) -+ (set (match_dup 2) (plus:SI (plus:SI (match_dup 3) (match_dup 3)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] - ) -@@ -3566,6 +4211,7 @@ +@@ -3566,6 +4198,7 @@ "TARGET_THUMB1" "lsl\\t%0, %1, %2" [(set_attr "length" "2") @@ -32485,53 +36022,15 @@ (set_attr "conds" "set")]) (define_expand "ashrdi3" -@@ -3615,18 +4261,42 @@ - " - ) - --(define_insn "arm_ashrdi3_1bit" -+(define_insn_and_split "arm_ashrdi3_1bit" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") - (const_int 1))) - (clobber (reg:CC CC_REGNUM))] +@@ -3623,7 +4256,6 @@ "TARGET_32BIT" -- "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" -+ "#" ; "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (ashiftrt:SI (match_dup 3) (const_int 1)) -+ (const_int 0))) -+ (set (match_dup 2) (ashiftrt:SI (match_dup 3) (const_int 1)))]) -+ (set (match_dup 0) (unspec:SI [(match_dup 1) -+ (reg:CC_C CC_REGNUM)] -+ UNSPEC_RRX))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } + "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") - (set_attr "insn" "mov") (set_attr "length" "8")] ) -+(define_insn "*rrx" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "r") -+ (reg:CC_C CC_REGNUM)] -+ UNSPEC_RRX))] -+ "TARGET_32BIT" -+ "mov\\t%0, %1, rrx" -+ [(set_attr "conds" "use") -+ (set_attr "type" "mov_shift")] -+) -+ - (define_expand "ashrsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") -@@ -3646,6 +4316,7 @@ +@@ -3646,6 +4278,7 @@ "TARGET_THUMB1" "asr\\t%0, %1, %2" [(set_attr "length" "2") @@ -32539,39 +36038,15 @@ (set_attr "conds" "set")]) (define_expand "lshrdi3" -@@ -3695,15 +4366,28 @@ - " - ) - --(define_insn "arm_lshrdi3_1bit" -+(define_insn_and_split "arm_lshrdi3_1bit" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") - (const_int 1))) - (clobber (reg:CC CC_REGNUM))] +@@ -3703,7 +4336,6 @@ "TARGET_32BIT" -- "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" -+ "#" ; "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (lshiftrt:SI (match_dup 3) (const_int 1)) -+ (const_int 0))) -+ (set (match_dup 2) (lshiftrt:SI (match_dup 3) (const_int 1)))]) -+ (set (match_dup 0) (unspec:SI [(match_dup 1) -+ (reg:CC_C CC_REGNUM)] -+ UNSPEC_RRX))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } + "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") - (set_attr "insn" "mov") (set_attr "length" "8")] ) -@@ -3729,6 +4413,7 @@ +@@ -3729,6 +4361,7 @@ "TARGET_THUMB1" "lsr\\t%0, %1, %2" [(set_attr "length" "2") @@ -32579,7 +36054,7 @@ (set_attr "conds" "set")]) (define_expand "rotlsi3" -@@ -3774,51 +4459,67 @@ +@@ -3774,51 +4407,52 @@ (match_operand:SI 2 "register_operand" "l")))] "TARGET_THUMB1" "ror\\t%0, %0, %2" @@ -32609,21 +36084,6 @@ + (set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")] ) -+(define_insn "*shiftsi3_compare" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_operator:SI 3 "shift_operator" -+ [(match_operand:SI 1 "s_register_operand" "r,r") -+ (match_operand:SI 2 "arm_rhs_operand" "M,r")]) -+ (const_int 0))) -+ (set (match_operand:SI 0 "s_register_operand" "=r,r") -+ (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] -+ "TARGET_32BIT" -+ "* return arm_output_shift(operands, 1);" -+ [(set_attr "conds" "set") -+ (set_attr "shift" "1") -+ (set_attr "type" "arlo_shift,arlo_shift_reg")] -+) -+ (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" @@ -32664,7 +36124,7 @@ ) (define_insn "*not_shiftsi" -@@ -3829,10 +4530,10 @@ +@@ -3829,10 +4463,10 @@ "TARGET_32BIT" "mvn%?\\t%0, %1%S3" [(set_attr "predicable" "yes") @@ -32677,7 +36137,7 @@ (define_insn "*not_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) -@@ -3847,9 +4548,8 @@ +@@ -3847,9 +4481,8 @@ "mvn%.\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") @@ -32688,7 +36148,7 @@ (define_insn "*not_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) -@@ -3863,9 +4563,8 @@ +@@ -3863,9 +4496,8 @@ "mvn%.\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") @@ -32699,7 +36159,7 @@ ;; We don't really have extzv, but defining this using shifts helps ;; to reduce register pressure later on. -@@ -4042,6 +4741,7 @@ +@@ -4042,6 +4674,7 @@ [(set_attr "arch" "t2,any") (set_attr "length" "2,4") (set_attr "predicable" "yes") @@ -32707,7 +36167,7 @@ (set_attr "type" "load1")]) (define_insn "unaligned_loadhis" -@@ -4054,6 +4754,7 @@ +@@ -4054,6 +4687,7 @@ [(set_attr "arch" "t2,any") (set_attr "length" "2,4") (set_attr "predicable" "yes") @@ -32715,7 +36175,7 @@ (set_attr "type" "load_byte")]) (define_insn "unaligned_loadhiu" -@@ -4066,6 +4767,7 @@ +@@ -4066,6 +4700,7 @@ [(set_attr "arch" "t2,any") (set_attr "length" "2,4") (set_attr "predicable" "yes") @@ -32723,7 +36183,7 @@ (set_attr "type" "load_byte")]) (define_insn "unaligned_storesi" -@@ -4077,6 +4779,7 @@ +@@ -4077,6 +4712,7 @@ [(set_attr "arch" "t2,any") (set_attr "length" "2,4") (set_attr "predicable" "yes") @@ -32731,7 +36191,7 @@ (set_attr "type" "store1")]) (define_insn "unaligned_storehi" -@@ -4088,8 +4791,67 @@ +@@ -4088,8 +4724,67 @@ [(set_attr "arch" "t2,any") (set_attr "length" "2,4") (set_attr "predicable" "yes") @@ -32799,7 +36259,7 @@ (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") -@@ -4098,7 +4860,8 @@ +@@ -4098,7 +4793,8 @@ "arm_arch_thumb2" "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -32809,7 +36269,7 @@ ) (define_insn "extzv_t2" -@@ -4109,7 +4872,8 @@ +@@ -4109,7 +4805,8 @@ "arm_arch_thumb2" "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -32819,7 +36279,7 @@ ) -@@ -4121,7 +4885,8 @@ +@@ -4121,7 +4818,8 @@ "TARGET_IDIV" "sdiv%?\t%0, %1, %2" [(set_attr "predicable" "yes") @@ -32829,7 +36289,7 @@ ) (define_insn "udivsi3" -@@ -4131,7 +4896,8 @@ +@@ -4131,7 +4829,8 @@ "TARGET_IDIV" "udiv%?\t%0, %1, %2" [(set_attr "predicable" "yes") @@ -32839,7 +36299,7 @@ ) -@@ -4154,12 +4920,24 @@ +@@ -4154,12 +4853,24 @@ ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). ;; The first alternative allows the common case of a *full* overlap. @@ -32866,7 +36326,7 @@ [(set_attr "conds" "clob") (set_attr "length" "8")] ) -@@ -4181,11 +4959,14 @@ +@@ -4181,11 +4892,14 @@ ) (define_insn "*arm_negsi2" @@ -32884,81 +36344,7 @@ ) (define_insn "*thumb1_negsi2" -@@ -4209,6 +4990,73 @@ - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "") - -+;; Negate an extended 32-bit value. -+(define_insn_and_split "*negdi_extendsidi" -+ [(set (match_operand:DI 0 "s_register_operand" "=r,&r,l,&l") -+ (neg:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "0,r,0,l")))) -+ (clobber (reg:CC CC_REGNUM))] -+ "TARGET_32BIT" -+ "#" ; rsb\\t%Q0, %1, #0\;asr\\t%R0, %Q0, #31 -+ "&& reload_completed" -+ [(const_int 0)] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ rtx tmp = gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_MINUS (SImode, -+ const0_rtx, -+ operands[1])); -+ if (TARGET_ARM) -+ { -+ emit_insn (tmp); -+ } -+ else -+ { -+ /* Set the flags, to emit the short encoding in Thumb2. */ -+ rtx flags = gen_rtx_SET (VOIDmode, -+ gen_rtx_REG (CCmode, CC_REGNUM), -+ gen_rtx_COMPARE (CCmode, -+ const0_rtx, -+ operands[1])); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, -+ gen_rtvec (2, -+ flags, -+ tmp))); -+ } -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[2], -+ gen_rtx_ASHIFTRT (SImode, -+ operands[0], -+ GEN_INT (31)))); -+ DONE; -+ } -+ [(set_attr "length" "8,8,4,4") -+ (set_attr "arch" "a,a,t2,t2")] -+) -+ -+(define_insn_and_split "*negdi_zero_extendsidi" -+ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") -+ (neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r")))) -+ (clobber (reg:CC CC_REGNUM))] -+ "TARGET_32BIT" -+ "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0" -+ ;; Don't care what register is input to sbc, -+ ;; since we just just need to propagate the carry. -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (const_int 0) (match_dup 1))) -+ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) -+ (set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ } -+ [(set_attr "conds" "clob") -+ (set_attr "length" "8")] ;; length in thumb is 4 -+) -+ - ;; abssi2 doesn't really clobber the condition codes if a different register - ;; is being set. To keep things simple, assume during rtl manipulations that - ;; it does, but tell the final scan operator the truth. Similarly for -@@ -4227,14 +5075,67 @@ +@@ -4227,14 +4941,67 @@ operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); ") @@ -33030,7 +36416,7 @@ [(set_attr "conds" "clob,*") (set_attr "shift" "1") (set_attr "predicable" "no, yes") -@@ -4255,14 +5156,56 @@ +@@ -4255,14 +5022,56 @@ [(set_attr "length" "6")] ) @@ -33091,7 +36477,7 @@ [(set_attr "conds" "clob,*") (set_attr "shift" "1") (set_attr "predicable" "no, yes") -@@ -4330,7 +5273,7 @@ +@@ -4330,7 +5139,7 @@ [(set_attr "length" "*,8,8,*") (set_attr "predicable" "no,yes,yes,no") (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") @@ -33100,7 +36486,7 @@ ) (define_expand "one_cmplsi2" -@@ -4341,12 +5284,15 @@ +@@ -4341,12 +5150,15 @@ ) (define_insn "*arm_one_cmplsi2" @@ -33119,7 +36505,7 @@ ) (define_insn "*thumb1_one_cmplsi2" -@@ -4355,7 +5301,7 @@ +@@ -4355,7 +5167,7 @@ "TARGET_THUMB1" "mvn\\t%0, %1" [(set_attr "length" "2") @@ -33128,7 +36514,7 @@ ) (define_insn "*notsi_compare0" -@@ -4367,7 +5313,7 @@ +@@ -4367,7 +5179,7 @@ "TARGET_32BIT" "mvn%.\\t%0, %1" [(set_attr "conds" "set") @@ -33137,7 +36523,7 @@ ) (define_insn "*notsi_compare0_scratch" -@@ -4378,7 +5324,7 @@ +@@ -4378,7 +5190,7 @@ "TARGET_32BIT" "mvn%.\\t%0, %1" [(set_attr "conds" "set") @@ -33146,7 +36532,7 @@ ) ;; Fixed <--> Floating conversion insns -@@ -4498,7 +5444,7 @@ +@@ -4498,7 +5310,7 @@ "TARGET_32BIT " "#" [(set_attr "length" "8,4,8,8") @@ -33155,7 +36541,7 @@ (set_attr "ce_count" "2") (set_attr "predicable" "yes")] ) -@@ -4513,7 +5459,7 @@ +@@ -4513,7 +5325,7 @@ (set_attr "ce_count" "2") (set_attr "shift" "1") (set_attr "predicable" "yes") @@ -33164,7 +36550,7 @@ ) ;; Splits for all extensions to DImode -@@ -4639,7 +5585,7 @@ +@@ -4639,7 +5451,7 @@ [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) @@ -33173,7 +36559,7 @@ ) (define_insn "*arm_zero_extendhisi2" -@@ -4649,7 +5595,7 @@ +@@ -4649,7 +5461,7 @@ "@ # ldr%(h%)\\t%0, %1" @@ -33182,7 +36568,7 @@ (set_attr "predicable" "yes")] ) -@@ -4661,7 +5607,7 @@ +@@ -4661,7 +5473,7 @@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" [(set_attr "predicable" "yes") @@ -33191,7 +36577,7 @@ ) (define_insn "*arm_zero_extendhisi2addsi" -@@ -4670,8 +5616,9 @@ +@@ -4670,8 +5482,9 @@ (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "uxtah%?\\t%0, %2, %1" @@ -33203,7 +36589,7 @@ ) (define_expand "zero_extendqisi2" -@@ -4719,7 +5666,7 @@ +@@ -4719,7 +5532,7 @@ # ldrb\\t%0, %1" [(set_attr "length" "4,2") @@ -33212,7 +36598,7 @@ (set_attr "pool_range" "*,32")] ) -@@ -4731,7 +5678,7 @@ +@@ -4731,7 +5544,7 @@ uxtb\\t%0, %1 ldrb\\t%0, %1" [(set_attr "length" "2") @@ -33221,7 +36607,7 @@ ) (define_insn "*arm_zero_extendqisi2" -@@ -4742,7 +5689,7 @@ +@@ -4742,7 +5555,7 @@ # ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "length" "8,4") @@ -33230,7 +36616,7 @@ (set_attr "predicable" "yes")] ) -@@ -4753,7 +5700,7 @@ +@@ -4753,7 +5566,7 @@ "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" @@ -33239,7 +36625,7 @@ (set_attr "predicable" "yes")] ) -@@ -4764,8 +5711,8 @@ +@@ -4764,8 +5577,8 @@ "TARGET_INT_SIMD" "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") @@ -33250,7 +36636,7 @@ ) (define_split -@@ -4816,7 +5763,8 @@ +@@ -4816,7 +5629,8 @@ "TARGET_32BIT" "tst%?\\t%0, #255" [(set_attr "conds" "set") @@ -33260,7 +36646,7 @@ ) (define_expand "extendhisi2" -@@ -4927,7 +5875,7 @@ +@@ -4927,7 +5741,7 @@ [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) @@ -33269,7 +36655,7 @@ (set_attr "pool_range" "*,1018")] ) -@@ -4986,7 +5934,7 @@ +@@ -4986,7 +5800,7 @@ # ldr%(sh%)\\t%0, %1" [(set_attr "length" "8,4") @@ -33278,7 +36664,7 @@ (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] -@@ -5000,8 +5948,9 @@ +@@ -5000,8 +5814,9 @@ "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" @@ -33289,7 +36675,7 @@ (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] ) -@@ -5086,7 +6035,7 @@ +@@ -5086,7 +5901,7 @@ # ldr%(sb%)\\t%0, %1" [(set_attr "length" "8,4") @@ -33298,7 +36684,7 @@ (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] -@@ -5100,7 +6049,7 @@ +@@ -5100,7 +5915,7 @@ "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" @@ -33307,7 +36693,7 @@ (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] -@@ -5112,9 +6061,9 @@ +@@ -5112,9 +5927,9 @@ (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" @@ -33320,7 +36706,7 @@ ) (define_split -@@ -5213,7 +6162,7 @@ +@@ -5213,7 +6028,7 @@ (const_int 2) (if_then_else (eq_attr "is_arch6" "yes") (const_int 4) (const_int 6))]) @@ -33329,7 +36715,7 @@ ) (define_expand "extendsfdf2" -@@ -5313,8 +6262,8 @@ +@@ -5313,8 +6128,8 @@ ) (define_insn "*arm_movdi" @@ -33340,7 +36726,7 @@ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_VFP) && !TARGET_IWMMXT -@@ -5472,8 +6421,7 @@ +@@ -5472,8 +6287,7 @@ } }" [(set_attr "length" "4,4,6,2,2,6,4,4") @@ -33350,7 +36736,7 @@ (set_attr "pool_range" "*,*,*,*,*,1018,*,*")] ) -@@ -5570,6 +6518,7 @@ +@@ -5570,6 +6384,7 @@ "arm_arch_thumb2" "movt%?\t%0, #:upper16:%c2" [(set_attr "predicable" "yes") @@ -33358,7 +36744,7 @@ (set_attr "length" "4")] ) -@@ -5587,8 +6536,7 @@ +@@ -5587,8 +6402,7 @@ movw%?\\t%0, %1 ldr%?\\t%0, %1 str%?\\t%1, %0" @@ -33368,7 +36754,7 @@ (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,*,*,4096,*") (set_attr "neg_pool_range" "*,*,*,*,4084,*")] -@@ -5890,7 +6838,7 @@ +@@ -5890,7 +6704,7 @@ cmp%?\\t%0, #0 sub%.\\t%0, %1, #0" [(set_attr "conds" "set") @@ -33377,7 +36763,7 @@ ) ;; Subroutine to store a half word from a register into memory. -@@ -6304,14 +7252,13 @@ +@@ -6304,14 +7118,13 @@ str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "predicable" "yes") @@ -33395,7 +36781,7 @@ (const_string "store1") (const_string "load1")])] ) -@@ -6325,8 +7272,7 @@ +@@ -6325,8 +7138,7 @@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi" [(set_attr "predicable" "yes") @@ -33405,7 +36791,7 @@ ) (define_expand "thumb_movhi_clobber" -@@ -6449,26 +7395,27 @@ +@@ -6449,26 +7261,27 @@ " ) @@ -33440,7 +36826,7 @@ ) (define_insn "*thumb1_movqi_insn" -@@ -6485,8 +7432,7 @@ +@@ -6485,8 +7298,7 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") @@ -33450,7 +36836,7 @@ (set_attr "pool_range" "*,32,*,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")]) -@@ -6515,7 +7461,7 @@ +@@ -6515,7 +7327,7 @@ (define_insn "*arm32_movhf" [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r") (match_operand:HF 1 "general_operand" " m,r,r,F"))] @@ -33459,7 +36845,7 @@ && ( s_register_operand (operands[0], HFmode) || s_register_operand (operands[1], HFmode))" "* -@@ -6551,8 +7497,7 @@ +@@ -6551,8 +7363,7 @@ } " [(set_attr "conds" "unconditional") @@ -33469,7 +36855,7 @@ (set_attr "length" "4,4,4,8") (set_attr "predicable" "yes")] ) -@@ -6587,8 +7532,7 @@ +@@ -6587,8 +7398,7 @@ } " [(set_attr "length" "2") @@ -33479,7 +36865,7 @@ (set_attr "pool_range" "*,1018,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond")]) -@@ -6642,8 +7586,8 @@ +@@ -6642,8 +7452,8 @@ ldr%?\\t%0, %1\\t%@ float str%?\\t%1, %0\\t%@ float" [(set_attr "predicable" "yes") @@ -33490,7 +36876,7 @@ (set_attr "arm_pool_range" "*,4096,*") (set_attr "thumb2_pool_range" "*,4094,*") (set_attr "arm_neg_pool_range" "*,4084,*") -@@ -6666,9 +7610,8 @@ +@@ -6666,9 +7476,8 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") @@ -33501,7 +36887,7 @@ (set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")] ) -@@ -6738,8 +7681,8 @@ +@@ -6738,8 +7547,8 @@ ) (define_insn "*movdf_soft_insn" @@ -33512,7 +36898,7 @@ "TARGET_32BIT && TARGET_SOFT_FLOAT && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" -@@ -6799,8 +7742,7 @@ +@@ -6799,8 +7608,7 @@ } " [(set_attr "length" "4,2,2,6,4,4") @@ -33522,7 +36908,7 @@ (set_attr "pool_range" "*,*,*,1018,*,*")] ) -@@ -6869,10 +7811,18 @@ +@@ -6869,10 +7677,18 @@ (match_operand:BLK 1 "general_operand" "") (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" "")] @@ -33542,7 +36928,7 @@ if (arm_gen_movmemqi (operands)) DONE; FAIL; -@@ -7568,7 +8518,7 @@ +@@ -7568,7 +8384,7 @@ (set_attr "arch" "t2,t2,any,any") (set_attr "length" "2,2,4,4") (set_attr "predicable" "yes") @@ -33551,7 +36937,7 @@ ) (define_insn "*cmpsi_shiftsi" -@@ -7582,7 +8532,7 @@ +@@ -7582,7 +8398,7 @@ [(set_attr "conds" "set") (set_attr "shift" "1") (set_attr "arch" "32,a") @@ -33560,7 +36946,7 @@ (define_insn "*cmpsi_shiftsi_swp" [(set (reg:CC_SWP CC_REGNUM) -@@ -7595,7 +8545,7 @@ +@@ -7595,7 +8411,7 @@ [(set_attr "conds" "set") (set_attr "shift" "1") (set_attr "arch" "32,a") @@ -33569,7 +36955,7 @@ (define_insn "*arm_cmpsi_negshiftsi_si" [(set (reg:CC_Z CC_REGNUM) -@@ -7608,8 +8558,8 @@ +@@ -7608,8 +8424,8 @@ "cmn%?\\t%0, %2%S1" [(set_attr "conds" "set") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") @@ -33580,7 +36966,7 @@ (set_attr "predicable" "yes")] ) -@@ -7617,25 +8567,69 @@ +@@ -7617,25 +8433,69 @@ ;; if-conversion can not reduce to a conditional compare, so we do ;; that directly. @@ -33657,7 +37043,7 @@ ) (define_insn "*arm_cmpdi_zero" -@@ -7758,36 +8752,56 @@ +@@ -7758,36 +8618,56 @@ operands[3] = const0_rtx;" ) @@ -33723,7 +37109,7 @@ (set_attr "length" "8")] ) -@@ -8069,7 +9083,7 @@ +@@ -8069,7 +8949,7 @@ (define_expand "movsfcc" [(set (match_operand:SF 0 "s_register_operand" "") @@ -33732,7 +37118,7 @@ (match_operand:SF 2 "s_register_operand" "") (match_operand:SF 3 "s_register_operand" "")))] "TARGET_32BIT && TARGET_HARD_FLOAT" -@@ -8091,7 +9105,7 @@ +@@ -8091,7 +8971,7 @@ (define_expand "movdfcc" [(set (match_operand:DF 0 "s_register_operand" "") @@ -33741,7 +37127,7 @@ (match_operand:DF 2 "s_register_operand" "") (match_operand:DF 3 "s_register_operand" "")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" -@@ -8110,7 +9124,40 @@ +@@ -8110,7 +8990,40 @@ }" ) @@ -33783,7 +37169,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") (if_then_else:SI (match_operator 3 "arm_comparison_operator" -@@ -8123,26 +9170,60 @@ +@@ -8123,26 +9036,60 @@ mvn%D3\\t%0, #%B2 mov%d3\\t%0, %1 mvn%d3\\t%0, #%B1 @@ -33859,7 +37245,7 @@ ) (define_insn "*movsfcc_soft_insn" -@@ -8156,7 +9237,7 @@ +@@ -8156,7 +9103,7 @@ mov%D3\\t%0, %2 mov%d3\\t%0, %1" [(set_attr "conds" "use") @@ -33868,7 +37254,7 @@ ) -@@ -8255,7 +9336,7 @@ +@@ -8255,7 +9202,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33877,7 +37263,7 @@ "blx%?\\t%0" [(set_attr "type" "call")] ) -@@ -8265,7 +9346,7 @@ +@@ -8265,7 +9212,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33886,7 +37272,7 @@ "* return output_call (operands); " -@@ -8284,7 +9365,7 @@ +@@ -8284,7 +9231,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33895,7 +37281,7 @@ "* return output_call_mem (operands); " -@@ -8297,7 +9378,7 @@ +@@ -8297,7 +9244,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33904,7 +37290,7 @@ "blx\\t%0" [(set_attr "length" "2") (set_attr "type" "call")] -@@ -8308,7 +9389,7 @@ +@@ -8308,7 +9255,7 @@ (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33913,7 +37299,7 @@ "* { if (!TARGET_CALLER_INTERWORKING) -@@ -8367,7 +9448,7 @@ +@@ -8367,7 +9314,7 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33922,7 +37308,7 @@ "blx%?\\t%1" [(set_attr "type" "call")] ) -@@ -8378,7 +9459,7 @@ +@@ -8378,7 +9325,7 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33931,7 +37317,7 @@ "* return output_call (&operands[1]); " -@@ -8394,7 +9475,8 @@ +@@ -8394,7 +9341,8 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -33941,7 +37327,7 @@ "* return output_call_mem (&operands[1]); " -@@ -8444,6 +9526,7 @@ +@@ -8444,6 +9392,7 @@ (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] "TARGET_32BIT @@ -33949,7 +37335,7 @@ && (GET_CODE (operands[0]) == SYMBOL_REF) && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" "* -@@ -8460,6 +9543,7 @@ +@@ -8460,6 +9409,7 @@ (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] "TARGET_32BIT @@ -33957,7 +37343,7 @@ && (GET_CODE (operands[1]) == SYMBOL_REF) && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" "* -@@ -8505,6 +9589,10 @@ +@@ -8505,6 +9455,10 @@ "TARGET_32BIT" " { @@ -33968,7 +37354,7 @@ if (operands[2] == NULL_RTX) operands[2] = const0_rtx; }" -@@ -8519,47 +9607,67 @@ +@@ -8519,47 +9473,67 @@ "TARGET_32BIT" " { @@ -34046,7 +37432,7 @@ DONE; } } -@@ -8584,13 +9692,13 @@ +@@ -8584,13 +9558,13 @@ (set_attr "predicable" "yes")] ) @@ -34063,7 +37449,7 @@ "* { if (arm_ccfsm_state == 2) -@@ -8598,20 +9706,21 @@ +@@ -8598,20 +9572,21 @@ arm_ccfsm_state += 2; return \"\"; } @@ -34089,7 +37475,7 @@ "* { if (arm_ccfsm_state == 2) -@@ -8619,7 +9728,8 @@ +@@ -8619,7 +9594,8 @@ arm_ccfsm_state += 2; return \"\"; } @@ -34099,7 +37485,7 @@ }" [(set_attr "conds" "use") (set_attr "length" "12") -@@ -8991,7 +10101,7 @@ +@@ -8991,7 +9967,7 @@ (if_then_else (match_operand:SI 3 "mult_operator" "") (const_string "no") (const_string "yes"))]) @@ -34108,7 +37494,7 @@ (define_split [(set (match_operand:SI 0 "s_register_operand" "") -@@ -9028,7 +10138,7 @@ +@@ -9028,7 +10004,7 @@ [(set_attr "conds" "set") (set_attr "shift" "4") (set_attr "arch" "32,a") @@ -34117,7 +37503,7 @@ (define_insn "*arith_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) -@@ -9045,7 +10155,7 @@ +@@ -9045,7 +10021,7 @@ [(set_attr "conds" "set") (set_attr "shift" "4") (set_attr "arch" "32,a") @@ -34126,7 +37512,7 @@ (define_insn "*sub_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") -@@ -9058,7 +10168,7 @@ +@@ -9058,7 +10034,7 @@ [(set_attr "predicable" "yes") (set_attr "shift" "3") (set_attr "arch" "32,a") @@ -34135,7 +37521,7 @@ (define_insn "*sub_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) -@@ -9076,7 +10186,7 @@ +@@ -9076,7 +10052,7 @@ [(set_attr "conds" "set") (set_attr "shift" "3") (set_attr "arch" "32,a") @@ -34144,7 +37530,7 @@ (define_insn "*sub_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) -@@ -9092,30 +10202,67 @@ +@@ -9092,30 +10068,67 @@ [(set_attr "conds" "set") (set_attr "shift" "3") (set_attr "arch" "32,a") @@ -34224,7 +37610,7 @@ [(set_attr "conds" "use") (set_attr "length" "4,8")] ) -@@ -9144,6 +10291,16 @@ +@@ -9144,6 +10157,16 @@ (eq:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] @@ -34241,7 +37627,7 @@ "TARGET_32BIT && reload_completed" [(parallel [(set (reg:CC CC_REGNUM) -@@ -9184,7 +10341,7 @@ +@@ -9184,7 +10207,7 @@ (set (match_dup 0) (const_int 1)))]) (define_insn_and_split "*compare_scc" @@ -34250,7 +37636,7 @@ (match_operator:SI 1 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rI,L")])) -@@ -9213,29 +10370,93 @@ +@@ -9213,29 +10236,93 @@ ;; Attempt to improve the sequence generated by the compare_scc splitters ;; not to use conditional execution. @@ -34354,7 +37740,7 @@ (define_insn "*cond_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") -@@ -9262,7 +10483,7 @@ +@@ -9262,7 +10349,7 @@ return \"\"; " [(set_attr "conds" "use") @@ -34363,7 +37749,7 @@ (set_attr "length" "4,4,8")] ) -@@ -9636,7 +10857,7 @@ +@@ -9636,7 +10723,7 @@ ) (define_insn_and_split "*ior_scc_scc" @@ -34372,7 +37758,7 @@ (ior:SI (match_operator:SI 3 "arm_comparison_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_add_operand" "rIL")]) -@@ -9674,7 +10895,7 @@ +@@ -9674,7 +10761,7 @@ [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "arm_add_operand" "rIL")])) (const_int 0))) @@ -34381,7 +37767,7 @@ (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] "TARGET_32BIT" -@@ -9692,7 +10913,7 @@ +@@ -9692,7 +10779,7 @@ (set_attr "length" "16")]) (define_insn_and_split "*and_scc_scc" @@ -34390,7 +37776,7 @@ (and:SI (match_operator:SI 3 "arm_comparison_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_add_operand" "rIL")]) -@@ -9732,7 +10953,7 @@ +@@ -9732,7 +10819,7 @@ [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "arm_add_operand" "rIL")])) (const_int 0))) @@ -34399,7 +37785,7 @@ (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] "TARGET_32BIT" -@@ -9754,7 +10975,7 @@ +@@ -9754,7 +10841,7 @@ ;; need only zero the value if false (if true, then the value is already ;; correct). (define_insn_and_split "*and_scc_scc_nodom" @@ -34408,7 +37794,7 @@ (and:SI (match_operator:SI 3 "arm_comparison_operator" [(match_operand:SI 1 "s_register_operand" "r,r,0") (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")]) -@@ -9822,24 +11043,75 @@ +@@ -9822,28 +10909,117 @@ "") ;; ??? The conditional patterns above need checking for Thumb-2 usefulness @@ -34494,7 +37880,49 @@ [(set_attr "conds" "clob") (set_attr "length" "12")] ) -@@ -9944,9 +11216,9 @@ + ++(define_insn_and_split "movcond_addsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") ++ (if_then_else:SI ++ (match_operator 5 "comparison_operator" ++ [(plus:SI (match_operand:SI 3 "s_register_operand" "r,r,r") ++ (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")) ++ (const_int 0)]) ++ (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r") ++ (match_operand:SI 2 "arm_rhs_operand" "rI,rPy,r"))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV ++ (plus:SI (match_dup 3) ++ (match_dup 4)) ++ (const_int 0))) ++ (set (match_dup 0) (match_dup 1)) ++ (cond_exec (match_dup 6) ++ (set (match_dup 0) (match_dup 2)))] ++ " ++ { ++ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]), ++ operands[3], operands[4]); ++ enum rtx_code rc = GET_CODE (operands[5]); ++ ++ operands[6] = gen_rtx_REG (mode, CC_REGNUM); ++ gcc_assert (!(mode == CCFPmode || mode == CCFPEmode)); ++ rc = reverse_condition (rc); ++ ++ operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); ++ } ++ " ++ [(set_attr "conds" "clob") ++ (set_attr "enabled_for_depr_it" "no,yes,yes")] ++) ++ + (define_insn "movcond" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (if_then_else:SI +@@ -9944,9 +11120,9 @@ (set_attr "length" "4,4,8,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") @@ -34506,7 +37934,7 @@ (const_string "*") (const_string "*")])] ) -@@ -9986,9 +11258,9 @@ +@@ -9986,9 +11162,9 @@ (set_attr "length" "4,4,8,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") @@ -34518,7 +37946,7 @@ (const_string "*") (const_string "*")])] ) -@@ -10174,7 +11446,7 @@ +@@ -10174,7 +11350,7 @@ mov%d4\\t%0, %1\;mvn%D4\\t%0, %2 mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2" [(set_attr "conds" "use") @@ -34527,7 +37955,7 @@ (set_attr "length" "4,8,8")] ) -@@ -10207,7 +11479,7 @@ +@@ -10207,7 +11383,7 @@ mov%D4\\t%0, %1\;mvn%d4\\t%0, %2 mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2" [(set_attr "conds" "use") @@ -34536,7 +37964,7 @@ (set_attr "length" "4,8,8")] ) -@@ -10245,10 +11517,9 @@ +@@ -10245,10 +11421,9 @@ [(set_attr "conds" "use") (set_attr "shift" "2") (set_attr "length" "4,8,8") @@ -34549,7 +37977,7 @@ ) (define_insn "*ifcompare_move_shift" -@@ -10285,10 +11556,9 @@ +@@ -10285,10 +11460,9 @@ [(set_attr "conds" "use") (set_attr "shift" "2") (set_attr "length" "4,8,8") @@ -34562,7 +37990,7 @@ ) (define_insn "*ifcompare_shift_shift" -@@ -10326,12 +11596,11 @@ +@@ -10326,12 +11500,11 @@ [(set_attr "conds" "use") (set_attr "shift" "1") (set_attr "length" "8") @@ -34577,7 +38005,7 @@ ) (define_insn "*ifcompare_not_arith" -@@ -10363,7 +11632,7 @@ +@@ -10363,7 +11536,7 @@ "TARGET_ARM" "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3" [(set_attr "conds" "use") @@ -34586,7 +38014,7 @@ (set_attr "length" "8")] ) -@@ -10396,7 +11665,7 @@ +@@ -10396,7 +11569,7 @@ "TARGET_ARM" "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3" [(set_attr "conds" "use") @@ -34595,7 +38023,7 @@ (set_attr "length" "8")] ) -@@ -10844,7 +12113,7 @@ +@@ -10844,7 +12017,7 @@ mvn%D4\\t%0, %2 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2" [(set_attr "conds" "use") @@ -34604,7 +38032,7 @@ (set_attr "length" "4,8")] ) -@@ -11239,7 +12508,7 @@ +@@ -11239,7 +12412,7 @@ "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") @@ -34613,7 +38041,7 @@ (define_insn "rbitsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") -@@ -11247,7 +12516,7 @@ +@@ -11247,7 +12420,7 @@ "TARGET_32BIT && arm_arch_thumb2" "rbit%?\\t%0, %1" [(set_attr "predicable" "yes") @@ -34622,7 +38050,7 @@ (define_expand "ctzsi2" [(set (match_operand:SI 0 "s_register_operand" "") -@@ -11280,6 +12549,7 @@ +@@ -11280,6 +12453,7 @@ (const_int 0)])] "TARGET_32BIT" "" @@ -34630,7 +38058,7 @@ ) (define_insn "force_register_use" -@@ -11399,7 +12669,8 @@ +@@ -11399,7 +12573,8 @@ "arm_arch_thumb2" "movt%?\t%0, %L1" [(set_attr "predicable" "yes") @@ -34640,7 +38068,7 @@ ) (define_insn "*arm_rev" -@@ -11550,7 +12821,8 @@ +@@ -11550,7 +12725,8 @@ false, true))" "ldrd%?\t%0, %3, [%1, %2]" [(set_attr "type" "load2") @@ -34650,7 +38078,7 @@ (define_insn "*thumb2_ldrd_base" [(set (match_operand:SI 0 "s_register_operand" "=r") -@@ -11564,7 +12836,8 @@ +@@ -11564,7 +12740,8 @@ operands[1], 0, false, true))" "ldrd%?\t%0, %2, [%1]" [(set_attr "type" "load2") @@ -34660,7 +38088,7 @@ (define_insn "*thumb2_ldrd_base_neg" [(set (match_operand:SI 0 "s_register_operand" "=r") -@@ -11578,7 +12851,8 @@ +@@ -11578,7 +12755,8 @@ operands[1], -4, false, true))" "ldrd%?\t%0, %2, [%1, #-4]" [(set_attr "type" "load2") @@ -34670,7 +38098,7 @@ (define_insn "*thumb2_strd" [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") -@@ -11595,7 +12869,8 @@ +@@ -11595,7 +12773,8 @@ false, false))" "strd%?\t%2, %4, [%0, %1]" [(set_attr "type" "store2") @@ -34680,7 +38108,7 @@ (define_insn "*thumb2_strd_base" [(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk")) -@@ -11609,7 +12884,8 @@ +@@ -11609,7 +12788,8 @@ operands[0], 0, false, false))" "strd%?\t%1, %2, [%0]" [(set_attr "type" "store2") @@ -34690,7 +38118,7 @@ (define_insn "*thumb2_strd_base_neg" [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") -@@ -11623,9 +12899,13 @@ +@@ -11623,9 +12803,13 @@ operands[0], -4, false, false))" "strd%?\t%1, %2, [%0, #-4]" [(set_attr "type" "store2") @@ -35562,9 +38990,24 @@ "__builtin_neon_sf", "float", 32, 2; "__builtin_neon_poly8", "poly", 8, 8; "__builtin_neon_poly16", "poly", 16, 4; +--- a/src/gcc/config/mips/linux-common.h ++++ b/src/gcc/config/mips/linux-common.h +@@ -44,7 +44,7 @@ + #undef LIB_SPEC + #define LIB_SPEC \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LIB_SPEC, \ +- GNU_USER_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC " " ANDROID_LIB_SPEC) + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ --- a/src/libobjc/ChangeLog.linaro +++ b/src/libobjc/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35594,7 +39037,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgfortran/ChangeLog.linaro +++ b/src/libgfortran/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35624,7 +39071,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libada/ChangeLog.linaro +++ b/src/libada/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35654,7 +39105,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libffi/ChangeLog.linaro +++ b/src/libffi/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35684,7 +39139,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libssp/ChangeLog.linaro +++ b/src/libssp/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35740,7 +39199,11 @@ hppa*64*-*-* | \ --- a/src/libcpp/ChangeLog.linaro +++ b/src/libcpp/ChangeLog.linaro -@@ -0,0 +1,35 @@ +@@ -0,0 +1,39 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35778,7 +39241,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/po/ChangeLog.linaro +++ b/src/libcpp/po/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. @@ -35808,7 +39275,11 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/fixincludes/ChangeLog.linaro +++ b/src/fixincludes/ChangeLog.linaro -@@ -0,0 +1,27 @@ +@@ -0,0 +1,31 @@ ++2013-10-15 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.10 released. ++ +2013-09-10 Christophe Lyon + + GCC Linaro 4.8-2013.09 released. diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-multiarch.diff gcc-4.8-4.8.2/debian/patches/gcc-multiarch.diff --- gcc-4.8-4.8.1/debian/patches/gcc-multiarch.diff 2013-11-29 20:02:20.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-multiarch.diff 2013-11-29 20:02:23.000000000 +0000 @@ -13,6 +13,31 @@ * config/s390/t-linux64: Set MULTIARCH_DIRNAME. * config/sparc/t-linux64: Set MULTIARCH_DIRNAME. +--- a/src/libstdc++-v3/python/hook.in ++++ b/src/libstdc++-v3/python/hook.in +@@ -47,14 +47,18 @@ + libdir = libdir[len (prefix):] + + # Compute the ".."s needed to get from libdir to the prefix. +- dotdots = ('..' + os.sep) * len (libdir.split (os.sep)) ++ backdirs = len (libdir.split (os.sep)) ++ if not os.path.basename(os.path.dirname(__file__)).startswith('lib'): ++ backdirs += 1 # multiarch subdir ++ dotdots = ('..' + os.sep) * backdirs + + objfile = gdb.current_objfile ().filename + dir_ = os.path.join (os.path.dirname (objfile), dotdots, pythondir) + +- if not dir_ in sys.path: ++ if not objfile.startswith('/usr/lib/debug/') and not dir_ in sys.path: + sys.path.insert(0, dir_) + + # Load the pretty-printers. +-from libstdcxx.v6.printers import register_libstdcxx_printers +-register_libstdcxx_printers (gdb.current_objfile ()) ++if gdb.current_objfile () is None or not gdb.current_objfile ().filename.startswith ('/usr/lib/debug/'): ++ from libstdcxx.v6.printers import register_libstdcxx_printers ++ register_libstdcxx_printers (gdb.current_objfile ()) Index: b/src/gcc/config/sh/t-linux =================================================================== --- a/src/gcc/config/sh/t-linux diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-ppc64el-doc.diff gcc-4.8-4.8.2/debian/patches/gcc-ppc64el-doc.diff --- gcc-4.8-4.8.1/debian/patches/gcc-ppc64el-doc.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-ppc64el-doc.diff 2013-11-29 20:02:23.000000000 +0000 @@ -0,0 +1,751 @@ +# DP: Changes from the ibm/gcc-4_8-branch (documentation) + +LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@204974 \ + svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_8-branch@205351 \ + | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ + +--- a/src/gcc/doc/extend.texi ++++ b/src/gcc/doc/extend.texi +@@ -8793,6 +8793,7 @@ + * picoChip Built-in Functions:: + * PowerPC Built-in Functions:: + * PowerPC AltiVec/VSX Built-in Functions:: ++* PowerPC Hardware Transactional Memory Built-in Functions:: + * RX Built-in Functions:: + * S/390 System z Built-in Functions:: + * SH Built-in Functions:: +@@ -13920,6 +13921,531 @@ + @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, + @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. + ++If the ISA 2.07 additions to the vector/scalar (power8-vector) ++instruction set is available, the following additional functions are ++available for both 32-bit and 64-bit targets. For 64-bit targets, you ++can use @var{vector long} instead of @var{vector long long}, ++@var{vector bool long} instead of @var{vector bool long long}, and ++@var{vector unsigned long} instead of @var{vector unsigned long long}. ++ ++@smallexample ++vector long long vec_abs (vector long long); ++ ++vector long long vec_add (vector long long, vector long long); ++vector unsigned long long vec_add (vector unsigned long long, ++ vector unsigned long long); ++ ++int vec_all_eq (vector long long, vector long long); ++int vec_all_ge (vector long long, vector long long); ++int vec_all_gt (vector long long, vector long long); ++int vec_all_le (vector long long, vector long long); ++int vec_all_lt (vector long long, vector long long); ++int vec_all_ne (vector long long, vector long long); ++int vec_any_eq (vector long long, vector long long); ++int vec_any_ge (vector long long, vector long long); ++int vec_any_gt (vector long long, vector long long); ++int vec_any_le (vector long long, vector long long); ++int vec_any_lt (vector long long, vector long long); ++int vec_any_ne (vector long long, vector long long); ++ ++vector long long vec_eqv (vector long long, vector long long); ++vector long long vec_eqv (vector bool long long, vector long long); ++vector long long vec_eqv (vector long long, vector bool long long); ++vector unsigned long long vec_eqv (vector unsigned long long, ++ vector unsigned long long); ++vector unsigned long long vec_eqv (vector bool long long, ++ vector unsigned long long); ++vector unsigned long long vec_eqv (vector unsigned long long, ++ vector bool long long); ++vector int vec_eqv (vector int, vector int); ++vector int vec_eqv (vector bool int, vector int); ++vector int vec_eqv (vector int, vector bool int); ++vector unsigned int vec_eqv (vector unsigned int, vector unsigned int); ++vector unsigned int vec_eqv (vector bool unsigned int, ++ vector unsigned int); ++vector unsigned int vec_eqv (vector unsigned int, ++ vector bool unsigned int); ++vector short vec_eqv (vector short, vector short); ++vector short vec_eqv (vector bool short, vector short); ++vector short vec_eqv (vector short, vector bool short); ++vector unsigned short vec_eqv (vector unsigned short, vector unsigned short); ++vector unsigned short vec_eqv (vector bool unsigned short, ++ vector unsigned short); ++vector unsigned short vec_eqv (vector unsigned short, ++ vector bool unsigned short); ++vector signed char vec_eqv (vector signed char, vector signed char); ++vector signed char vec_eqv (vector bool signed char, vector signed char); ++vector signed char vec_eqv (vector signed char, vector bool signed char); ++vector unsigned char vec_eqv (vector unsigned char, vector unsigned char); ++vector unsigned char vec_eqv (vector bool unsigned char, vector unsigned char); ++vector unsigned char vec_eqv (vector unsigned char, vector bool unsigned char); ++ ++vector long long vec_max (vector long long, vector long long); ++vector unsigned long long vec_max (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_min (vector long long, vector long long); ++vector unsigned long long vec_min (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_nand (vector long long, vector long long); ++vector long long vec_nand (vector bool long long, vector long long); ++vector long long vec_nand (vector long long, vector bool long long); ++vector unsigned long long vec_nand (vector unsigned long long, ++ vector unsigned long long); ++vector unsigned long long vec_nand (vector bool long long, ++ vector unsigned long long); ++vector unsigned long long vec_nand (vector unsigned long long, ++ vector bool long long); ++vector int vec_nand (vector int, vector int); ++vector int vec_nand (vector bool int, vector int); ++vector int vec_nand (vector int, vector bool int); ++vector unsigned int vec_nand (vector unsigned int, vector unsigned int); ++vector unsigned int vec_nand (vector bool unsigned int, ++ vector unsigned int); ++vector unsigned int vec_nand (vector unsigned int, ++ vector bool unsigned int); ++vector short vec_nand (vector short, vector short); ++vector short vec_nand (vector bool short, vector short); ++vector short vec_nand (vector short, vector bool short); ++vector unsigned short vec_nand (vector unsigned short, vector unsigned short); ++vector unsigned short vec_nand (vector bool unsigned short, ++ vector unsigned short); ++vector unsigned short vec_nand (vector unsigned short, ++ vector bool unsigned short); ++vector signed char vec_nand (vector signed char, vector signed char); ++vector signed char vec_nand (vector bool signed char, vector signed char); ++vector signed char vec_nand (vector signed char, vector bool signed char); ++vector unsigned char vec_nand (vector unsigned char, vector unsigned char); ++vector unsigned char vec_nand (vector bool unsigned char, vector unsigned char); ++vector unsigned char vec_nand (vector unsigned char, vector bool unsigned char); ++ ++vector long long vec_orc (vector long long, vector long long); ++vector long long vec_orc (vector bool long long, vector long long); ++vector long long vec_orc (vector long long, vector bool long long); ++vector unsigned long long vec_orc (vector unsigned long long, ++ vector unsigned long long); ++vector unsigned long long vec_orc (vector bool long long, ++ vector unsigned long long); ++vector unsigned long long vec_orc (vector unsigned long long, ++ vector bool long long); ++vector int vec_orc (vector int, vector int); ++vector int vec_orc (vector bool int, vector int); ++vector int vec_orc (vector int, vector bool int); ++vector unsigned int vec_orc (vector unsigned int, vector unsigned int); ++vector unsigned int vec_orc (vector bool unsigned int, ++ vector unsigned int); ++vector unsigned int vec_orc (vector unsigned int, ++ vector bool unsigned int); ++vector short vec_orc (vector short, vector short); ++vector short vec_orc (vector bool short, vector short); ++vector short vec_orc (vector short, vector bool short); ++vector unsigned short vec_orc (vector unsigned short, vector unsigned short); ++vector unsigned short vec_orc (vector bool unsigned short, ++ vector unsigned short); ++vector unsigned short vec_orc (vector unsigned short, ++ vector bool unsigned short); ++vector signed char vec_orc (vector signed char, vector signed char); ++vector signed char vec_orc (vector bool signed char, vector signed char); ++vector signed char vec_orc (vector signed char, vector bool signed char); ++vector unsigned char vec_orc (vector unsigned char, vector unsigned char); ++vector unsigned char vec_orc (vector bool unsigned char, vector unsigned char); ++vector unsigned char vec_orc (vector unsigned char, vector bool unsigned char); ++ ++vector int vec_pack (vector long long, vector long long); ++vector unsigned int vec_pack (vector unsigned long long, ++ vector unsigned long long); ++vector bool int vec_pack (vector bool long long, vector bool long long); ++ ++vector int vec_packs (vector long long, vector long long); ++vector unsigned int vec_packs (vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned int vec_packsu (vector long long, vector long long); ++ ++vector long long vec_rl (vector long long, ++ vector unsigned long long); ++vector long long vec_rl (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_sl (vector long long, vector unsigned long long); ++vector long long vec_sl (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_sr (vector long long, vector unsigned long long); ++vector unsigned long long char vec_sr (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_sra (vector long long, vector unsigned long long); ++vector unsigned long long vec_sra (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_sub (vector long long, vector long long); ++vector unsigned long long vec_sub (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_unpackh (vector int); ++vector unsigned long long vec_unpackh (vector unsigned int); ++ ++vector long long vec_unpackl (vector int); ++vector unsigned long long vec_unpackl (vector unsigned int); ++ ++vector long long vec_vaddudm (vector long long, vector long long); ++vector long long vec_vaddudm (vector bool long long, vector long long); ++vector long long vec_vaddudm (vector long long, vector bool long long); ++vector unsigned long long vec_vaddudm (vector unsigned long long, ++ vector unsigned long long); ++vector unsigned long long vec_vaddudm (vector bool unsigned long long, ++ vector unsigned long long); ++vector unsigned long long vec_vaddudm (vector unsigned long long, ++ vector bool unsigned long long); ++ ++vector long long vec_vclz (vector long long); ++vector unsigned long long vec_vclz (vector unsigned long long); ++vector int vec_vclz (vector int); ++vector unsigned int vec_vclz (vector int); ++vector short vec_vclz (vector short); ++vector unsigned short vec_vclz (vector unsigned short); ++vector signed char vec_vclz (vector signed char); ++vector unsigned char vec_vclz (vector unsigned char); ++ ++vector signed char vec_vclzb (vector signed char); ++vector unsigned char vec_vclzb (vector unsigned char); ++ ++vector long long vec_vclzd (vector long long); ++vector unsigned long long vec_vclzd (vector unsigned long long); ++ ++vector short vec_vclzh (vector short); ++vector unsigned short vec_vclzh (vector unsigned short); ++ ++vector int vec_vclzw (vector int); ++vector unsigned int vec_vclzw (vector int); ++ ++vector long long vec_vmaxsd (vector long long, vector long long); ++ ++vector unsigned long long vec_vmaxud (vector unsigned long long, ++ unsigned vector long long); ++ ++vector long long vec_vminsd (vector long long, vector long long); ++ ++vector unsigned long long vec_vminud (vector long long, ++ vector long long); ++ ++vector int vec_vpksdss (vector long long, vector long long); ++vector unsigned int vec_vpksdss (vector long long, vector long long); ++ ++vector unsigned int vec_vpkudus (vector unsigned long long, ++ vector unsigned long long); ++ ++vector int vec_vpkudum (vector long long, vector long long); ++vector unsigned int vec_vpkudum (vector unsigned long long, ++ vector unsigned long long); ++vector bool int vec_vpkudum (vector bool long long, vector bool long long); ++ ++vector long long vec_vpopcnt (vector long long); ++vector unsigned long long vec_vpopcnt (vector unsigned long long); ++vector int vec_vpopcnt (vector int); ++vector unsigned int vec_vpopcnt (vector int); ++vector short vec_vpopcnt (vector short); ++vector unsigned short vec_vpopcnt (vector unsigned short); ++vector signed char vec_vpopcnt (vector signed char); ++vector unsigned char vec_vpopcnt (vector unsigned char); ++ ++vector signed char vec_vpopcntb (vector signed char); ++vector unsigned char vec_vpopcntb (vector unsigned char); ++ ++vector long long vec_vpopcntd (vector long long); ++vector unsigned long long vec_vpopcntd (vector unsigned long long); ++ ++vector short vec_vpopcnth (vector short); ++vector unsigned short vec_vpopcnth (vector unsigned short); ++ ++vector int vec_vpopcntw (vector int); ++vector unsigned int vec_vpopcntw (vector int); ++ ++vector long long vec_vrld (vector long long, vector unsigned long long); ++vector unsigned long long vec_vrld (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_vsld (vector long long, vector unsigned long long); ++vector long long vec_vsld (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_vsrad (vector long long, vector unsigned long long); ++vector unsigned long long vec_vsrad (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_vsrd (vector long long, vector unsigned long long); ++vector unsigned long long char vec_vsrd (vector unsigned long long, ++ vector unsigned long long); ++ ++vector long long vec_vsubudm (vector long long, vector long long); ++vector long long vec_vsubudm (vector bool long long, vector long long); ++vector long long vec_vsubudm (vector long long, vector bool long long); ++vector unsigned long long vec_vsubudm (vector unsigned long long, ++ vector unsigned long long); ++vector unsigned long long vec_vsubudm (vector bool long long, ++ vector unsigned long long); ++vector unsigned long long vec_vsubudm (vector unsigned long long, ++ vector bool long long); ++ ++vector long long vec_vupkhsw (vector int); ++vector unsigned long long vec_vupkhsw (vector unsigned int); ++ ++vector long long vec_vupklsw (vector int); ++vector unsigned long long vec_vupklsw (vector int); ++@end smallexample ++ ++If the cryptographic instructions are enabled (@option{-mcrypto} or ++@option{-mcpu=power8}), the following builtins are enabled. ++ ++@smallexample ++vector unsigned long long __builtin_crypto_vsbox (vector unsigned long long); ++ ++vector unsigned long long __builtin_crypto_vcipher (vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned long long __builtin_crypto_vcipherlast ++ (vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned long long __builtin_crypto_vncipher (vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned long long __builtin_crypto_vncipherlast ++ (vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned char __builtin_crypto_vpermxor (vector unsigned char, ++ vector unsigned char, ++ vector unsigned char); ++ ++vector unsigned short __builtin_crypto_vpermxor (vector unsigned short, ++ vector unsigned short, ++ vector unsigned short); ++ ++vector unsigned int __builtin_crypto_vpermxor (vector unsigned int, ++ vector unsigned int, ++ vector unsigned int); ++ ++vector unsigned long long __builtin_crypto_vpermxor (vector unsigned long long, ++ vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned char __builtin_crypto_vpmsumb (vector unsigned char, ++ vector unsigned char); ++ ++vector unsigned short __builtin_crypto_vpmsumb (vector unsigned short, ++ vector unsigned short); ++ ++vector unsigned int __builtin_crypto_vpmsumb (vector unsigned int, ++ vector unsigned int); ++ ++vector unsigned long long __builtin_crypto_vpmsumb (vector unsigned long long, ++ vector unsigned long long); ++ ++vector unsigned long long __builtin_crypto_vshasigmad ++ (vector unsigned long long, int, int); ++ ++vector unsigned int __builtin_crypto_vshasigmaw (vector unsigned int, ++ int, int); ++@end smallexample ++ ++The second argument to the @var{__builtin_crypto_vshasigmad} and ++@var{__builtin_crypto_vshasigmaw} builtin functions must be a constant ++integer that is 0 or 1. The third argument to these builtin functions ++must be a constant integer in the range of 0 to 15. ++ ++@node PowerPC Hardware Transactional Memory Built-in Functions ++@subsection PowerPC Hardware Transactional Memory Built-in Functions ++GCC provides two interfaces for accessing the Hardware Transactional ++Memory (HTM) instructions available on some of the PowerPC family ++of prcoessors (eg, POWER8). The two interfaces come in a low level ++interface, consisting of built-in functions specific to PowerPC and a ++higher level interface consisting of inline functions that are common ++between PowerPC and S/390. ++ ++@subsubsection PowerPC HTM Low Level Built-in Functions ++ ++The following low level built-in functions are available with ++@option{-mhtm} or @option{-mcpu=CPU} where CPU is `power8' or later. ++They all generate the machine instruction that is part of the name. ++ ++The HTM built-ins return true or false depending on their success and ++their arguments match exactly the type and order of the associated ++hardware instruction's operands. Refer to the ISA manual for a ++description of each instruction's operands. ++ ++@smallexample ++unsigned int __builtin_tbegin (unsigned int) ++unsigned int __builtin_tend (unsigned int) ++ ++unsigned int __builtin_tabort (unsigned int) ++unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int) ++unsigned int __builtin_tabortdci (unsigned int, unsigned int, int) ++unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int) ++unsigned int __builtin_tabortwci (unsigned int, unsigned int, int) ++ ++unsigned int __builtin_tcheck (unsigned int) ++unsigned int __builtin_treclaim (unsigned int) ++unsigned int __builtin_trechkpt (void) ++unsigned int __builtin_tsr (unsigned int) ++@end smallexample ++ ++In addition to the above HTM built-ins, we have added built-ins for ++some common extended mnemonics of the HTM instructions: ++ ++@smallexample ++unsigned int __builtin_tendall (void) ++unsigned int __builtin_tresume (void) ++unsigned int __builtin_tsuspend (void) ++@end smallexample ++ ++The following set of built-in functions are available to gain access ++to the HTM specific special purpose registers. ++ ++@smallexample ++unsigned long __builtin_get_texasr (void) ++unsigned long __builtin_get_texasru (void) ++unsigned long __builtin_get_tfhar (void) ++unsigned long __builtin_get_tfiar (void) ++ ++void __builtin_set_texasr (unsigned long); ++void __builtin_set_texasru (unsigned long); ++void __builtin_set_tfhar (unsigned long); ++void __builtin_set_tfiar (unsigned long); ++@end smallexample ++ ++Example usage of these low level built-in functions may look like: ++ ++@smallexample ++#include ++ ++int num_retries = 10; ++ ++while (1) ++ @{ ++ if (__builtin_tbegin (0)) ++ @{ ++ /* Transaction State Initiated. */ ++ if (is_locked (lock)) ++ __builtin_tabort (0); ++ ... transaction code... ++ __builtin_tend (0); ++ break; ++ @} ++ else ++ @{ ++ /* Transaction State Failed. Use locks if the transaction ++ failure is "persistent" or we've tried too many times. */ ++ if (num_retries-- <= 0 ++ || _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ())) ++ @{ ++ acquire_lock (lock); ++ ... non transactional fallback path... ++ release_lock (lock); ++ break; ++ @} ++ @} ++ @} ++@end smallexample ++ ++One final built-in function has been added that returns the value of ++the 2-bit Transaction State field of the Machine Status Register (MSR) ++as stored in @code{CR0}. ++ ++@smallexample ++unsigned long __builtin_ttest (void) ++@end smallexample ++ ++This built-in can be used to determine the current transaction state ++using the following code example: ++ ++@smallexample ++#include ++ ++unsigned char tx_state = _HTM_STATE (__builtin_ttest ()); ++ ++if (tx_state == _HTM_TRANSACTIONAL) ++ @{ ++ /* Code to use in transactional state. */ ++ @} ++else if (tx_state == _HTM_NONTRANSACTIONAL) ++ @{ ++ /* Code to use in non-transactional state. */ ++ @} ++else if (tx_state == _HTM_SUSPENDED) ++ @{ ++ /* Code to use in transaction suspended state. */ ++ @} ++@end smallexample ++ ++@subsubsection PowerPC HTM High Level Inline Functions ++ ++The following high level HTM interface is made available by including ++@code{} and using @option{-mhtm} or @option{-mcpu=CPU} ++where CPU is `power8' or later. This interface is common between PowerPC ++and S/390, allowing users to write one HTM source implementation that ++can be compiled and executed on either system. ++ ++@smallexample ++long __TM_simple_begin (void) ++long __TM_begin (void* const TM_buff) ++long __TM_end (void) ++void __TM_abort (void) ++void __TM_named_abort (unsigned char const code) ++void __TM_resume (void) ++void __TM_suspend (void) ++ ++long __TM_is_user_abort (void* const TM_buff) ++long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code) ++long __TM_is_illegal (void* const TM_buff) ++long __TM_is_footprint_exceeded (void* const TM_buff) ++long __TM_nesting_depth (void* const TM_buff) ++long __TM_is_nested_too_deep(void* const TM_buff) ++long __TM_is_conflict(void* const TM_buff) ++long __TM_is_failure_persistent(void* const TM_buff) ++long __TM_failure_address(void* const TM_buff) ++long long __TM_failure_code(void* const TM_buff) ++@end smallexample ++ ++Using these common set of HTM inline functions, we can create ++a more portable version of the HTM example in the previous ++section that will work on either PowerPC or S/390: ++ ++@smallexample ++#include ++ ++int num_retries = 10; ++TM_buff_type TM_buff; ++ ++while (1) ++ @{ ++ if (__TM_begin (TM_buff)) ++ @{ ++ /* Transaction State Initiated. */ ++ if (is_locked (lock)) ++ __TM_abort (); ++ ... transaction code... ++ __TM_end (); ++ break; ++ @} ++ else ++ @{ ++ /* Transaction State Failed. Use locks if the transaction ++ failure is "persistent" or we've tried too many times. */ ++ if (num_retries-- <= 0 ++ || __TM_is_failure_persistent (TM_buff)) ++ @{ ++ acquire_lock (lock); ++ ... non transactional fallback path... ++ release_lock (lock); ++ break; ++ @} ++ @} ++ @} ++@end smallexample ++ + @node RX Built-in Functions + @subsection RX Built-in Functions + GCC supports some of the RX instructions which cannot be expressed in +--- a/src/gcc/doc/invoke.texi ++++ b/src/gcc/doc/invoke.texi +@@ -855,7 +855,10 @@ + -mno-recip-precision @gol + -mveclibabi=@var{type} -mfriz -mno-friz @gol + -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol +--msave-toc-indirect -mno-save-toc-indirect} ++-msave-toc-indirect -mno-save-toc-indirect @gol ++-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol ++-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol ++-mquad-memory -mno-quad-memory} + + @emph{RX Options} + @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol +@@ -17226,7 +17229,9 @@ + @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol + -mpopcntb -mpopcntd -mpowerpc64 @gol + -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol +--msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} ++-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol ++-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector -mquad-memory @gol ++-mcompat-align-parm -mno-compat-align-parm} + + The particular options set for any particular CPU varies between + compiler versions, depending on what setting seems to produce optimal +@@ -17344,6 +17349,47 @@ + instructions, and also enable the use of built-in functions that allow + more direct access to the VSX instruction set. + ++@item -mcrypto ++@itemx -mno-crypto ++@opindex mcrypto ++@opindex mno-crypto ++Enable the use (disable) of the built-in functions that allow direct ++access to the cryptographic instructions that were added in version ++2.07 of the PowerPC ISA. ++ ++@item -mdirect-move ++@itemx -mno-direct-move ++@opindex mdirect-move ++@opindex mno-direct-move ++Generate code that uses (does not use) the instructions to move data ++between the general purpose registers and the vector/scalar (VSX) ++registers that were added in version 2.07 of the PowerPC ISA. ++ ++@item -mpower8-fusion ++@itemx -mno-power8-fusion ++@opindex mpower8-fusion ++@opindex mno-power8-fusion ++Generate code that keeps (does not keeps) some integer operations ++adjacent so that the instructions can be fused together on power8 and ++later processors. ++ ++@item -mpower8-vector ++@itemx -mno-power8-vector ++@opindex mpower8-vector ++@opindex mno-power8-vector ++Generate code that uses (does not use) the vector and scalar ++instructions that were added in version 2.07 of the PowerPC ISA. Also ++enable the use of built-in functions that allow more direct access to ++the vector instructions. ++ ++@item -mquad-memory ++@itemx -mno-quad-memory ++@opindex mquad-memory ++@opindex mno-quad-memory ++Generate code that uses (does not use) the quad word memory ++instructions. The @option{-mquad-memory} option requires use of ++64-bit mode. ++ + @item -mfloat-gprs=@var{yes/single/double/no} + @itemx -mfloat-gprs + @opindex mfloat-gprs +@@ -17763,7 +17809,8 @@ + @opindex mabi + Extend the current ABI with a particular extension, or remove such extension. + Valid values are @var{altivec}, @var{no-altivec}, @var{spe}, +-@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}@. ++@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}, ++@var{elfv1}, @var{elfv2}@. + + @item -mabi=spe + @opindex mabi=spe +@@ -17785,6 +17832,20 @@ + Change the current ABI to use IEEE extended-precision long double. + This is a PowerPC 32-bit Linux ABI option. + ++@item -mabi=elfv1 ++@opindex mabi=elfv1 ++Change the current ABI to use the ELFv1 ABI. ++This is the default ABI for big-endian PowerPC 64-bit Linux. ++Overriding the default ABI requires special system support and is ++likely to fail in spectacular ways. ++ ++@item -mabi=elfv2 ++@opindex mabi=elfv2 ++Change the current ABI to use the ELFv2 ABI. ++This is the default ABI for little-endian PowerPC 64-bit Linux. ++Overriding the default ABI requires special system support and is ++likely to fail in spectacular ways. ++ + @item -mprototype + @itemx -mno-prototype + @opindex mprototype +@@ -18070,6 +18131,23 @@ + a pointer on AIX and 64-bit Linux systems. If the TOC value is not + saved in the prologue, it is saved just before the call through the + pointer. The @option{-mno-save-toc-indirect} option is the default. ++ ++@item -mcompat-align-parm ++@itemx -mno-compat-align-parm ++@opindex mcompat-align-parm ++Generate (do not generate) code to pass structure parameters with a ++maximum alignment of 64 bits, for compatibility with older versions ++of GCC. ++ ++Older versions of GCC (prior to 4.9.0) incorrectly did not align a ++structure parameter on a 128-bit boundary when that structure contained ++a member requiring 128-bit alignment. This is corrected in more ++recent versions of GCC. This option may be used to generate code ++that is compatible with functions compiled with older versions of ++GCC. ++ ++In this version of the compiler, the @option{-mcompat-align-parm} ++is the default, except when using the Linux ELFv2 ABI. + @end table + + @node RX Options +--- a/src/gcc/doc/md.texi ++++ b/src/gcc/doc/md.texi +@@ -2055,7 +2055,7 @@ + + @end table + +-@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h} ++@item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md} + @table @code + @item b + Address base register +@@ -2069,18 +2069,58 @@ + @item v + Altivec vector register + ++@item wa ++Any VSX register if the -mvsx option was used or NO_REGS. ++ + @item wd +-VSX vector register to hold vector double data ++VSX vector register to hold vector double data or NO_REGS. + + @item wf +-VSX vector register to hold vector float data ++VSX vector register to hold vector float data or NO_REGS. + ++@item wg ++If @option{-mmfpgpr} was used, a floating point register or NO_REGS. ++ ++@item wl ++Floating point register if the LFIWAX instruction is enabled or NO_REGS. ++ ++@item wm ++VSX register if direct move instructions are enabled, or NO_REGS. ++ ++@item wn ++No register (NO_REGS). ++ ++@item wr ++General purpose register if 64-bit instructions are enabled or NO_REGS. ++ + @item ws +-VSX vector register to hold scalar float data ++VSX vector register to hold scalar double values or NO_REGS. + +-@item wa +-Any VSX register ++@item wt ++VSX vector register to hold 128 bit integer or NO_REGS. + ++@item wu ++Altivec register to use for float/32-bit int loads/stores or NO_REGS. ++ ++@item wv ++Altivec register to use for double loads/stores or NO_REGS. ++ ++@item ww ++FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS. ++ ++@item wx ++Floating point register if the STFIWX instruction is enabled or NO_REGS. ++ ++@item wy ++VSX vector register to hold scalar float values or NO_REGS. ++ ++@item wz ++Floating point register if the LFIWZX instruction is enabled or NO_REGS. ++ ++@item wQ ++A memory address that will work with the @code{lq} and @code{stq} ++instructions. ++ + @item h + @samp{MQ}, @samp{CTR}, or @samp{LINK} register + diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-ppc64el.diff gcc-4.8-4.8.2/debian/patches/gcc-ppc64el.diff --- gcc-4.8-4.8.1/debian/patches/gcc-ppc64el.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-ppc64el.diff 2013-11-29 20:02:23.000000000 +0000 @@ -0,0 +1,30501 @@ +# DP: Changes from the ibm/gcc-4_8-branch (20131125) + +LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@204974 \ + svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_8-branch@205351 \ + | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ + +--- a/src/libitm/configure ++++ b/src/libitm/configure +@@ -7270,7 +7270,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -7295,7 +7295,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -7314,7 +7317,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11779,7 +11785,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11782 "configure" ++#line 11788 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11885,7 +11891,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11888 "configure" ++#line 11894 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -17401,7 +17407,44 @@ + esac + LIBITM_CHECK_AS_HTM + ++case "${target_cpu}" in ++powerpc*) ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports HTM" >&5 ++$as_echo_n "checking if the assembler supports HTM... " >&6; } ++if test "${libitm_cv_as_htm+set}" = set; then : ++ $as_echo_n "(cached) " >&6 ++else + ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++asm("tbegin. 0; tend. 0"); ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ libitm_cv_as_htm=yes ++else ++ libitm_cv_as_htm=no ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++ ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libitm_cv_as_htm" >&5 ++$as_echo "$libitm_cv_as_htm" >&6; } ++ if test x$libitm_cv_as_htm = xyes; then ++ ++$as_echo "#define HAVE_AS_HTM 1" >>confdefs.h ++ ++ fi ++ ;; ++esac ++ ++ + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether weak refs work like ELF" >&5 + $as_echo_n "checking whether weak refs work like ELF... " >&6; } + if test "${ac_cv_have_elf_style_weakref+set}" = set; then : +--- a/src/libitm/ChangeLog.ibm ++++ b/src/libitm/ChangeLog.ibm +@@ -0,0 +1,31 @@ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204808: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/powerpc/sjlj.S [__powerpc64__ && _CALL_ELF == 2]: ++ (FUNC): Define ELFv2 variant. ++ (END): Likewise. ++ (HIDDEN): Likewise. ++ (CALL): Likewise. ++ (BASE): Likewise. ++ (LR_SAVE): Likewise. ++ ++2013-07-15 Peter Bergner ++ ++ Backport from mainline ++ 2013-07-15 Peter Bergner ++ ++ * acinclude.m4 (LIBITM_CHECK_AS_HTM): New. ++ * configure.ac: Use it. ++ (AC_CHECK_HEADERS): Check for sys/auxv.h. ++ (AC_CHECK_FUNCS): Check for getauxval. ++ * config.h.in, configure: Rebuild. ++ * configure.tgt (target_cpu): Add -mhtm to XCFLAGS. ++ * config/powerpc/target.h: Include sys/auxv.h and htmintrin.h. ++ (USE_HTM_FASTPATH): Define. ++ (_TBEGIN_STARTED, _TBEGIN_INDETERMINATE, _TBEGIN_PERSISTENT, ++ _HTM_RETRIES) New macros. ++ (htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init, ++ htm_begin_success, htm_commit, htm_transaction_active): New functions. +--- a/src/libitm/configure.tgt ++++ b/src/libitm/configure.tgt +@@ -47,7 +47,10 @@ + # work out any special compilation flags as necessary. + case "${target_cpu}" in + alpha*) ARCH=alpha ;; +- rs6000 | powerpc*) ARCH=powerpc ;; ++ rs6000 | powerpc*) ++ XCFLAGS="${XCFLAGS} -mhtm" ++ ARCH=powerpc ++ ;; + + arm*) ARCH=arm ;; + +--- a/src/libitm/config/powerpc/sjlj.S ++++ b/src/libitm/config/powerpc/sjlj.S +@@ -26,8 +26,27 @@ + + #include "asmcfi.h" + +-#if defined(__powerpc64__) && defined(__ELF__) ++#if defined(__powerpc64__) && _CALL_ELF == 2 + .macro FUNC name ++ .globl \name ++ .type \name, @function ++\name: ++0: addis 2,12,(.TOC.-0b)@ha ++ addi 2,2,(.TOC.-0b)@l ++ .localentry \name, . - \name ++.endm ++.macro END name ++ .size \name, . - \name ++.endm ++.macro HIDDEN name ++ .hidden \name ++.endm ++.macro CALL name ++ bl \name ++ nop ++.endm ++#elif defined(__powerpc64__) && defined(__ELF__) ++.macro FUNC name + .globl \name, .\name + .section ".opd","aw" + .align 3 +@@ -117,6 +136,9 @@ + #if defined(_CALL_AIXDESC) + # define BASE 6*WS + # define LR_SAVE 2*WS ++#elif _CALL_ELF == 2 ++# define BASE 6*WS ++# define LR_SAVE 2*WS + #elif defined(_CALL_SYSV) + # define BASE 2*WS + # define LR_SAVE 1*WS +--- a/src/libitm/config/powerpc/target.h ++++ b/src/libitm/config/powerpc/target.h +@@ -22,6 +22,10 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + ++#ifdef HAVE_SYS_AUXV_H ++#include ++#endif ++ + namespace GTM HIDDEN { + + typedef int v128 __attribute__((vector_size(16), may_alias, aligned(16))); +@@ -55,4 +59,82 @@ + __asm volatile ("" : : : "memory"); + } + ++// Use HTM if it is supported by the system. ++// See gtm_thread::begin_transaction for how these functions are used. ++#if defined (__linux__) \ ++ && defined (HAVE_AS_HTM) \ ++ && defined (HAVE_GETAUXVAL) \ ++ && defined (AT_HWCAP2) \ ++ && defined (PPC_FEATURE2_HAS_HTM) ++ ++#include ++ ++#define USE_HTM_FASTPATH ++ ++#define _TBEGIN_STARTED 0 ++#define _TBEGIN_INDETERMINATE 1 ++#define _TBEGIN_PERSISTENT 2 ++ ++/* Number of retries for transient failures. */ ++#define _HTM_RETRIES 10 ++ ++static inline bool ++htm_available (void) ++{ ++ return (getauxval (AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) ? true : false; ++} ++ ++static inline uint32_t ++htm_init (void) ++{ ++ // Maximum number of times we try to execute a transaction ++ // as a HW transaction. ++ return htm_available () ? _HTM_RETRIES : 0; ++} ++ ++static inline uint32_t ++htm_begin (void) ++{ ++ if (__builtin_expect (__builtin_tbegin (0), 1)) ++ return _TBEGIN_STARTED; ++ ++ if (_TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ())) ++ return _TBEGIN_PERSISTENT; ++ ++ return _TBEGIN_INDETERMINATE; ++} ++ ++static inline bool ++htm_begin_success (uint32_t begin_ret) ++{ ++ return begin_ret == _TBEGIN_STARTED; ++} ++ ++static inline void ++htm_commit (void) ++{ ++ __builtin_tend (0); ++} ++ ++static inline void ++htm_abort (void) ++{ ++ __builtin_tabort (0); ++} ++ ++static inline bool ++htm_abort_should_retry (uint32_t begin_ret) ++{ ++ return begin_ret != _TBEGIN_PERSISTENT; ++} ++ ++/* Returns true iff a hardware transaction is currently being executed. */ ++static inline bool ++htm_transaction_active (void) ++{ ++ return (_HTM_STATE (__builtin_ttest ()) == _HTM_TRANSACTIONAL); ++} ++ ++#endif ++ + } // namespace GTM +--- a/src/libitm/acinclude.m4 ++++ b/src/libitm/acinclude.m4 +@@ -134,6 +134,20 @@ + ;; + esac]) + ++dnl Check if as supports HTM instructions. ++AC_DEFUN([LIBITM_CHECK_AS_HTM], [ ++case "${target_cpu}" in ++powerpc*) ++ AC_CACHE_CHECK([if the assembler supports HTM], libitm_cv_as_htm, [ ++ AC_TRY_COMPILE([], [asm("tbegin. 0; tend. 0");], ++ [libitm_cv_as_htm=yes], [libitm_cv_as_htm=no]) ++ ]) ++ if test x$libitm_cv_as_htm = xyes; then ++ AC_DEFINE(HAVE_AS_HTM, 1, [Define to 1 if the assembler supports HTM.]) ++ fi ++ ;; ++esac]) ++ + sinclude(../libtool.m4) + dnl The lines below arrange for aclocal not to bring an installed + dnl libtool.m4 into aclocal.m4, while still arranging for automake to +--- a/src/libtool.m4 ++++ b/src/libtool.m4 +@@ -1220,7 +1220,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -1241,7 +1241,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -1260,7 +1263,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +--- a/src/libgomp/configure ++++ b/src/libgomp/configure +@@ -6580,7 +6580,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6605,7 +6605,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6624,7 +6627,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11088,7 +11094,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11091 "configure" ++#line 11097 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11194,7 +11200,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11197 "configure" ++#line 11203 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/libquadmath/configure ++++ b/src/libquadmath/configure +@@ -6248,7 +6248,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6273,7 +6273,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6292,7 +6295,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -10521,7 +10527,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10524 "configure" ++#line 10530 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -10627,7 +10633,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10630 "configure" ++#line 10636 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/libsanitizer/configure ++++ b/src/libsanitizer/configure +@@ -6604,7 +6604,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6629,7 +6629,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6648,7 +6651,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11111,7 +11117,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11114 "configure" ++#line 11120 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11217,7 +11223,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11220 "configure" ++#line 11226 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/zlib/configure ++++ b/src/zlib/configure +@@ -5853,7 +5853,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -5878,7 +5878,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -5897,7 +5900,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -10394,7 +10400,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10397 "configure" ++#line 10403 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -10500,7 +10506,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10503 "configure" ++#line 10509 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/libstdc++-v3/configure ++++ b/src/libstdc++-v3/configure +@@ -7111,7 +7111,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -7136,7 +7136,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -7155,7 +7158,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11513,7 +11519,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11516 "configure" ++#line 11522 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11619,7 +11625,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11622 "configure" ++#line 11628 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -15033,7 +15039,7 @@ + # + # Fake what AC_TRY_COMPILE does. XXX Look at redoing this new-style. + cat > conftest.$ac_ext << EOF +-#line 15036 "configure" ++#line 15042 "configure" + struct S { ~S(); }; + void bar(); + void foo() +@@ -15383,7 +15389,7 @@ + # Fake what AC_TRY_COMPILE does. + + cat > conftest.$ac_ext << EOF +-#line 15386 "configure" ++#line 15392 "configure" + int main() + { + typedef bool atomic_type; +@@ -15418,7 +15424,7 @@ + rm -f conftest* + + cat > conftest.$ac_ext << EOF +-#line 15421 "configure" ++#line 15427 "configure" + int main() + { + typedef short atomic_type; +@@ -15453,7 +15459,7 @@ + rm -f conftest* + + cat > conftest.$ac_ext << EOF +-#line 15456 "configure" ++#line 15462 "configure" + int main() + { + // NB: _Atomic_word not necessarily int. +@@ -15489,7 +15495,7 @@ + rm -f conftest* + + cat > conftest.$ac_ext << EOF +-#line 15492 "configure" ++#line 15498 "configure" + int main() + { + typedef long long atomic_type; +@@ -15568,7 +15574,7 @@ + # unnecessary for this test. + + cat > conftest.$ac_ext << EOF +-#line 15571 "configure" ++#line 15577 "configure" + int main() + { + _Decimal32 d1; +@@ -15610,7 +15616,7 @@ + # unnecessary for this test. + + cat > conftest.$ac_ext << EOF +-#line 15613 "configure" ++#line 15619 "configure" + template + struct same + { typedef T2 type; }; +@@ -15644,7 +15650,7 @@ + rm -f conftest* + + cat > conftest.$ac_ext << EOF +-#line 15647 "configure" ++#line 15653 "configure" + template + struct same + { typedef T2 type; }; +--- a/src/libstdc++-v3/scripts/extract_symvers.in ++++ b/src/libstdc++-v3/scripts/extract_symvers.in +@@ -53,6 +53,7 @@ + # present on Solaris. + ${readelf} ${lib} |\ + sed -e 's/ \[: [A-Fa-f0-9]*\] //' -e '/\.dynsym/,/^$/p;d' |\ ++ sed -e 's/ \[: [0-9]*\] //' |\ + egrep -v ' (LOCAL|UND) ' |\ + egrep -v ' (_DYNAMIC|_GLOBAL_OFFSET_TABLE_|_PROCEDURE_LINKAGE_TABLE_|_edata|_end|_etext)$' |\ + sed -e 's/ : / :_/g' |\ +--- a/src/libstdc++-v3/ChangeLog.ibm ++++ b/src/libstdc++-v3/ChangeLog.ibm +@@ -0,0 +1,19 @@ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204808: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * scripts/extract_symvers.in: Ignore fields ++ in readelf --symbols output. ++ ++2013-08-04 Peter Bergner ++ ++ Backport from mainline ++ 2013-08-01 Fabien Chêne ++ ++ PR c++/54537 ++ * include/tr1/cmath: Remove pow(double,double) overload, remove a ++ duplicated comment about DR 550. Add a comment to explain the issue. ++ * testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc: New. ++ +--- a/src/libstdc++-v3/include/tr1/cmath ++++ b/src/libstdc++-v3/include/tr1/cmath +@@ -846,10 +846,6 @@ + nexttoward(_Tp __x, long double __y) + { return __builtin_nexttoward(__x, __y); } + +- // DR 550. What should the return type of pow(float,int) be? +- // NB: C++0x and TR1 != C++03. +- // using std::pow; +- + inline float + remainder(float __x, float __y) + { return __builtin_remainderf(__x, __y); } +@@ -985,10 +981,19 @@ + + // DR 550. What should the return type of pow(float,int) be? + // NB: C++0x and TR1 != C++03. +- inline double +- pow(double __x, double __y) +- { return std::pow(__x, __y); } + ++ // The std::tr1::pow(double, double) overload cannot be provided ++ // here, because it would clash with ::pow(double,double) declared ++ // in , if is included at the same time (raised ++ // by the fix of PR c++/54537). It is not possible either to use the ++ // using-declaration 'using ::pow;' here, because if the user code ++ // has a 'using std::pow;', it would bring the pow(*,int) averloads ++ // in the tr1 namespace, which is undesirable. Consequently, the ++ // solution is to forward std::tr1::pow(double,double) to ++ // std::pow(double,double) via the templatized version below. See ++ // the discussion about this issue here: ++ // http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01278.html ++ + inline float + pow(float __x, float __y) + { return std::pow(__x, __y); } +--- a/src/libstdc++-v3/testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc ++++ b/src/libstdc++-v3/testsuite/tr1/8_c_compatibility/cmath/pow_cmath.cc +@@ -0,0 +1,33 @@ ++// { dg-do compile } ++ ++// Copyright (C) 2013 Free Software Foundation, Inc. ++// ++// This file is part of the GNU ISO C++ Library. This library is free ++// software; you can redistribute it and/or modify it under the ++// terms of the GNU General Public License as published by the ++// Free Software Foundation; either version 3, or (at your option) ++// any later version. ++ ++// This library is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License along ++// with this library; see the file COPYING3. If not see ++// . ++ ++#include ++using std::pow; ++#include ++#include ++ ++void ++test01() ++{ ++ using namespace __gnu_test; ++ ++ float x = 2080703.375F; ++ check_ret_type(std::pow(x, 2)); ++ check_ret_type(std::tr1::pow(x, 2)); ++} +--- a/src/libmudflap/configure ++++ b/src/libmudflap/configure +@@ -6377,7 +6377,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6402,7 +6402,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6421,7 +6424,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -10615,7 +10621,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10618 "configure" ++#line 10624 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -10721,7 +10727,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10724 "configure" ++#line 10730 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/boehm-gc/configure ++++ b/src/boehm-gc/configure +@@ -6770,7 +6770,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6795,7 +6795,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6814,7 +6817,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11312,7 +11318,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11315 "configure" ++#line 11321 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11418,7 +11424,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11421 "configure" ++#line 11427 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/lto-plugin/configure ++++ b/src/lto-plugin/configure +@@ -6044,7 +6044,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6069,7 +6069,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6088,7 +6091,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -10552,7 +10558,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10555 "configure" ++#line 10561 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -10658,7 +10664,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 10661 "configure" ++#line 10667 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/libatomic/configure ++++ b/src/libatomic/configure +@@ -6505,7 +6505,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6530,7 +6530,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6549,7 +6552,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11013,7 +11019,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11016 "configure" ++#line 11022 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11119,7 +11125,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11122 "configure" ++#line 11128 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/libbacktrace/configure ++++ b/src/libbacktrace/configure +@@ -6842,7 +6842,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -6867,7 +6867,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -6886,7 +6889,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11081,7 +11087,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11084 "configure" ++#line 11090 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11187,7 +11193,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11190 "configure" ++#line 11196 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/libjava/libltdl/configure ++++ b/src/libjava/libltdl/configure +@@ -4806,7 +4806,7 @@ + rm -rf conftest* + ;; + +-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*) ++x86_64-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 +@@ -4820,7 +4820,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_i386" + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -4836,7 +4839,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*) +@@ -6456,11 +6462,11 @@ + -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` +- (eval echo "\"\$as_me:6459: $lt_compile\"" >&5) ++ (eval echo "\"\$as_me:6465: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 +- echo "$as_me:6463: \$? = $ac_status" >&5 ++ echo "$as_me:6469: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. +@@ -6718,11 +6724,11 @@ + -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` +- (eval echo "\"\$as_me:6721: $lt_compile\"" >&5) ++ (eval echo "\"\$as_me:6727: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 +- echo "$as_me:6725: \$? = $ac_status" >&5 ++ echo "$as_me:6731: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. +@@ -6780,11 +6786,11 @@ + -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` +- (eval echo "\"\$as_me:6783: $lt_compile\"" >&5) ++ (eval echo "\"\$as_me:6789: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 +- echo "$as_me:6787: \$? = $ac_status" >&5 ++ echo "$as_me:6793: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized +@@ -8099,7 +8105,7 @@ + libsuff= + case "$host_cpu" in + x86_64*|s390x*|powerpc64*) +- echo '#line 8102 "configure"' > conftest.$ac_ext ++ echo '#line 8108 "configure"' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? +@@ -8652,7 +8658,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext < conftest.$ac_ext < conftest.$ac_ext < conftest.$ac_ext + if AC_TRY_EVAL(ac_compile); then +@@ -529,7 +529,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_i386" + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -545,7 +548,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*) +--- a/src/libjava/classpath/configure ++++ b/src/libjava/classpath/configure +@@ -7577,7 +7577,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -7602,7 +7602,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -7621,7 +7624,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -11820,7 +11826,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11823 "configure" ++#line 11829 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -11926,7 +11932,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 11929 "configure" ++#line 11935 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -25300,7 +25306,7 @@ + JAVA_TEST=Object.java + CLASS_TEST=Object.class + cat << \EOF > $JAVA_TEST +-/* #line 25303 "configure" */ ++/* #line 25309 "configure" */ + package java.lang; + + public class Object +@@ -25393,7 +25399,7 @@ + if uudecode$EXEEXT Test.uue; then + ac_cv_prog_uudecode_base64=yes + else +- echo "configure: 25396: uudecode had trouble decoding base 64 file 'Test.uue'" >&5 ++ echo "configure: 25402: uudecode had trouble decoding base 64 file 'Test.uue'" >&5 + echo "configure: failed file was:" >&5 + cat Test.uue >&5 + ac_cv_prog_uudecode_base64=no +@@ -25421,7 +25427,7 @@ + CLASS_TEST=Test.class + TEST=Test + cat << \EOF > $JAVA_TEST +-/* [#]line 25424 "configure" */ ++/* [#]line 25430 "configure" */ + public class Test { + public static void main (String args[]) { + System.exit (0); +@@ -25629,7 +25635,7 @@ + JAVA_TEST=Test.java + CLASS_TEST=Test.class + cat << \EOF > $JAVA_TEST +- /* #line 25632 "configure" */ ++ /* #line 25638 "configure" */ + public class Test + { + public static void main(String args) +--- a/src/libjava/configure ++++ b/src/libjava/configure +@@ -8842,7 +8842,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -8867,7 +8867,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -8886,7 +8889,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -13382,7 +13388,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 13385 "configure" ++#line 13391 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -13488,7 +13494,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 13491 "configure" ++#line 13497 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -19483,7 +19489,7 @@ + enableval=$enable_sjlj_exceptions; : + else + cat > conftest.$ac_ext << EOF +-#line 19486 "configure" ++#line 19492 "configure" + struct S { ~S(); }; + void bar(); + void foo() +--- a/src/libgcc/config/rs6000/tramp.S ++++ b/src/libgcc/config/rs6000/tramp.S +@@ -116,4 +116,70 @@ + + #endif + ++#elif _CALL_ELF == 2 ++ .type trampoline_initial,@object ++ .align 3 ++trampoline_initial: ++ ld r11,.Lchain(r12) ++ ld r12,.Lfunc(r12) ++ mtctr r12 ++ bctr ++.Lfunc = .-trampoline_initial ++ .quad 0 /* will be replaced with function address */ ++.Lchain = .-trampoline_initial ++ .quad 0 /* will be replaced with static chain */ ++ ++trampoline_size = .-trampoline_initial ++ .size trampoline_initial,trampoline_size ++ ++ ++/* R3 = stack address to store trampoline */ ++/* R4 = length of trampoline area */ ++/* R5 = function address */ ++/* R6 = static chain */ ++ ++ .pushsection ".toc","aw" ++.LC0: ++ .quad trampoline_initial-8 ++ .popsection ++ ++FUNC_START(__trampoline_setup) ++ addis 7,2,.LC0@toc@ha ++ ld 7,.LC0@toc@l(7) /* trampoline address -8 */ ++ ++ li r8,trampoline_size /* verify that the trampoline is big enough */ ++ cmpw cr1,r8,r4 ++ srwi r4,r4,3 /* # doublewords to move */ ++ addi r9,r3,-8 /* adjust pointer for stdu */ ++ mtctr r4 ++ blt cr1,.Labort ++ ++ /* Copy the instructions to the stack */ ++.Lmove: ++ ldu r10,8(r7) ++ stdu r10,8(r9) ++ bdnz .Lmove ++ ++ /* Store correct function and static chain */ ++ std r5,.Lfunc(r3) ++ std r6,.Lchain(r3) ++ ++ /* Now flush both caches */ ++ mtctr r4 ++.Lcache: ++ icbi 0,r3 ++ dcbf 0,r3 ++ addi r3,r3,8 ++ bdnz .Lcache ++ ++ /* Finally synchronize things & return */ ++ sync ++ isync ++ blr ++ ++.Labort: ++ bl JUMP_TARGET(abort) ++ nop ++FUNC_END(__trampoline_setup) ++ + #endif +--- a/src/libgcc/config/rs6000/linux-unwind.h ++++ b/src/libgcc/config/rs6000/linux-unwind.h +@@ -24,9 +24,19 @@ + + #define R_LR 65 + #define R_CR2 70 ++#define R_CR3 71 ++#define R_CR4 72 + #define R_VR0 77 + #define R_VRSAVE 109 + ++#ifdef __powerpc64__ ++#if _CALL_ELF == 2 ++#define TOC_SAVE_SLOT 24 ++#else ++#define TOC_SAVE_SLOT 40 ++#endif ++#endif ++ + struct gcc_vregs + { + __attribute__ ((vector_size (16))) int vr[32]; +@@ -107,6 +117,8 @@ + } + else if (pc[1] == 0x380000AC) + { ++#if _CALL_ELF != 2 ++ /* These old kernel versions never supported ELFv2. */ + /* This works for 2.4 kernels, but not for 2.6 kernels with vdso + because pc isn't pointing into the stack. Can be removed when + no one is running 2.4.19 or 2.4.20, the first two ppc64 +@@ -121,6 +133,7 @@ + if ((long) frame24->puc != -21 * 8) + return frame24->puc->regs; + else ++#endif + { + /* This works for 2.4.21 and later kernels. */ + struct rt_sigframe { +@@ -185,6 +198,7 @@ + { + struct gcc_regs *regs = get_regs (context); + struct gcc_vregs *vregs; ++ long cr_offset; + long new_cfa; + int i; + +@@ -206,11 +220,21 @@ + fs->regs.reg[i].loc.offset = (long) ®s->gpr[i] - new_cfa; + } + ++ /* The CR is saved in the low 32 bits of regs->ccr. */ ++ cr_offset = (long) ®s->ccr - new_cfa; ++#ifndef __LITTLE_ENDIAN__ ++ cr_offset += sizeof (long) - 4; ++#endif ++ /* In the ELFv1 ABI, CR2 stands in for the whole CR. */ + fs->regs.reg[R_CR2].how = REG_SAVED_OFFSET; +- /* CR? regs are always 32-bit and PPC is big-endian, so in 64-bit +- libgcc loc.offset needs to point to the low 32 bits of regs->ccr. */ +- fs->regs.reg[R_CR2].loc.offset = (long) ®s->ccr - new_cfa +- + sizeof (long) - 4; ++ fs->regs.reg[R_CR2].loc.offset = cr_offset; ++#if _CALL_ELF == 2 ++ /* In the ELFv2 ABI, every CR field has a separate CFI entry. */ ++ fs->regs.reg[R_CR3].how = REG_SAVED_OFFSET; ++ fs->regs.reg[R_CR3].loc.offset = cr_offset; ++ fs->regs.reg[R_CR4].how = REG_SAVED_OFFSET; ++ fs->regs.reg[R_CR4].loc.offset = cr_offset; ++#endif + + fs->regs.reg[R_LR].how = REG_SAVED_OFFSET; + fs->regs.reg[R_LR].loc.offset = (long) ®s->link - new_cfa; +@@ -294,9 +318,13 @@ + figure out if it was saved. The big problem here is that the + code that does the save/restore is generated by the linker, so + we have no good way to determine at compile time what to do. */ +- if (pc[0] == 0xF8410028 ++ if (pc[0] == 0xF8410000 + TOC_SAVE_SLOT ++#if _CALL_ELF != 2 ++ /* The ELFv2 linker never generates the old PLT stub form. */ + || ((pc[0] & 0xFFFF0000) == 0x3D820000 +- && pc[1] == 0xF8410028)) ++ && pc[1] == 0xF8410000 + TOC_SAVE_SLOT) ++#endif ++ ) + { + /* We are in a plt call stub or r2 adjusting long branch stub, + before r2 has been saved. Keep REG_UNSAVED. */ +@@ -305,18 +333,21 @@ + { + unsigned int *insn + = (unsigned int *) _Unwind_GetGR (context, R_LR); +- if (insn && *insn == 0xE8410028) +- _Unwind_SetGRPtr (context, 2, context->cfa + 40); ++ if (insn && *insn == 0xE8410000 + TOC_SAVE_SLOT) ++ _Unwind_SetGRPtr (context, 2, context->cfa + TOC_SAVE_SLOT); ++#if _CALL_ELF != 2 ++ /* ELFv2 does not use this function pointer call sequence. */ + else if (pc[0] == 0x4E800421 +- && pc[1] == 0xE8410028) ++ && pc[1] == 0xE8410000 + TOC_SAVE_SLOT) + { + /* We are at the bctrl instruction in a call via function + pointer. gcc always emits the load of the new R2 just + before the bctrl so this is the first and only place + we need to use the stored R2. */ + _Unwind_Word sp = _Unwind_GetGR (context, 1); +- _Unwind_SetGRPtr (context, 2, (void *)(sp + 40)); ++ _Unwind_SetGRPtr (context, 2, (void *)(sp + TOC_SAVE_SLOT)); + } ++#endif + } + } + #endif +--- a/src/libgcc/ChangeLog.ibm ++++ b/src/libgcc/ChangeLog.ibm +@@ -0,0 +1,38 @@ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204808: ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * config/rs6000/linux-unwind.h (TOC_SAVE_SLOT): Define. ++ (frob_update_context): Use it. ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * config/rs6000/tramp.S [__powerpc64__ && _CALL_ELF == 2]: ++ (trampoline_initial): Provide ELFv2 variant. ++ (__trampoline_setup): Likewise. ++ ++ * config/rs6000/linux-unwind.h (frob_update_context): Do not ++ check for AIX indirect function call sequence if _CALL_ELF == 2. ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * config/rs6000/linux-unwind.h (get_regs): Do not support ++ old kernel versions if _CALL_ELF == 2. ++ (frob_update_context): Do not support PLT stub variants only ++ generated by old linkers if _CALL_ELF == 2. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204800: ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Correct ++ location of CR save area for 64-bit little-endian systems. ++ +--- a/src/config.guess ++++ b/src/config.guess +@@ -1,10 +1,8 @@ + #! /bin/sh + # Attempt to guess a canonical system name. +-# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, +-# 2011, 2012, 2013 Free Software Foundation, Inc. ++# Copyright 1992-2013 Free Software Foundation, Inc. + +-timestamp='2012-12-30' ++timestamp='2013-06-10' + + # This file is free software; you can redistribute it and/or modify it + # under the terms of the GNU General Public License as published by +@@ -52,9 +50,7 @@ + GNU config.guess ($timestamp) + + Originally written by Per Bothner. +-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, +-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, +-2012, 2013 Free Software Foundation, Inc. ++Copyright 1992-2013 Free Software Foundation, Inc. + + This is free software; see the source for copying conditions. There is NO + warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." +@@ -136,6 +132,27 @@ + UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown + UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + ++case "${UNAME_SYSTEM}" in ++Linux|GNU|GNU/*) ++ # If the system lacks a compiler, then just pick glibc. ++ # We could probably try harder. ++ LIBC=gnu ++ ++ eval $set_cc_for_build ++ cat <<-EOF > $dummy.c ++ #include ++ #if defined(__UCLIBC__) ++ LIBC=uclibc ++ #elif defined(__dietlibc__) ++ LIBC=dietlibc ++ #else ++ LIBC=gnu ++ #endif ++ EOF ++ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` ++ ;; ++esac ++ + # Note: order is significant - the case branches are not exclusive. + + case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in +@@ -857,21 +874,21 @@ + exit ;; + *:GNU:*:*) + # the GNU system +- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` ++ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland +- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu ++ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} + exit ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit ;; + aarch64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + aarch64_be:Linux:*:*) + UNAME_MACHINE=aarch64_be +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in +@@ -884,59 +901,54 @@ + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep -q ld.so.1 +- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi +- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} ++ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; ++ arc:Linux:*:* | arceb:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; + arm*:Linux:*:*) + eval $set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_EABI__ + then +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + else + if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_PCS_VFP + then +- echo ${UNAME_MACHINE}-unknown-linux-gnueabi ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi + else +- echo ${UNAME_MACHINE}-unknown-linux-gnueabihf ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf + fi + fi + exit ;; + avr32*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + cris:Linux:*:*) +- echo ${UNAME_MACHINE}-axis-linux-gnu ++ echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + crisv32:Linux:*:*) +- echo ${UNAME_MACHINE}-axis-linux-gnu ++ echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + frv:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + hexagon:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:Linux:*:*) +- LIBC=gnu +- eval $set_cc_for_build +- sed 's/^ //' << EOF >$dummy.c +- #ifdef __dietlibc__ +- LIBC=dietlibc +- #endif +-EOF +- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` +- echo "${UNAME_MACHINE}-pc-linux-${LIBC}" ++ echo ${UNAME_MACHINE}-pc-linux-${LIBC} + exit ;; + ia64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m32r*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m68*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + mips:Linux:*:* | mips64:Linux:*:*) + eval $set_cc_for_build +@@ -955,54 +967,63 @@ + #endif + EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` +- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ++ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } + ;; ++ or1k:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; + or32:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + padre:Linux:*:*) +- echo sparc-unknown-linux-gnu ++ echo sparc-unknown-linux-${LIBC} + exit ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) +- echo hppa64-unknown-linux-gnu ++ echo hppa64-unknown-linux-${LIBC} + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in +- PA7*) echo hppa1.1-unknown-linux-gnu ;; +- PA8*) echo hppa2.0-unknown-linux-gnu ;; +- *) echo hppa-unknown-linux-gnu ;; ++ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; ++ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; ++ *) echo hppa-unknown-linux-${LIBC} ;; + esac + exit ;; + ppc64:Linux:*:*) +- echo powerpc64-unknown-linux-gnu ++ echo powerpc64-unknown-linux-${LIBC} + exit ;; + ppc:Linux:*:*) +- echo powerpc-unknown-linux-gnu ++ echo powerpc-unknown-linux-${LIBC} + exit ;; ++ ppc64le:Linux:*:*) ++ echo powerpc64le-unknown-linux-${LIBC} ++ exit ;; ++ ppcle:Linux:*:*) ++ echo powerpcle-unknown-linux-${LIBC} ++ exit ;; + s390:Linux:*:* | s390x:Linux:*:*) +- echo ${UNAME_MACHINE}-ibm-linux ++ echo ${UNAME_MACHINE}-ibm-linux-${LIBC} + exit ;; + sh64*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sh*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + tile*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + vax:Linux:*:*) +- echo ${UNAME_MACHINE}-dec-linux-gnu ++ echo ${UNAME_MACHINE}-dec-linux-${LIBC} + exit ;; + x86_64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + xtensa*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. +@@ -1235,19 +1256,21 @@ + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown +- case $UNAME_PROCESSOR in +- i386) +- eval $set_cc_for_build +- if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then +- if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ +- (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ +- grep IS_64BIT_ARCH >/dev/null +- then +- UNAME_PROCESSOR="x86_64" +- fi +- fi ;; +- unknown) UNAME_PROCESSOR=powerpc ;; +- esac ++ eval $set_cc_for_build ++ if test "$UNAME_PROCESSOR" = unknown ; then ++ UNAME_PROCESSOR=powerpc ++ fi ++ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then ++ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ ++ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ ++ grep IS_64BIT_ARCH >/dev/null ++ then ++ case $UNAME_PROCESSOR in ++ i386) UNAME_PROCESSOR=x86_64 ;; ++ powerpc) UNAME_PROCESSOR=powerpc64 ;; ++ esac ++ fi ++ fi + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) +--- a/src/gcc/configure ++++ b/src/gcc/configure +@@ -13590,7 +13590,7 @@ + rm -rf conftest* + ;; + +-x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ ++x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ + s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext +@@ -13615,7 +13615,10 @@ + ;; + esac + ;; +- ppc64-*linux*|powerpc64-*linux*) ++ powerpc64le-*linux*) ++ LD="${LD-ld} -m elf32lppclinux" ++ ;; ++ powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) +@@ -13634,7 +13637,10 @@ + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; +- ppc*-*linux*|powerpc*-*linux*) ++ powerpcle-*linux*) ++ LD="${LD-ld} -m elf64lppc" ++ ;; ++ powerpc-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) +@@ -17828,7 +17834,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 17831 "configure" ++#line 17837 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +@@ -17934,7 +17940,7 @@ + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +-#line 17937 "configure" ++#line 17943 "configure" + #include "confdefs.h" + + #if HAVE_DLFCN_H +--- a/src/gcc/builtins.c ++++ b/src/gcc/builtins.c +@@ -5846,6 +5846,9 @@ + switch (fcode) + { + CASE_FLT_FN (BUILT_IN_FABS): ++ case BUILT_IN_FABSD32: ++ case BUILT_IN_FABSD64: ++ case BUILT_IN_FABSD128: + target = expand_builtin_fabs (exp, target, subtarget); + if (target) + return target; +@@ -10298,6 +10301,9 @@ + return fold_builtin_strlen (loc, type, arg0); + + CASE_FLT_FN (BUILT_IN_FABS): ++ case BUILT_IN_FABSD32: ++ case BUILT_IN_FABSD64: ++ case BUILT_IN_FABSD128: + return fold_builtin_fabs (loc, arg0, type); + + case BUILT_IN_ABS: +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c +@@ -5,8 +5,7 @@ + /* { dg-final { scan-assembler-times "fabs" 3 } } */ + /* { dg-final { scan-assembler-times "fnabs" 3 } } */ + /* { dg-final { scan-assembler-times "fsel" 3 } } */ +-/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */ +-/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */ ++/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */ + + /* fabs/fnabs/fsel */ + double normal1 (double a, double b) { return __builtin_copysign (a, b); } +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c +@@ -0,0 +1,65 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++#ifndef TYPE ++#define TYPE long long ++#endif ++ ++#ifndef SIGN_TYPE ++#define SIGN_TYPE signed TYPE ++#endif ++ ++#ifndef UNS_TYPE ++#define UNS_TYPE unsigned TYPE ++#endif ++ ++typedef vector SIGN_TYPE v_sign; ++typedef vector UNS_TYPE v_uns; ++ ++v_sign sign_add (v_sign a, v_sign b) ++{ ++ return a + b; ++} ++ ++v_sign sign_sub (v_sign a, v_sign b) ++{ ++ return a - b; ++} ++ ++v_sign sign_shift_left (v_sign a, v_sign b) ++{ ++ return a << b; ++} ++ ++v_sign sign_shift_right (v_sign a, v_sign b) ++{ ++ return a >> b; ++} ++ ++v_uns uns_add (v_uns a, v_uns b) ++{ ++ return a + b; ++} ++ ++v_uns uns_sub (v_uns a, v_uns b) ++{ ++ return a - b; ++} ++ ++v_uns uns_shift_left (v_uns a, v_uns b) ++{ ++ return a << b; ++} ++ ++v_uns uns_shift_right (v_uns a, v_uns b) ++{ ++ return a >> b; ++} ++ ++/* { dg-final { scan-assembler-times "vaddudm" 2 } } */ ++/* { dg-final { scan-assembler-times "vsubudm" 2 } } */ ++/* { dg-final { scan-assembler-times "vsld" 2 } } */ ++/* { dg-final { scan-assembler-times "vsrad" 1 } } */ ++/* { dg-final { scan-assembler-times "vsrd" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c +@@ -0,0 +1,200 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++#ifndef ALIGN ++#define ALIGN 32 ++#endif ++ ++#ifndef TYPE ++#define TYPE long long ++#endif ++ ++#ifndef SIGN_TYPE ++#define SIGN_TYPE signed TYPE ++#endif ++ ++#ifndef UNS_TYPE ++#define UNS_TYPE unsigned TYPE ++#endif ++ ++#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) ++ ++SIGN_TYPE sa[SIZE] ALIGN_ATTR; ++SIGN_TYPE sb[SIZE] ALIGN_ATTR; ++SIGN_TYPE sc[SIZE] ALIGN_ATTR; ++ ++UNS_TYPE ua[SIZE] ALIGN_ATTR; ++UNS_TYPE ub[SIZE] ALIGN_ATTR; ++UNS_TYPE uc[SIZE] ALIGN_ATTR; ++ ++void ++sign_add (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = sb[i] + sc[i]; ++} ++ ++void ++sign_sub (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = sb[i] - sc[i]; ++} ++ ++void ++sign_shift_left (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = sb[i] << sc[i]; ++} ++ ++void ++sign_shift_right (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = sb[i] >> sc[i]; ++} ++ ++void ++sign_max (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = (sb[i] > sc[i]) ? sb[i] : sc[i]; ++} ++ ++void ++sign_min (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = (sb[i] < sc[i]) ? sb[i] : sc[i]; ++} ++ ++void ++sign_abs (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = (sb[i] < 0) ? -sb[i] : sb[i]; /* xor, vsubudm, vmaxsd. */ ++} ++ ++void ++sign_eq (SIGN_TYPE val1, SIGN_TYPE val2) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = (sb[i] == sc[i]) ? val1 : val2; ++} ++ ++void ++sign_lt (SIGN_TYPE val1, SIGN_TYPE val2) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ sa[i] = (sb[i] < sc[i]) ? val1 : val2; ++} ++ ++void ++uns_add (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = ub[i] + uc[i]; ++} ++ ++void ++uns_sub (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = ub[i] - uc[i]; ++} ++ ++void ++uns_shift_left (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = ub[i] << uc[i]; ++} ++ ++void ++uns_shift_right (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = ub[i] >> uc[i]; ++} ++ ++void ++uns_max (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = (ub[i] > uc[i]) ? ub[i] : uc[i]; ++} ++ ++void ++uns_min (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = (ub[i] < uc[i]) ? ub[i] : uc[i]; ++} ++ ++void ++uns_eq (UNS_TYPE val1, UNS_TYPE val2) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = (ub[i] == uc[i]) ? val1 : val2; ++} ++ ++void ++uns_lt (UNS_TYPE val1, UNS_TYPE val2) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ ua[i] = (ub[i] < uc[i]) ? val1 : val2; ++} ++ ++/* { dg-final { scan-assembler-times "\[\t \]vaddudm\[\t \]" 2 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vsubudm\[\t \]" 3 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vmaxsd\[\t \]" 2 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vmaxud\[\t \]" 1 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vminsd\[\t \]" 1 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vminud\[\t \]" 1 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vsld\[\t \]" 2 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vsrad\[\t \]" 1 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vsrd\[\t \]" 1 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */ ++/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/pr57744.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr57744.c +@@ -0,0 +1,39 @@ ++/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O3" } */ ++ ++void abort (void); ++ ++typedef unsigned U_16 __attribute__((mode(TI))); ++ ++extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int) ++ __attribute__((__noinline__)); ++ ++/* PR 57744: lqarx/stqcx needs even/odd register pairs. The assembler will ++ complain if the compiler gets an odd/even register pair. Create a function ++ which has the 16 byte compare and exchange instructions, but don't actually ++ execute it, so that we can detect these failures on older machines. */ ++ ++int ++libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval, ++ int smodel, int fmodel __attribute__((unused))) ++{ ++ if (((smodel) == 0)) ++ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0); ++ else if (((smodel) != 5)) ++ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0); ++ else ++ return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0); ++} ++ ++U_16 a = 1, b = 1, c = -2; ++volatile int do_test = 0; ++ ++int main (void) ++{ ++ if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0)) ++ abort (); ++ ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-1.c +@@ -3,8 +3,8 @@ + /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */ + /* { dg-final { scan-assembler-times "frsqrte" 2 } } */ + /* { dg-final { scan-assembler-times "fmsub" 2 } } */ +-/* { dg-final { scan-assembler-times "fmul" 8 } } */ +-/* { dg-final { scan-assembler-times "fnmsub" 4 } } */ ++/* { dg-final { scan-assembler-times "fmul" 6 } } */ ++/* { dg-final { scan-assembler-times "fnmsub" 3 } } */ + + double + rsqrt_d (double a) +--- a/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c +@@ -11,7 +11,11 @@ + int i[2]; + } ud; + ud.ll = in; ++#ifdef __LITTLE_ENDIAN__ ++ return ud.i[1]; ++#else + return ud.i[0]; ++#endif + } + + int main() +--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p8.c +@@ -0,0 +1,32 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-O2 -mcpu=power8" } */ ++/* { dg-final { scan-assembler-not "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlnand " } } */ ++ ++#ifndef TYPE ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++ ++#include "bool2.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */ ++/* { dg-final { scan-assembler "mffgpr" } } */ ++/* { dg-final { scan-assembler "mftgpr" } } */ ++ ++/* Test that we generate the instructions to move between the GPR and FPR ++ registers under power6x. */ ++ ++extern long return_long (void); ++extern double return_double (void); ++ ++double return_double2 (void) ++{ ++ return (double) return_long (); ++} ++ ++long return_long2 (void) ++{ ++ return (long) return_double (); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler "mtvsrd" } } */ ++/* { dg-final { scan-assembler "mfvsrd" } } */ ++ ++/* Check code generation for direct move for vector types. */ ++ ++#define TYPE vector int ++#define VSX_REG_ATTR "wa" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-av.c +@@ -0,0 +1,32 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-O2 -mcpu=power6 -maltivec" } */ ++/* { dg-final { scan-assembler-not "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */ ++/* { dg-final { scan-assembler "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler "\[ \t\]vandc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ ++ ++#ifndef TYPE ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++ ++#include "bool2.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/pr43154.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr43154.c +@@ -1,5 +1,6 @@ + /* { dg-do compile { target { powerpc*-*-* } } } */ + /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ + /* { dg-require-effective-target powerpc_vsx_ok } */ + /* { dg-options "-O2 -mcpu=power7" } */ + +--- a/src/gcc/testsuite/gcc.target/powerpc/pr59054.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr59054.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O0 -m64" } */ ++ ++long foo (void) { return 0; } ++ ++/* { dg-final { scan-assembler-not "xxlor" } } */ ++/* { dg-final { scan-assembler-not "stfd" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +@@ -0,0 +1,204 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++#include ++ ++typedef vector long long v_sign; ++typedef vector unsigned long long v_uns; ++typedef vector bool long long v_bool; ++ ++v_sign sign_add_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vaddudm (a, b); ++} ++ ++v_sign sign_add_2 (v_sign a, v_sign b) ++{ ++ return vec_add (a, b); ++} ++ ++v_sign sign_add_3 (v_sign a, v_sign b) ++{ ++ return vec_vaddudm (a, b); ++} ++ ++v_sign sign_sub_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vsubudm (a, b); ++} ++ ++v_sign sign_sub_2 (v_sign a, v_sign b) ++{ ++ return vec_sub (a, b); ++} ++ ++ ++v_sign sign_sub_3 (v_sign a, v_sign b) ++{ ++ return vec_vsubudm (a, b); ++} ++ ++v_sign sign_min_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vminsd (a, b); ++} ++ ++v_sign sign_min_2 (v_sign a, v_sign b) ++{ ++ return vec_min (a, b); ++} ++ ++v_sign sign_min_3 (v_sign a, v_sign b) ++{ ++ return vec_vminsd (a, b); ++} ++ ++v_sign sign_max_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vmaxsd (a, b); ++} ++ ++v_sign sign_max_2 (v_sign a, v_sign b) ++{ ++ return vec_max (a, b); ++} ++ ++v_sign sign_max_3 (v_sign a, v_sign b) ++{ ++ return vec_vmaxsd (a, b); ++} ++ ++v_sign sign_abs (v_sign a) ++{ ++ return vec_abs (a); /* xor, vsubudm, vmaxsd. */ ++} ++ ++v_bool sign_eq (v_sign a, v_sign b) ++{ ++ return vec_cmpeq (a, b); ++} ++ ++v_bool sign_lt (v_sign a, v_sign b) ++{ ++ return vec_cmplt (a, b); ++} ++ ++v_uns uns_add_2 (v_uns a, v_uns b) ++{ ++ return vec_add (a, b); ++} ++ ++v_uns uns_add_3 (v_uns a, v_uns b) ++{ ++ return vec_vaddudm (a, b); ++} ++ ++v_uns uns_sub_2 (v_uns a, v_uns b) ++{ ++ return vec_sub (a, b); ++} ++ ++v_uns uns_sub_3 (v_uns a, v_uns b) ++{ ++ return vec_vsubudm (a, b); ++} ++ ++v_uns uns_min_2 (v_uns a, v_uns b) ++{ ++ return vec_min (a, b); ++} ++ ++v_uns uns_min_3 (v_uns a, v_uns b) ++{ ++ return vec_vminud (a, b); ++} ++ ++v_uns uns_max_2 (v_uns a, v_uns b) ++{ ++ return vec_max (a, b); ++} ++ ++v_uns uns_max_3 (v_uns a, v_uns b) ++{ ++ return vec_vmaxud (a, b); ++} ++ ++v_bool uns_eq (v_uns a, v_uns b) ++{ ++ return vec_cmpeq (a, b); ++} ++ ++v_bool uns_lt (v_uns a, v_uns b) ++{ ++ return vec_cmplt (a, b); ++} ++ ++v_sign sign_rl_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vrld (a, b); ++} ++ ++v_sign sign_rl_2 (v_sign a, v_uns b) ++{ ++ return vec_rl (a, b); ++} ++ ++v_uns uns_rl_2 (v_uns a, v_uns b) ++{ ++ return vec_rl (a, b); ++} ++ ++v_sign sign_sl_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vsld (a, b); ++} ++ ++v_sign sign_sl_2 (v_sign a, v_uns b) ++{ ++ return vec_sl (a, b); ++} ++ ++v_sign sign_sl_3 (v_sign a, v_uns b) ++{ ++ return vec_vsld (a, b); ++} ++ ++v_uns uns_sl_2 (v_uns a, v_uns b) ++{ ++ return vec_sl (a, b); ++} ++ ++v_uns uns_sl_3 (v_uns a, v_uns b) ++{ ++ return vec_vsld (a, b); ++} ++ ++v_sign sign_sra_1 (v_sign a, v_sign b) ++{ ++ return __builtin_altivec_vsrad (a, b); ++} ++ ++v_sign sign_sra_2 (v_sign a, v_uns b) ++{ ++ return vec_sra (a, b); ++} ++ ++v_sign sign_sra_3 (v_sign a, v_uns b) ++{ ++ return vec_vsrad (a, b); ++} ++ ++/* { dg-final { scan-assembler-times "vaddudm" 5 } } */ ++/* { dg-final { scan-assembler-times "vsubudm" 6 } } */ ++/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */ ++/* { dg-final { scan-assembler-times "vminsd" 3 } } */ ++/* { dg-final { scan-assembler-times "vmaxud" 2 } } */ ++/* { dg-final { scan-assembler-times "vminud" 2 } } */ ++/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */ ++/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */ ++/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */ ++/* { dg-final { scan-assembler-times "vrld" 3 } } */ ++/* { dg-final { scan-assembler-times "vsld" 5 } } */ ++/* { dg-final { scan-assembler-times "vsrad" 3 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c +@@ -0,0 +1,30 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */ ++ ++#include ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++#ifndef ALIGN ++#define ALIGN 32 ++#endif ++ ++#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) ++ ++long long sign_ll[SIZE] ALIGN_ATTR; ++int sign_i [SIZE] ALIGN_ATTR; ++ ++void copy_int_to_long_long (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < SIZE; i++) ++ sign_ll[i] = sign_i[i]; ++} ++ ++/* { dg-final { scan-assembler "vupkhsw" } } */ ++/* { dg-final { scan-assembler "vupklsw" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ ++/* { dg-options "-O -maltivec -mno-vsx" } */ ++ ++typedef unsigned char V __attribute__((vector_size(16))); ++ ++V p2(V x, V y) ++{ ++ return __builtin_shuffle(x, y, ++ (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 }); ++ ++} ++ ++V p4(V x, V y) ++{ ++ return __builtin_shuffle(x, y, ++ (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 }); ++} ++ ++/* { dg-final { scan-assembler-not "vperm" } } */ ++/* { dg-final { scan-assembler "vpkuhum" } } */ ++/* { dg-final { scan-assembler "vpkuwum" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-1.c +@@ -0,0 +1,78 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -m64 -O1" } */ ++ ++enum typecode ++{ ++ QIcode, QUcode, HIcode, HUcode, SIcode, SUcode, DIcode, DUcode, SFcode, ++ DFcode, XFcode, Pcode, Tcode, LAST_AND_UNUSED_TYPECODE ++}; ++enum bytecode_opcode ++{ ++ neverneverland, drop, duplicate, over, setstackSI, adjstackSI, constQI, ++ constHI, constSI, constDI, constSF, constDF, constXF, constP, loadQI, ++ loadHI, loadSI, loadDI, loadSF, loadDF, loadXF, loadP, storeQI, storeHI, ++ storeSI, storeDI, storeSF, storeDF, storeXF, storeP, storeBLK, clearBLK, ++ addconstPSI, newlocalSI, localP, argP, convertQIHI, convertHISI, ++ convertSIDI, convertQISI, convertQUHU, convertHUSU, convertSUDU, ++ convertQUSU, convertSFDF, convertDFXF, convertHIQI, convertSIHI, ++ convertDISI, convertSIQI, convertSUQU, convertDFSF, convertXFDF, ++ convertSISF, convertSIDF, convertSIXF, convertSUSF, convertSUDF, ++ convertSUXF, convertDISF, convertDIDF, convertDIXF, convertDUSF, ++ convertDUDF, convertDUXF, convertSFSI, convertDFSI, convertXFSI, ++ convertSFSU, convertDFSU, convertXFSU, convertSFDI, convertDFDI, ++ convertXFDI, convertSFDU, convertDFDU, convertXFDU, convertPSI, ++ convertSIP, convertSIT, convertDIT, convertSFT, convertDFT, convertXFT, ++ convertPT, zxloadBI, sxloadBI, sstoreBI, addSI, addDI, addSF, addDF, ++ addXF, addPSI, subSI, subDI, subSF, subDF, subXF, subPP, mulSI, mulDI, ++ mulSU, mulDU, mulSF, mulDF, mulXF, divSI, divDI, divSU, divDU, divSF, ++ divDF, divXF, modSI, modDI, modSU, modDU, andSI, andDI, iorSI, iorDI, ++ xorSI, xorDI, lshiftSI, lshiftSU, lshiftDI, lshiftDU, rshiftSI, rshiftSU, ++ rshiftDI, rshiftDU, ltSI, ltSU, ltDI, ltDU, ltSF, ltDF, ltXF, ltP, leSI, ++ leSU, leDI, leDU, leSF, leDF, leXF, leP, geSI, geSU, geDI, geDU, geSF, ++ geDF, geXF, geP, gtSI, gtSU, gtDI, gtDU, gtSF, gtDF, gtXF, gtP, eqSI, ++ eqDI, eqSF, eqDF, eqXF, eqP, neSI, neDI, neSF, neDF, neXF, neP, negSI, ++ negDI, negSF, negDF, negXF, notSI, notDI, notT, predecQI, predecHI, ++ predecSI, predecDI, predecP, predecSF, predecDF, predecXF, predecBI, ++ preincQI, preincHI, preincSI, preincDI, preincP, preincSF, preincDF, ++ preincXF, preincBI, postdecQI, postdecHI, postdecSI, postdecDI, postdecP, ++ postdecSF, postdecDF, postdecXF, postdecBI, postincQI, postincHI, ++ postincSI, postincDI, postincP, postincSF, postincDF, postincXF, ++ postincBI, xjumpif, xjumpifnot, jump, jumpP, caseSI, caseSU, caseDI, ++ caseDU, call, returnP, ret, linenote, LAST_AND_UNUSED_OPCODE ++}; ++struct binary_operator ++{ ++ enum bytecode_opcode opcode; ++ enum typecode arg0; ++}; ++static struct conversion_recipe ++{ ++ unsigned char *opcodes; ++ int cost; ++} ++conversion_recipe[((int) LAST_AND_UNUSED_TYPECODE)][((int) ++ LAST_AND_UNUSED_TYPECODE)]; ++static struct conversion_recipe ++deduce_conversion (from, to) ++ enum typecode from, to; ++{ ++ (conversion_recipe[(int) from][(int) to]. ++ opcodes ? 0 : (conversion_recipe[(int) from][(int) to] = ++ deduce_conversion (from, to), 0)); ++} ++ ++void ++bc_expand_binary_operation (optab, resulttype, arg0, arg1) ++ struct binary_operator optab[]; ++{ ++ int i, besti, cost, bestcost; ++ enum typecode resultcode, arg0code; ++ for (i = 0; optab[i].opcode != -1; ++i) ++ { ++ (conversion_recipe[(int) arg0code][(int) optab[i].arg0]. ++ opcodes ? 0 : (conversion_recipe[(int) arg0code][(int) optab[i].arg0] = ++ deduce_conversion (arg0code, optab[i].arg0), 0)); ++ } ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-1.c +@@ -1,5 +1,6 @@ + /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ + /* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ + /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ + + int +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +@@ -0,0 +1,139 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */ ++ ++float abs_sf (float *p) ++{ ++ float f = *p; ++ __asm__ ("# reg %x0" : "+v" (f)); ++ return __builtin_fabsf (f); ++} ++ ++float nabs_sf (float *p) ++{ ++ float f = *p; ++ __asm__ ("# reg %x0" : "+v" (f)); ++ return - __builtin_fabsf (f); ++} ++ ++float neg_sf (float *p) ++{ ++ float f = *p; ++ __asm__ ("# reg %x0" : "+v" (f)); ++ return - f; ++} ++ ++float add_sf (float *p, float *q) ++{ ++ float f1 = *p; ++ float f2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); ++ return f1 + f2; ++} ++ ++float sub_sf (float *p, float *q) ++{ ++ float f1 = *p; ++ float f2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); ++ return f1 - f2; ++} ++ ++float mul_sf (float *p, float *q) ++{ ++ float f1 = *p; ++ float f2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); ++ return f1 * f2; ++} ++ ++float div_sf (float *p, float *q) ++{ ++ float f1 = *p; ++ float f2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); ++ return f1 / f2; ++} ++ ++float sqrt_sf (float *p) ++{ ++ float f = *p; ++ __asm__ ("# reg %x0" : "+v" (f)); ++ return __builtin_sqrtf (f); ++} ++ ++ ++double abs_df (double *p) ++{ ++ double d = *p; ++ __asm__ ("# reg %x0" : "+v" (d)); ++ return __builtin_fabs (d); ++} ++ ++double nabs_df (double *p) ++{ ++ double d = *p; ++ __asm__ ("# reg %x0" : "+v" (d)); ++ return - __builtin_fabs (d); ++} ++ ++double neg_df (double *p) ++{ ++ double d = *p; ++ __asm__ ("# reg %x0" : "+v" (d)); ++ return - d; ++} ++ ++double add_df (double *p, double *q) ++{ ++ double d1 = *p; ++ double d2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); ++ return d1 + d2; ++} ++ ++double sub_df (double *p, double *q) ++{ ++ double d1 = *p; ++ double d2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); ++ return d1 - d2; ++} ++ ++double mul_df (double *p, double *q) ++{ ++ double d1 = *p; ++ double d2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); ++ return d1 * d2; ++} ++ ++double div_df (double *p, double *q) ++{ ++ double d1 = *p; ++ double d2 = *q; ++ __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); ++ return d1 / d2; ++} ++ ++double sqrt_df (float *p) ++{ ++ double d = *p; ++ __asm__ ("# reg %x0" : "+v" (d)); ++ return __builtin_sqrt (d); ++} ++ ++/* { dg-final { scan-assembler "xsabsdp" } } */ ++/* { dg-final { scan-assembler "xsadddp" } } */ ++/* { dg-final { scan-assembler "xsaddsp" } } */ ++/* { dg-final { scan-assembler "xsdivdp" } } */ ++/* { dg-final { scan-assembler "xsdivsp" } } */ ++/* { dg-final { scan-assembler "xsmuldp" } } */ ++/* { dg-final { scan-assembler "xsmulsp" } } */ ++/* { dg-final { scan-assembler "xsnabsdp" } } */ ++/* { dg-final { scan-assembler "xsnegdp" } } */ ++/* { dg-final { scan-assembler "xssqrtdp" } } */ ++/* { dg-final { scan-assembler "xssqrtsp" } } */ ++/* { dg-final { scan-assembler "xssubdp" } } */ ++/* { dg-final { scan-assembler "xssubsp" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c +@@ -0,0 +1,13 @@ ++/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target p8vector_hw } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++/* Check whether we get the right bits for direct move at runtime. */ ++ ++#define TYPE vector int ++#define DO_MAIN ++#define VSX_REG_ATTR "wa" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p7.c +@@ -0,0 +1,37 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7" } */ ++/* { dg-final { scan-assembler "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ ++ ++/* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the ++ vector unit doesn't support these, so the appropriate combine patterns may ++ not be generated. */ ++ ++#ifndef TYPE ++#ifdef _ARCH_PPC64 ++#define TYPE __int128_t ++#else ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++#endif ++ ++#include "bool3.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c +@@ -0,0 +1,104 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */ ++ ++#include ++ ++typedef vector long long vll_sign; ++typedef vector unsigned long long vll_uns; ++typedef vector bool long long vll_bool; ++ ++typedef vector int vi_sign; ++typedef vector unsigned int vi_uns; ++typedef vector bool int vi_bool; ++ ++typedef vector short vs_sign; ++typedef vector unsigned short vs_uns; ++typedef vector bool short vs_bool; ++ ++typedef vector signed char vc_sign; ++typedef vector unsigned char vc_uns; ++typedef vector bool char vc_bool; ++ ++ ++vi_sign vi_pack_1 (vll_sign a, vll_sign b) ++{ ++ return __builtin_altivec_vpkudum (a, b); ++} ++ ++vi_sign vi_pack_2 (vll_sign a, vll_sign b) ++{ ++ return vec_pack (a, b); ++} ++ ++vi_sign vi_pack_3 (vll_sign a, vll_sign b) ++{ ++ return vec_vpkudum (a, b); ++} ++ ++vs_sign vs_pack_1 (vi_sign a, vi_sign b) ++{ ++ return __builtin_altivec_vpkuwum (a, b); ++} ++ ++vs_sign vs_pack_2 (vi_sign a, vi_sign b) ++{ ++ return vec_pack (a, b); ++} ++ ++vs_sign vs_pack_3 (vi_sign a, vi_sign b) ++{ ++ return vec_vpkuwum (a, b); ++} ++ ++vc_sign vc_pack_1 (vs_sign a, vs_sign b) ++{ ++ return __builtin_altivec_vpkuhum (a, b); ++} ++ ++vc_sign vc_pack_2 (vs_sign a, vs_sign b) ++{ ++ return vec_pack (a, b); ++} ++ ++vc_sign vc_pack_3 (vs_sign a, vs_sign b) ++{ ++ return vec_vpkuhum (a, b); ++} ++ ++vll_sign vll_unpack_hi_1 (vi_sign a) ++{ ++ return __builtin_altivec_vupkhsw (a); ++} ++ ++vll_sign vll_unpack_hi_2 (vi_sign a) ++{ ++ return vec_unpackh (a); ++} ++ ++vll_sign vll_unpack_hi_3 (vi_sign a) ++{ ++ return __builtin_vec_vupkhsw (a); ++} ++ ++vll_sign vll_unpack_lo_1 (vi_sign a) ++{ ++ return vec_vupklsw (a); ++} ++ ++vll_sign vll_unpack_lo_2 (vi_sign a) ++{ ++ return vec_unpackl (a); ++} ++ ++vll_sign vll_unpack_lo_3 (vi_sign a) ++{ ++ return vec_vupklsw (a); ++} ++ ++/* { dg-final { scan-assembler-times "vpkudum" 3 } } */ ++/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */ ++/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */ ++/* { dg-final { scan-assembler-times "vupklsw" 3 } } */ ++/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c +@@ -0,0 +1,29 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */ ++ ++#include ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++#ifndef ALIGN ++#define ALIGN 32 ++#endif ++ ++#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) ++ ++long long sign_ll[SIZE] ALIGN_ATTR; ++int sign_i [SIZE] ALIGN_ATTR; ++ ++void copy_long_long_to_int (void) ++{ ++ size_t i; ++ ++ for (i = 0; i < SIZE; i++) ++ sign_i[i] = sign_ll[i]; ++} ++ ++/* { dg-final { scan-assembler "vpkudum" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move.h ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move.h +@@ -0,0 +1,187 @@ ++/* Test functions for direct move support. */ ++ ++ ++#ifndef VSX_REG_ATTR ++#define VSX_REG_ATTR "wa" ++#endif ++ ++void __attribute__((__noinline__)) ++copy (TYPE *a, TYPE *b) ++{ ++ *b = *a; ++} ++ ++#ifndef NO_GPR ++void __attribute__((__noinline__)) ++load_gpr (TYPE *a, TYPE *b) ++{ ++ TYPE c = *a; ++ __asm__ ("# gpr, reg = %0" : "+b" (c)); ++ *b = c; ++} ++#endif ++ ++#ifndef NO_FPR ++void __attribute__((__noinline__)) ++load_fpr (TYPE *a, TYPE *b) ++{ ++ TYPE c = *a; ++ __asm__ ("# fpr, reg = %0" : "+d" (c)); ++ *b = c; ++} ++#endif ++ ++#ifndef NO_ALTIVEC ++void __attribute__((__noinline__)) ++load_altivec (TYPE *a, TYPE *b) ++{ ++ TYPE c = *a; ++ __asm__ ("# altivec, reg = %0" : "+v" (c)); ++ *b = c; ++} ++#endif ++ ++#ifndef NO_VSX ++void __attribute__((__noinline__)) ++load_vsx (TYPE *a, TYPE *b) ++{ ++ TYPE c = *a; ++ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c)); ++ *b = c; ++} ++#endif ++ ++#ifndef NO_GPR_TO_VSX ++void __attribute__((__noinline__)) ++load_gpr_to_vsx (TYPE *a, TYPE *b) ++{ ++ TYPE c = *a; ++ TYPE d; ++ __asm__ ("# gpr, reg = %0" : "+b" (c)); ++ d = c; ++ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d)); ++ *b = d; ++} ++#endif ++ ++#ifndef NO_VSX_TO_GPR ++void __attribute__((__noinline__)) ++load_vsx_to_gpr (TYPE *a, TYPE *b) ++{ ++ TYPE c = *a; ++ TYPE d; ++ __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c)); ++ d = c; ++ __asm__ ("# gpr, reg = %0" : "+b" (d)); ++ *b = d; ++} ++#endif ++ ++#ifdef DO_MAIN ++typedef void (fn_type (TYPE *, TYPE *)); ++ ++struct test_struct { ++ fn_type *func; ++ const char *name; ++}; ++ ++const struct test_struct test_functions[] = { ++ { copy, "copy" }, ++#ifndef NO_GPR ++ { load_gpr, "load_gpr" }, ++#endif ++#ifndef NO_FPR ++ { load_fpr, "load_fpr" }, ++#endif ++#ifndef NO_ALTIVEC ++ { load_altivec, "load_altivec" }, ++#endif ++#ifndef NO_VSX ++ { load_vsx, "load_vsx" }, ++#endif ++#ifndef NO_GPR_TO_VSX ++ { load_gpr_to_vsx, "load_gpr_to_vsx" }, ++#endif ++#ifndef NO_VSX_TO_GPR ++ { load_vsx_to_gpr, "load_vsx_to_gpr" }, ++#endif ++}; ++ ++/* Test a given value for each of the functions. */ ++void __attribute__((__noinline__)) ++test_value (TYPE a) ++{ ++ size_t i; ++ ++ for (i = 0; i < sizeof (test_functions) / sizeof (test_functions[0]); i++) ++ { ++ TYPE b; ++ ++ test_functions[i].func (&a, &b); ++ if (memcmp ((void *)&a, (void *)&b, sizeof (TYPE)) != 0) ++ abort (); ++ } ++} ++ ++/* Main program. */ ++int ++main (void) ++{ ++ size_t i; ++ long j; ++ union { ++ TYPE value; ++ unsigned char bytes[sizeof (TYPE)]; ++ } u; ++ ++#if IS_INT ++ TYPE value = (TYPE)-5; ++ for (i = 0; i < 12; i++) ++ { ++ test_value (value); ++ value++; ++ } ++ ++ for (i = 0; i < 8*sizeof (TYPE); i++) ++ test_value (((TYPE)1) << i); ++ ++#elif IS_UNS ++ TYPE value = (TYPE)0; ++ for (i = 0; i < 10; i++) ++ { ++ test_value (value); ++ test_value (~ value); ++ value++; ++ } ++ ++ for (i = 0; i < 8*sizeof (TYPE); i++) ++ test_value (((TYPE)1) << i); ++ ++#elif IS_FLOAT ++ TYPE value = (TYPE)-5; ++ for (i = 0; i < 12; i++) ++ { ++ test_value (value); ++ value++; ++ } ++ ++ test_value ((TYPE)3.1415926535); ++ test_value ((TYPE)1.23456); ++ test_value ((TYPE)(-0.0)); ++ test_value ((TYPE)NAN); ++ test_value ((TYPE)+INFINITY); ++ test_value ((TYPE)-INFINITY); ++#else ++ ++ for (j = 0; j < 10; j++) ++ { ++ for (i = 0; i < sizeof (TYPE); i++) ++ u.bytes[i] = (unsigned char) (random () >> 4); ++ ++ test_value (u.value); ++ } ++#endif ++ ++ return 0; ++} ++#endif +--- a/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/sd-vsx.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */ ++/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ ++/* { dg-final { scan-assembler-times "stfiwx" 1 } } */ ++/* { dg-final { scan-assembler-not "lfd" } } */ ++/* { dg-final { scan-assembler-not "stfd" } } */ ++/* { dg-final { scan-assembler-times "dctdp" 2 } } */ ++/* { dg-final { scan-assembler-times "dadd" 1 } } */ ++/* { dg-final { scan-assembler-times "drsp" 1 } } */ ++ ++/* Test that power7 can directly load/store SDmode variables without using a ++ bounce buffer. */ ++_Decimal32 a; ++ ++void inc_dec32 (void) ++{ ++ a += (_Decimal32) 1.0; ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr58673-2.c +@@ -0,0 +1,217 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O3 -m64 -funroll-loops" } */ ++ ++#include ++#include ++#include ++#include ++ ++typedef long unsigned int size_t; ++typedef struct _IO_FILE FILE; ++typedef float real; ++typedef real rvec[3]; ++typedef real matrix[3][3]; ++typedef real tensor[3][3]; ++enum ++{ ++ F_BONDS, F_G96BONDS, F_MORSE, F_CUBICBONDS, F_CONNBONDS, F_HARMONIC, ++ F_ANGLES, F_G96ANGLES, F_PDIHS, F_RBDIHS, F_IDIHS, F_LJ14, F_COUL14, F_LJ, ++ F_BHAM, F_LJLR, F_DISPCORR, F_SR, F_LR, F_WPOL, F_POSRES, F_DISRES, ++ F_DISRESVIOL, F_ORIRES, F_ORIRESDEV, F_ANGRES, F_ANGRESZ, F_SHAKE, ++ F_SHAKENC, F_SETTLE, F_DUMMY2, F_DUMMY3, F_DUMMY3FD, F_DUMMY3FAD, ++ F_DUMMY3OUT, F_DUMMY4FD, F_EQM, F_EPOT, F_EKIN, F_ETOT, F_TEMP, F_PRES, ++ F_DVDL, F_DVDLKIN, F_NRE ++}; ++typedef union ++{ ++ struct ++ { ++ } ++ bham; ++ struct ++ { ++ real rA, krA, rB, krB; ++ } ++ harmonic; ++} ++t_iparams; ++typedef struct ++{ ++ t_iparams *iparams; ++} ++t_idef; ++typedef struct ++{ ++} ++t_inputrec; ++typedef struct ++{ ++} ++t_commrec; ++typedef struct ++{ ++} ++t_forcerec; ++typedef struct ++{ ++} ++t_mdatoms; ++typedef struct ++{ ++} ++t_filenm; ++enum ++{ ++ eoPres, eoEpot, eoVir, eoDist, eoMu, eoForce, eoFx, eoFy, eoFz, eoPx, eoPy, ++ eoPz, eoPolarizability, eoDipole, eoObsNR, eoMemory = ++ eoObsNR, eoInter, eoUseVirial, eoNR ++}; ++extern char *eoNames[eoNR]; ++typedef struct ++{ ++ int bPrint; ++} ++t_coupl_LJ; ++typedef struct ++{ ++ int eObs; ++ t_iparams xi; ++} ++t_coupl_iparams; ++typedef struct ++{ ++ real act_value[eoObsNR]; ++ real av_value[eoObsNR]; ++ real ref_value[eoObsNR]; ++ int bObsUsed[eoObsNR]; ++ int nLJ, nBU, nQ, nIP; ++ t_coupl_LJ *tcLJ; ++} ++t_coupl_rec; ++static void ++pr_ff (t_coupl_rec * tcr, real time, t_idef * idef, t_commrec * cr, int nfile, ++ t_filenm fnm[]) ++{ ++ static FILE *prop; ++ static FILE **out = ((void *) 0); ++ static FILE **qq = ((void *) 0); ++ static FILE **ip = ((void *) 0); ++ char buf[256]; ++ char *leg[] = { ++ "C12", "C6" ++ }; ++ char **raleg; ++ int i, j, index; ++ if ((prop == ((void *) 0)) && (out == ((void *) 0)) && (qq == ((void *) 0)) ++ && (ip == ((void *) 0))) ++ { ++ for (i = j = 0; (i < eoObsNR); i++) ++ { ++ if (tcr->bObsUsed[i]) ++ { ++ raleg[j++] = ++ (__extension__ ++ (__builtin_constant_p (eoNames[i]) ++ && ((size_t) (const void *) ((eoNames[i]) + 1) - ++ (size_t) (const void *) (eoNames[i]) == ++ 1) ? (((const char *) (eoNames[i]))[0] == ++ '\0' ? (char *) calloc ((size_t) 1, ++ (size_t) 1) : ( ++ { ++ size_t ++ __len ++ = ++ strlen ++ (eoNames ++ [i]) ++ + ++ 1; ++ char ++ *__retval ++ = ++ (char ++ *) ++ malloc ++ (__len); ++ __retval;} ++ )): __strdup (eoNames[i]))); ++ raleg[j++] = ++ (__extension__ ++ (__builtin_constant_p (buf) ++ && ((size_t) (const void *) ((buf) + 1) - ++ (size_t) (const void *) (buf) == ++ 1) ? (((const char *) (buf))[0] == ++ '\0' ? (char *) calloc ((size_t) 1, ++ (size_t) 1) : ( ++ { ++ size_t ++ __len ++ = ++ strlen ++ (buf) ++ + ++ 1; ++ char ++ *__retval ++ = ++ (char ++ *) ++ malloc ++ (__len); ++ __retval;} ++ )): __strdup (buf))); ++ } ++ } ++ if (tcr->nLJ) ++ { ++ for (i = 0; (i < tcr->nLJ); i++) ++ { ++ if (tcr->tcLJ[i].bPrint) ++ { ++ xvgr_legend (out[i], (sizeof (leg) / sizeof ((leg)[0])), ++ leg); ++ } ++ } ++ } ++ } ++} ++ ++void ++do_coupling (FILE * log, int nfile, t_filenm fnm[], t_coupl_rec * tcr, real t, ++ int step, real ener[], t_forcerec * fr, t_inputrec * ir, ++ int bMaster, t_mdatoms * md, t_idef * idef, real mu_aver, ++ int nmols, t_commrec * cr, matrix box, tensor virial, ++ tensor pres, rvec mu_tot, rvec x[], rvec f[], int bDoIt) ++{ ++ int i, j, ati, atj, atnr2, type, ftype; ++ real deviation[eoObsNR], prdev[eoObsNR], epot0, dist, rmsf; ++ real ff6, ff12, ffa, ffb, ffc, ffq, factor, dt, mu_ind; ++ int bTest, bPrint; ++ t_coupl_iparams *tip; ++ if (bPrint) ++ { ++ pr_ff (tcr, t, idef, cr, nfile, fnm); ++ } ++ for (i = 0; (i < eoObsNR); i++) ++ { ++ deviation[i] = ++ calc_deviation (tcr->av_value[i], tcr->act_value[i], ++ tcr->ref_value[i]); ++ prdev[i] = tcr->ref_value[i] - tcr->act_value[i]; ++ } ++ if (bPrint) ++ pr_dev (tcr, t, prdev, cr, nfile, fnm); ++ for (i = 0; (i < atnr2); i++) ++ { ++ factor = dt * deviation[tip->eObs]; ++ switch (ftype) ++ { ++ case F_BONDS: ++ if (fabs (tip->xi.harmonic.krA) > 1.2e-38) ++ idef->iparams[type].harmonic.krA *= ++ (1 + factor / tip->xi.harmonic.krA); ++ } ++ } ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p7.c +@@ -0,0 +1,207 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O2" } */ ++/* { dg-final { scan-assembler-not "lbarx" } } */ ++/* { dg-final { scan-assembler-not "lharx" } } */ ++/* { dg-final { scan-assembler-times "lwarx" 18 } } */ ++/* { dg-final { scan-assembler-times "ldarx" 6 } } */ ++/* { dg-final { scan-assembler-not "lqarx" } } */ ++/* { dg-final { scan-assembler-not "stbcx" } } */ ++/* { dg-final { scan-assembler-not "sthcx" } } */ ++/* { dg-final { scan-assembler-times "stwcx" 18 } } */ ++/* { dg-final { scan-assembler-times "stdcx" 6 } } */ ++/* { dg-final { scan-assembler-not "stqcx" } } */ ++/* { dg-final { scan-assembler-times "bl __atomic" 6 } } */ ++/* { dg-final { scan-assembler-times "isync" 12 } } */ ++/* { dg-final { scan-assembler-times "lwsync" 8 } } */ ++/* { dg-final { scan-assembler-not "mtvsrd" } } */ ++/* { dg-final { scan-assembler-not "mtvsrwa" } } */ ++/* { dg-final { scan-assembler-not "mtvsrwz" } } */ ++/* { dg-final { scan-assembler-not "mfvsrd" } } */ ++/* { dg-final { scan-assembler-not "mfvsrwz" } } */ ++ ++/* Test for the byte atomic operations on power8 using lbarx/stbcx. */ ++char ++char_fetch_add_relaxed (char *ptr, int value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++char ++char_fetch_sub_consume (char *ptr, int value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++char ++char_fetch_and_acquire (char *ptr, int value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++char ++char_fetch_ior_release (char *ptr, int value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++char ++char_fetch_xor_acq_rel (char *ptr, int value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++char ++char_fetch_nand_seq_cst (char *ptr, int value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++/* Test for the half word atomic operations on power8 using lharx/sthcx. */ ++short ++short_fetch_add_relaxed (short *ptr, int value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++short ++short_fetch_sub_consume (short *ptr, int value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++short ++short_fetch_and_acquire (short *ptr, int value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++short ++short_fetch_ior_release (short *ptr, int value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++short ++short_fetch_xor_acq_rel (short *ptr, int value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++short ++short_fetch_nand_seq_cst (short *ptr, int value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++/* Test for the word atomic operations on power8 using lwarx/stwcx. */ ++int ++int_fetch_add_relaxed (int *ptr, int value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++int ++int_fetch_sub_consume (int *ptr, int value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++int ++int_fetch_and_acquire (int *ptr, int value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++int ++int_fetch_ior_release (int *ptr, int value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++int ++int_fetch_xor_acq_rel (int *ptr, int value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++int ++int_fetch_nand_seq_cst (int *ptr, int value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++/* Test for the double word atomic operations on power8 using ldarx/stdcx. */ ++long ++long_fetch_add_relaxed (long *ptr, long value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++long ++long_fetch_sub_consume (long *ptr, long value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++long ++long_fetch_and_acquire (long *ptr, long value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++long ++long_fetch_ior_release (long *ptr, long value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++long ++long_fetch_xor_acq_rel (long *ptr, long value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++long ++long_fetch_nand_seq_cst (long *ptr, long value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */ ++__int128_t ++quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++__int128_t ++quad_fetch_sub_consume (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++__int128_t ++quad_fetch_and_acquire (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++__int128_t ++quad_fetch_ior_release (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++__int128_t ++quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++__int128_t ++quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-3.c +@@ -1,14 +1,14 @@ + /* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ + /* { dg-require-effective-target powerpc_fprs } */ + /* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */ +-/* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */ ++/* { dg-final { scan-assembler-times "xsrsqrtedp\|frsqrte\ " 1 } } */ + /* { dg-final { scan-assembler-times "xsmsub.dp\|fmsub\ " 1 } } */ +-/* { dg-final { scan-assembler-times "xsmuldp" 4 } } */ ++/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 4 } } */ + /* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 2 } } */ +-/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ +-/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +-/* { dg-final { scan-assembler-times "fmuls" 4 } } */ +-/* { dg-final { scan-assembler-times "fnmsubs" 2 } } */ ++/* { dg-final { scan-assembler-times "xsrsqrtesp\|frsqrtes" 1 } } */ ++/* { dg-final { scan-assembler-times "xsmsub.sp\|fmsubs" 1 } } */ ++/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 1 } } */ + + double + rsqrt_d (double a) +--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-2.c +@@ -1,5 +1,6 @@ + /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ + /* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ + /* { dg-options "-O2 -mpointers-to-nested-functions" } */ + + int +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +@@ -0,0 +1,42 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ ++ ++float load_sf (float *p) ++{ ++ float f = *p; ++ __asm__ ("# reg %x0" : "+v" (f)); ++ return f; ++} ++ ++double load_df (double *p) ++{ ++ double d = *p; ++ __asm__ ("# reg %x0" : "+v" (d)); ++ return d; ++} ++ ++double load_dfsf (float *p) ++{ ++ double d = (double) *p; ++ __asm__ ("# reg %x0" : "+v" (d)); ++ return d; ++} ++ ++void store_sf (float *p, float f) ++{ ++ __asm__ ("# reg %x0" : "+v" (f)); ++ *p = f; ++} ++ ++void store_df (double *p, double d) ++{ ++ __asm__ ("# reg %x0" : "+v" (d)); ++ *p = d; ++} ++ ++/* { dg-final { scan-assembler "lxsspx" } } */ ++/* { dg-final { scan-assembler "lxsdx" } } */ ++/* { dg-final { scan-assembler "stxsspx" } } */ ++/* { dg-final { scan-assembler "stxsdx" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c +@@ -0,0 +1,36 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-O2 -mcpu=power8" } */ ++/* { dg-final { scan-assembler "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]eqv " } } */ ++/* { dg-final { scan-assembler "\[ \t\]orc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]nand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ ++ ++#ifndef TYPE ++#ifdef _ARCH_PPC64 ++#define TYPE __int128_t ++#else ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++#endif ++ ++#include "bool3.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c +@@ -0,0 +1,32 @@ ++/* This checks the availability of the XL compiler intrinsics for ++ transactional execution with the expected prototypes. */ ++ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_htm_ok } */ ++/* { dg-options "-O2 -mhtm" } */ ++ ++#include ++ ++void ++foo (void *TM_buff, long *result, unsigned char *code) ++{ ++ *result++ = __TM_simple_begin (); ++ *result++ = __TM_begin (TM_buff); ++ *result++ = __TM_end (); ++ __TM_abort (); ++ __TM_named_abort (*code); ++ __TM_resume (); ++ __TM_suspend (); ++ *result++ = __TM_is_user_abort (TM_buff); ++ *result++ = __TM_is_named_user_abort (TM_buff, code); ++ *result++ = __TM_is_illegal (TM_buff); ++ *result++ = __TM_is_footprint_exceeded (TM_buff); ++ *result++ = __TM_nesting_depth (TM_buff); ++ *result++ = __TM_is_nested_too_deep (TM_buff); ++ *result++ = __TM_is_conflict (TM_buff); ++ *result++ = __TM_is_failure_persistent (TM_buff); ++ *result++ = __TM_failure_address (TM_buff); ++ *result++ = __TM_failure_code (TM_buff); ++} ++ +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c +@@ -0,0 +1,249 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */ ++ ++#include ++ ++typedef vector long long vll_sign; ++typedef vector unsigned long long vll_uns; ++typedef vector bool long long vll_bool; ++ ++typedef vector int vi_sign; ++typedef vector unsigned int vi_uns; ++typedef vector bool int vi_bool; ++ ++typedef vector short vs_sign; ++typedef vector unsigned short vs_uns; ++typedef vector bool short vs_bool; ++ ++typedef vector signed char vc_sign; ++typedef vector unsigned char vc_uns; ++typedef vector bool char vc_bool; ++ ++vll_sign vll_clz_1 (vll_sign a) ++{ ++ return __builtin_altivec_vclzd (a); ++} ++ ++vll_sign vll_clz_2 (vll_sign a) ++{ ++ return vec_vclz (a); ++} ++ ++vll_sign vll_clz_3 (vll_sign a) ++{ ++ return vec_vclzd (a); ++} ++ ++vll_uns vll_clz_4 (vll_uns a) ++{ ++ return vec_vclz (a); ++} ++ ++vll_uns vll_clz_5 (vll_uns a) ++{ ++ return vec_vclzd (a); ++} ++ ++vi_sign vi_clz_1 (vi_sign a) ++{ ++ return __builtin_altivec_vclzw (a); ++} ++ ++vi_sign vi_clz_2 (vi_sign a) ++{ ++ return vec_vclz (a); ++} ++ ++vi_sign vi_clz_3 (vi_sign a) ++{ ++ return vec_vclzw (a); ++} ++ ++vi_uns vi_clz_4 (vi_uns a) ++{ ++ return vec_vclz (a); ++} ++ ++vi_uns vi_clz_5 (vi_uns a) ++{ ++ return vec_vclzw (a); ++} ++ ++vs_sign vs_clz_1 (vs_sign a) ++{ ++ return __builtin_altivec_vclzh (a); ++} ++ ++vs_sign vs_clz_2 (vs_sign a) ++{ ++ return vec_vclz (a); ++} ++ ++vs_sign vs_clz_3 (vs_sign a) ++{ ++ return vec_vclzh (a); ++} ++ ++vs_uns vs_clz_4 (vs_uns a) ++{ ++ return vec_vclz (a); ++} ++ ++vs_uns vs_clz_5 (vs_uns a) ++{ ++ return vec_vclzh (a); ++} ++ ++vc_sign vc_clz_1 (vc_sign a) ++{ ++ return __builtin_altivec_vclzb (a); ++} ++ ++vc_sign vc_clz_2 (vc_sign a) ++{ ++ return vec_vclz (a); ++} ++ ++vc_sign vc_clz_3 (vc_sign a) ++{ ++ return vec_vclzb (a); ++} ++ ++vc_uns vc_clz_4 (vc_uns a) ++{ ++ return vec_vclz (a); ++} ++ ++vc_uns vc_clz_5 (vc_uns a) ++{ ++ return vec_vclzb (a); ++} ++ ++vll_sign vll_popcnt_1 (vll_sign a) ++{ ++ return __builtin_altivec_vpopcntd (a); ++} ++ ++vll_sign vll_popcnt_2 (vll_sign a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vll_sign vll_popcnt_3 (vll_sign a) ++{ ++ return vec_vpopcntd (a); ++} ++ ++vll_uns vll_popcnt_4 (vll_uns a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vll_uns vll_popcnt_5 (vll_uns a) ++{ ++ return vec_vpopcntd (a); ++} ++ ++vi_sign vi_popcnt_1 (vi_sign a) ++{ ++ return __builtin_altivec_vpopcntw (a); ++} ++ ++vi_sign vi_popcnt_2 (vi_sign a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vi_sign vi_popcnt_3 (vi_sign a) ++{ ++ return vec_vpopcntw (a); ++} ++ ++vi_uns vi_popcnt_4 (vi_uns a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vi_uns vi_popcnt_5 (vi_uns a) ++{ ++ return vec_vpopcntw (a); ++} ++ ++vs_sign vs_popcnt_1 (vs_sign a) ++{ ++ return __builtin_altivec_vpopcnth (a); ++} ++ ++vs_sign vs_popcnt_2 (vs_sign a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vs_sign vs_popcnt_3 (vs_sign a) ++{ ++ return vec_vpopcnth (a); ++} ++ ++vs_uns vs_popcnt_4 (vs_uns a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vs_uns vs_popcnt_5 (vs_uns a) ++{ ++ return vec_vpopcnth (a); ++} ++ ++vc_sign vc_popcnt_1 (vc_sign a) ++{ ++ return __builtin_altivec_vpopcntb (a); ++} ++ ++vc_sign vc_popcnt_2 (vc_sign a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vc_sign vc_popcnt_3 (vc_sign a) ++{ ++ return vec_vpopcntb (a); ++} ++ ++vc_uns vc_popcnt_4 (vc_uns a) ++{ ++ return vec_vpopcnt (a); ++} ++ ++vc_uns vc_popcnt_5 (vc_uns a) ++{ ++ return vec_vpopcntb (a); ++} ++ ++vc_uns vc_gbb_1 (vc_uns a) ++{ ++ return __builtin_altivec_vgbbd (a); ++} ++ ++vc_sign vc_gbb_2 (vc_sign a) ++{ ++ return vec_vgbbd (a); ++} ++ ++vc_uns vc_gbb_3 (vc_uns a) ++{ ++ return vec_vgbbd (a); ++} ++ ++/* { dg-final { scan-assembler-times "vclzd" 5 } } */ ++/* { dg-final { scan-assembler-times "vclzw" 5 } } */ ++/* { dg-final { scan-assembler-times "vclzh" 5 } } */ ++/* { dg-final { scan-assembler-times "vclzb" 5 } } */ ++ ++/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */ ++/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */ ++/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */ ++/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */ ++ ++/* { dg-final { scan-assembler-times "vgbbd" 3 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool3-av.c +@@ -0,0 +1,37 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */ ++/* { dg-final { scan-assembler "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ ++ ++/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the ++ vector unit doesn't support these, so the appropriate combine patterns may ++ not be generated. */ ++ ++#ifndef TYPE ++#ifdef _ARCH_PPC64 ++#define TYPE __int128_t ++#else ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++#endif ++ ++#include "bool3.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c +@@ -0,0 +1,69 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++#ifndef ALIGN ++#define ALIGN 32 ++#endif ++ ++#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) ++ ++#define DO_BUILTIN(PREFIX, TYPE, CLZ, POPCNT) \ ++TYPE PREFIX ## _a[SIZE] ALIGN_ATTR; \ ++TYPE PREFIX ## _b[SIZE] ALIGN_ATTR; \ ++ \ ++void \ ++PREFIX ## _clz (void) \ ++{ \ ++ unsigned long i; \ ++ \ ++ for (i = 0; i < SIZE; i++) \ ++ PREFIX ## _a[i] = CLZ (PREFIX ## _b[i]); \ ++} \ ++ \ ++void \ ++PREFIX ## _popcnt (void) \ ++{ \ ++ unsigned long i; \ ++ \ ++ for (i = 0; i < SIZE; i++) \ ++ PREFIX ## _a[i] = POPCNT (PREFIX ## _b[i]); \ ++} ++ ++#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR) ++#define DO_INT 1 ++#endif ++ ++#if DO_LONG_LONG ++/* At the moment, only int is auto vectorized. */ ++DO_BUILTIN (sll, long long, __builtin_clzll, __builtin_popcountll) ++DO_BUILTIN (ull, unsigned long long, __builtin_clzll, __builtin_popcountll) ++#endif ++ ++#if defined(_ARCH_PPC64) && DO_LONG ++DO_BUILTIN (sl, long, __builtin_clzl, __builtin_popcountl) ++DO_BUILTIN (ul, unsigned long, __builtin_clzl, __builtin_popcountl) ++#endif ++ ++#if DO_INT ++DO_BUILTIN (si, int, __builtin_clz, __builtin_popcount) ++DO_BUILTIN (ui, unsigned int, __builtin_clz, __builtin_popcount) ++#endif ++ ++#if DO_SHORT ++DO_BUILTIN (ss, short, __builtin_clz, __builtin_popcount) ++DO_BUILTIN (us, unsigned short, __builtin_clz, __builtin_popcount) ++#endif ++ ++#if DO_CHAR ++DO_BUILTIN (sc, signed char, __builtin_clz, __builtin_popcount) ++DO_BUILTIN (uc, unsigned char, __builtin_clz, __builtin_popcount) ++#endif ++ ++/* { dg-final { scan-assembler-times "vclzw" 2 } } */ ++/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ ++/* { dg-options "-O2 -mcpu=power7 -mno-compat-align-parm" } */ ++ ++/* Verify that vs is 16-byte aligned with -mcompat-align-parm. */ ++ ++typedef float v4sf __attribute__ ((vector_size (16))); ++struct s { long m; v4sf v; }; ++long n; ++v4sf ve; ++ ++void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6, ++ long d7, long d8, long d9, struct s vs) { ++ n = vs.m; ++ ve = vs.v; ++} ++ ++/* { dg-final { scan-assembler "li \.\*,144" } } */ ++/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/atomic-p8.c +@@ -0,0 +1,237 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler-times "lbarx" 7 } } */ ++/* { dg-final { scan-assembler-times "lharx" 7 } } */ ++/* { dg-final { scan-assembler-times "lwarx" 7 } } */ ++/* { dg-final { scan-assembler-times "ldarx" 7 } } */ ++/* { dg-final { scan-assembler-times "lqarx" 7 } } */ ++/* { dg-final { scan-assembler-times "stbcx" 7 } } */ ++/* { dg-final { scan-assembler-times "sthcx" 7 } } */ ++/* { dg-final { scan-assembler-times "stwcx" 7 } } */ ++/* { dg-final { scan-assembler-times "stdcx" 7 } } */ ++/* { dg-final { scan-assembler-times "stqcx" 7 } } */ ++/* { dg-final { scan-assembler-not "bl __atomic" } } */ ++/* { dg-final { scan-assembler-times "isync" 20 } } */ ++/* { dg-final { scan-assembler-times "lwsync" 10 } } */ ++/* { dg-final { scan-assembler-not "mtvsrd" } } */ ++/* { dg-final { scan-assembler-not "mtvsrwa" } } */ ++/* { dg-final { scan-assembler-not "mtvsrwz" } } */ ++/* { dg-final { scan-assembler-not "mfvsrd" } } */ ++/* { dg-final { scan-assembler-not "mfvsrwz" } } */ ++ ++/* Test for the byte atomic operations on power8 using lbarx/stbcx. */ ++char ++char_fetch_add_relaxed (char *ptr, int value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++char ++char_fetch_sub_consume (char *ptr, int value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++char ++char_fetch_and_acquire (char *ptr, int value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++char ++char_fetch_ior_release (char *ptr, int value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++char ++char_fetch_xor_acq_rel (char *ptr, int value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++char ++char_fetch_nand_seq_cst (char *ptr, int value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++void ++char_val_compare_and_swap (char *p, int i, int j, char *q) ++{ ++ *q = __sync_val_compare_and_swap (p, i, j); ++} ++ ++/* Test for the half word atomic operations on power8 using lharx/sthcx. */ ++short ++short_fetch_add_relaxed (short *ptr, int value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++short ++short_fetch_sub_consume (short *ptr, int value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++short ++short_fetch_and_acquire (short *ptr, int value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++short ++short_fetch_ior_release (short *ptr, int value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++short ++short_fetch_xor_acq_rel (short *ptr, int value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++short ++short_fetch_nand_seq_cst (short *ptr, int value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++void ++short_val_compare_and_swap (short *p, int i, int j, short *q) ++{ ++ *q = __sync_val_compare_and_swap (p, i, j); ++} ++ ++/* Test for the word atomic operations on power8 using lwarx/stwcx. */ ++int ++int_fetch_add_relaxed (int *ptr, int value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++int ++int_fetch_sub_consume (int *ptr, int value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++int ++int_fetch_and_acquire (int *ptr, int value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++int ++int_fetch_ior_release (int *ptr, int value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++int ++int_fetch_xor_acq_rel (int *ptr, int value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++int ++int_fetch_nand_seq_cst (int *ptr, int value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++void ++int_val_compare_and_swap (int *p, int i, int j, int *q) ++{ ++ *q = __sync_val_compare_and_swap (p, i, j); ++} ++ ++/* Test for the double word atomic operations on power8 using ldarx/stdcx. */ ++long ++long_fetch_add_relaxed (long *ptr, long value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++long ++long_fetch_sub_consume (long *ptr, long value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++long ++long_fetch_and_acquire (long *ptr, long value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++long ++long_fetch_ior_release (long *ptr, long value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++long ++long_fetch_xor_acq_rel (long *ptr, long value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++long ++long_fetch_nand_seq_cst (long *ptr, long value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++void ++long_val_compare_and_swap (long *p, long i, long j, long *q) ++{ ++ *q = __sync_val_compare_and_swap (p, i, j); ++} ++ ++/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */ ++__int128_t ++quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); ++} ++ ++__int128_t ++quad_fetch_sub_consume (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); ++} ++ ++__int128_t ++quad_fetch_and_acquire (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); ++} ++ ++__int128_t ++quad_fetch_ior_release (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); ++} ++ ++__int128_t ++quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); ++} ++ ++__int128_t ++quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value) ++{ ++ return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); ++} ++ ++void ++quad_val_compare_and_swap (__int128_t *p, __int128_t i, __int128_t j, __int128_t *q) ++{ ++ *q = __sync_val_compare_and_swap (p, i, j); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */ ++/* { dg-final { scan-assembler-not "lfiwzx" } } */ ++/* { dg-final { scan-assembler-times "lfd" 2 } } */ ++/* { dg-final { scan-assembler-times "dctdp" 2 } } */ ++/* { dg-final { scan-assembler-times "dadd" 1 } } */ ++/* { dg-final { scan-assembler-times "drsp" 1 } } */ ++ ++/* Test that for power6 we need to use a bounce buffer on the stack to load ++ SDmode variables because the power6 does not have a way to directly load ++ 32-bit values from memory. */ ++_Decimal32 a; ++ ++void inc_dec32 (void) ++{ ++ a += (_Decimal32) 1.0; ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-4.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-4.c +@@ -7,8 +7,8 @@ + /* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */ + /* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */ + /* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */ +-/* { dg-final { scan-assembler-times "xvmulsp" 4 } } */ +-/* { dg-final { scan-assembler-times "xvnmsub.sp" 2 } } */ ++/* { dg-final { scan-assembler-times "xvmulsp" 2 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub.sp" 1 } } */ + + #define SIZE 1024 + +--- a/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/no-r11-3.c +@@ -1,5 +1,6 @@ + /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ + /* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ + /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ + + extern void ext_call (int (func) (void)); +--- a/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c +@@ -0,0 +1,130 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++typedef vector unsigned long long crypto_t; ++typedef vector unsigned long long v2di_t; ++typedef vector unsigned int v4si_t; ++typedef vector unsigned short v8hi_t; ++typedef vector unsigned char v16qi_t; ++ ++crypto_t crpyto1 (crypto_t a) ++{ ++ return __builtin_crypto_vsbox (a); ++} ++ ++crypto_t crypto2 (crypto_t a, crypto_t b) ++{ ++ return __builtin_crypto_vcipher (a, b); ++} ++ ++crypto_t crypto3 (crypto_t a, crypto_t b) ++{ ++ return __builtin_crypto_vcipherlast (a, b); ++} ++ ++crypto_t crypto4 (crypto_t a, crypto_t b) ++{ ++ return __builtin_crypto_vncipher (a, b); ++} ++ ++crypto_t crypto5 (crypto_t a, crypto_t b) ++{ ++ return __builtin_crypto_vncipherlast (a, b); ++} ++ ++v16qi_t crypto6a (v16qi_t a, v16qi_t b, v16qi_t c) ++{ ++ return __builtin_crypto_vpermxor (a, b, c); ++} ++ ++v8hi_t crypto6b (v8hi_t a, v8hi_t b, v8hi_t c) ++{ ++ return __builtin_crypto_vpermxor (a, b, c); ++} ++ ++v4si_t crypto6c (v4si_t a, v4si_t b, v4si_t c) ++{ ++ return __builtin_crypto_vpermxor (a, b, c); ++} ++ ++v2di_t crypto6d (v2di_t a, v2di_t b, v2di_t c) ++{ ++ return __builtin_crypto_vpermxor (a, b, c); ++} ++ ++v16qi_t crypto7a (v16qi_t a, v16qi_t b) ++{ ++ return __builtin_crypto_vpmsumb (a, b); ++} ++ ++v16qi_t crypto7b (v16qi_t a, v16qi_t b) ++{ ++ return __builtin_crypto_vpmsum (a, b); ++} ++ ++v8hi_t crypto7c (v8hi_t a, v8hi_t b) ++{ ++ return __builtin_crypto_vpmsumh (a, b); ++} ++ ++v8hi_t crypto7d (v8hi_t a, v8hi_t b) ++{ ++ return __builtin_crypto_vpmsum (a, b); ++} ++ ++v4si_t crypto7e (v4si_t a, v4si_t b) ++{ ++ return __builtin_crypto_vpmsumw (a, b); ++} ++ ++v4si_t crypto7f (v4si_t a, v4si_t b) ++{ ++ return __builtin_crypto_vpmsum (a, b); ++} ++ ++v2di_t crypto7g (v2di_t a, v2di_t b) ++{ ++ return __builtin_crypto_vpmsumd (a, b); ++} ++ ++v2di_t crypto7h (v2di_t a, v2di_t b) ++{ ++ return __builtin_crypto_vpmsum (a, b); ++} ++ ++v2di_t crypto8a (v2di_t a) ++{ ++ return __builtin_crypto_vshasigmad (a, 0, 8); ++} ++ ++v2di_t crypto8b (v2di_t a) ++{ ++ return __builtin_crypto_vshasigma (a, 0, 8); ++} ++ ++v4si_t crypto8c (v4si_t a) ++{ ++ return __builtin_crypto_vshasigmaw (a, 1, 15); ++} ++ ++v4si_t crypto8d (v4si_t a) ++{ ++ return __builtin_crypto_vshasigma (a, 1, 15); ++} ++ ++/* Note space is used after the instruction so that vcipherlast does not match ++ vcipher. */ ++/* { dg-final { scan-assembler-times "vcipher " 1 } } */ ++/* { dg-final { scan-assembler-times "vcipherlast " 1 } } */ ++/* { dg-final { scan-assembler-times "vncipher " 1 } } */ ++/* { dg-final { scan-assembler-times "vncipherlast " 1 } } */ ++/* { dg-final { scan-assembler-times "vpermxor " 4 } } */ ++/* { dg-final { scan-assembler-times "vpmsumb " 2 } } */ ++/* { dg-final { scan-assembler-times "vpmsumd " 2 } } */ ++/* { dg-final { scan-assembler-times "vpmsumh " 2 } } */ ++/* { dg-final { scan-assembler-times "vpmsumw " 2 } } */ ++/* { dg-final { scan-assembler-times "vsbox " 1 } } */ ++/* { dg-final { scan-assembler-times "vshasigmad " 2 } } */ ++/* { dg-final { scan-assembler-times "vshasigmaw " 2 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/pr42747.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr42747.c +@@ -5,4 +5,4 @@ + + double foo (double x) { return __builtin_sqrt (x); } + +-/* { dg-final { scan-assembler "xssqrtdp" } } */ ++/* { dg-final { scan-assembler "xssqrtdp\|fsqrt" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c +@@ -0,0 +1,26 @@ ++/* Test generation of DFP instructions for POWER6. */ ++/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ ++/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */ ++ ++/* { dg-final { scan-assembler-times "fneg" 1 } } */ ++/* { dg-final { scan-assembler-times "fabs" 1 } } */ ++/* { dg-final { scan-assembler-times "fnabs" 1 } } */ ++/* { dg-final { scan-assembler-times "fmr" 0 } } */ ++ ++_Decimal64 ++func1 (_Decimal64 a, _Decimal64 b) ++{ ++ return -b; ++} ++ ++_Decimal64 ++func2 (_Decimal64 a, _Decimal64 b) ++{ ++ return __builtin_fabsd64 (b); ++} ++ ++_Decimal64 ++func3 (_Decimal64 a, _Decimal64 b) ++{ ++ return - __builtin_fabsd64 (b); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler "mtvsrd" } } */ ++/* { dg-final { scan-assembler "mfvsrd" } } */ ++/* { dg-final { scan-assembler "xscvdpspn" } } */ ++/* { dg-final { scan-assembler "xscvspdpn" } } */ ++ ++/* Check code generation for direct move for float types. */ ++ ++#define TYPE float ++#define IS_FLOAT 1 ++#define NO_ALTIVEC 1 ++#define VSX_REG_ATTR "ww" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c +@@ -0,0 +1,29 @@ ++/* Test generation of DFP instructions for POWER6. */ ++/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ ++/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */ ++ ++/* { dg-final { scan-assembler-times "fneg" 1 } } */ ++/* { dg-final { scan-assembler-times "fabs" 1 } } */ ++/* { dg-final { scan-assembler-times "fnabs" 1 } } */ ++/* { dg-final { scan-assembler-times "fmr" 0 } } */ ++ ++/* These tests verify we only generate fneg, fabs and fnabs ++ instructions and no fmr's since these are done in place. */ ++ ++_Decimal128 ++func1 (_Decimal128 a) ++{ ++ return -a; ++} ++ ++_Decimal128 ++func2 (_Decimal128 a) ++{ ++ return __builtin_fabsd128 (a); ++} ++ ++_Decimal128 ++func3 (_Decimal128 a) ++{ ++ return - __builtin_fabsd128 (a); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c +@@ -0,0 +1,105 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++#include ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++#ifndef ALIGN ++#define ALIGN 32 ++#endif ++ ++#ifndef ATTR_ALIGN ++#define ATTR_ALIGN __attribute__((__aligned__(ALIGN))) ++#endif ++ ++#define DOIT(TYPE, PREFIX) \ ++TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \ ++{ \ ++ return vec_eqv (a, b); \ ++} \ ++ \ ++TYPE PREFIX ## _eqv_arith (TYPE a, TYPE b) \ ++{ \ ++ return ~(a ^ b); \ ++} \ ++ \ ++TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \ ++{ \ ++ return vec_nand (a, b); \ ++} \ ++ \ ++TYPE PREFIX ## _nand_arith1 (TYPE a, TYPE b) \ ++{ \ ++ return ~(a & b); \ ++} \ ++ \ ++TYPE PREFIX ## _nand_arith2 (TYPE a, TYPE b) \ ++{ \ ++ return (~a) | (~b); \ ++} \ ++ \ ++TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \ ++{ \ ++ return vec_orc (a, b); \ ++} \ ++ \ ++TYPE PREFIX ## _orc_arith1 (TYPE a, TYPE b) \ ++{ \ ++ return (~ a) | b; \ ++} \ ++ \ ++TYPE PREFIX ## _orc_arith2 (TYPE a, TYPE b) \ ++{ \ ++ return a | (~ b); \ ++} ++ ++#define DOIT_FLOAT(TYPE, PREFIX) \ ++TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \ ++{ \ ++ return vec_eqv (a, b); \ ++} \ ++ \ ++TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \ ++{ \ ++ return vec_nand (a, b); \ ++} \ ++ \ ++TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \ ++{ \ ++ return vec_orc (a, b); \ ++} ++ ++typedef vector signed char sign_char_vec; ++typedef vector short sign_short_vec; ++typedef vector int sign_int_vec; ++typedef vector long long sign_llong_vec; ++ ++typedef vector unsigned char uns_char_vec; ++typedef vector unsigned short uns_short_vec; ++typedef vector unsigned int uns_int_vec; ++typedef vector unsigned long long uns_llong_vec; ++ ++typedef vector float float_vec; ++typedef vector double double_vec; ++ ++DOIT(sign_char_vec, sign_char) ++DOIT(sign_short_vec, sign_short) ++DOIT(sign_int_vec, sign_int) ++DOIT(sign_llong_vec, sign_llong) ++ ++DOIT(uns_char_vec, uns_char) ++DOIT(uns_short_vec, uns_short) ++DOIT(uns_int_vec, uns_int) ++DOIT(uns_llong_vec, uns_llong) ++ ++DOIT_FLOAT(float_vec, float) ++DOIT_FLOAT(double_vec, double) ++ ++/* { dg-final { scan-assembler-times "xxleqv" 18 } } */ ++/* { dg-final { scan-assembler-times "xxlnand" 26 } } */ ++/* { dg-final { scan-assembler-times "xxlorc" 26 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c +@@ -0,0 +1,87 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ ++ ++#ifndef SIZE ++#define SIZE 1024 ++#endif ++ ++#ifndef ALIGN ++#define ALIGN 32 ++#endif ++ ++#ifndef ATTR_ALIGN ++#define ATTR_ALIGN __attribute__((__aligned__(ALIGN))) ++#endif ++ ++#ifndef TYPE ++#define TYPE unsigned int ++#endif ++ ++TYPE in1 [SIZE] ATTR_ALIGN; ++TYPE in2 [SIZE] ATTR_ALIGN; ++TYPE eqv [SIZE] ATTR_ALIGN; ++TYPE nand1[SIZE] ATTR_ALIGN; ++TYPE nand2[SIZE] ATTR_ALIGN; ++TYPE orc1 [SIZE] ATTR_ALIGN; ++TYPE orc2 [SIZE] ATTR_ALIGN; ++ ++void ++do_eqv (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ { ++ eqv[i] = ~(in1[i] ^ in2[i]); ++ } ++} ++ ++void ++do_nand1 (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ { ++ nand1[i] = ~(in1[i] & in2[i]); ++ } ++} ++ ++void ++do_nand2 (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ { ++ nand2[i] = (~in1[i]) | (~in2[i]); ++ } ++} ++ ++void ++do_orc1 (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ { ++ orc1[i] = (~in1[i]) | in2[i]; ++ } ++} ++ ++void ++do_orc2 (void) ++{ ++ unsigned long i; ++ ++ for (i = 0; i < SIZE; i++) ++ { ++ orc1[i] = in1[i] | (~in2[i]); ++ } ++} ++ ++/* { dg-final { scan-assembler-times "xxleqv" 1 } } */ ++/* { dg-final { scan-assembler-times "xxlnand" 2 } } */ ++/* { dg-final { scan-assembler-times "xxlorc" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr57949-2.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ ++/* { dg-options "-O2 -mcpu=power7" } */ ++ ++/* Verify that vs is not 16-byte aligned in the absence of -mno-compat-align-parm. */ ++ ++typedef float v4sf __attribute__ ((vector_size (16))); ++struct s { long m; v4sf v; }; ++long n; ++v4sf ve; ++ ++void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6, ++ long d7, long d8, long d9, struct s vs) { ++ n = vs.m; ++ ve = vs.v; ++} ++ ++/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */ ++/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/recip-5.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/recip-5.c +@@ -4,8 +4,16 @@ + /* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */ + /* { dg-final { scan-assembler-times "xvredp" 4 } } */ + /* { dg-final { scan-assembler-times "xvresp" 5 } } */ +-/* { dg-final { scan-assembler-times "xsredp" 2 } } */ +-/* { dg-final { scan-assembler-times "fres" 2 } } */ ++/* { dg-final { scan-assembler-times "xsredp\|fre\ " 2 } } */ ++/* { dg-final { scan-assembler-times "xsresp\|fres" 2 } } */ ++/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 2 } } */ ++/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 2 } } */ ++/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 4 } } */ ++/* { dg-final { scan-assembler-times "xvmulsp" 7 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub.sp" 5 } } */ ++/* { dg-final { scan-assembler-times "xvmuldp" 6 } } */ ++/* { dg-final { scan-assembler-times "xvnmsub.dp" 8 } } */ + + #include + +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c +@@ -89,8 +89,10 @@ + long a1; + long a2; + long a3; ++#if _CALL_ELF != 2 + long a4; + long a5; ++#endif + parm_t slot[100]; + } stack_frame_t; + +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c +@@ -0,0 +1,15 @@ ++/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target p8vector_hw } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++/* Check whether we get the right bits for direct move at runtime. */ ++ ++#define TYPE float ++#define IS_FLOAT 1 ++#define NO_ALTIVEC 1 ++#define DO_MAIN ++#define VSX_REG_ATTR "ww" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler "mtvsrd" } } */ ++/* { dg-final { scan-assembler "mfvsrd" } } */ ++ ++/* Check code generation for direct move for double types. */ ++ ++#define TYPE double ++#define IS_FLOAT 1 ++#define NO_ALTIVEC 1 ++#define VSX_REG_ATTR "ws" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c +@@ -0,0 +1,29 @@ ++/* Test generation of DFP instructions for POWER6. */ ++/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ ++/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */ ++ ++/* { dg-final { scan-assembler-times "fneg" 1 } } */ ++/* { dg-final { scan-assembler-times "fabs" 1 } } */ ++/* { dg-final { scan-assembler-times "fnabs" 1 } } */ ++/* { dg-final { scan-assembler-times "fmr" 3 } } */ ++ ++/* These tests verify we generate fneg, fabs and fnabs and ++ associated fmr's since these are not done in place. */ ++ ++_Decimal128 ++func1 (_Decimal128 a, _Decimal128 b) ++{ ++ return -b; ++} ++ ++_Decimal128 ++func2 (_Decimal128 a, _Decimal128 b) ++{ ++ return __builtin_fabsd128 (b); ++} ++ ++_Decimal128 ++func3 (_Decimal128 a, _Decimal128 b) ++{ ++ return - __builtin_fabsd128 (b); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); } ++double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); } ++ ++/* { dg-final { scan-assembler "xscvdpspn" } } */ ++/* { dg-final { scan-assembler "xscvspdpn" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c +@@ -16,9 +16,9 @@ + /* { dg-final { scan-assembler "xvrspiz" } } */ + /* { dg-final { scan-assembler "xsrdpi" } } */ + /* { dg-final { scan-assembler "xsrdpic" } } */ +-/* { dg-final { scan-assembler "xsrdpim" } } */ +-/* { dg-final { scan-assembler "xsrdpip" } } */ +-/* { dg-final { scan-assembler "xsrdpiz" } } */ ++/* { dg-final { scan-assembler "xsrdpim\|frim" } } */ ++/* { dg-final { scan-assembler "xsrdpip\|frip" } } */ ++/* { dg-final { scan-assembler "xsrdpiz\|friz" } } */ + /* { dg-final { scan-assembler "xsmaxdp" } } */ + /* { dg-final { scan-assembler "xsmindp" } } */ + /* { dg-final { scan-assembler "xxland" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c +@@ -0,0 +1,51 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_htm_ok } */ ++/* { dg-options "-O2 -mhtm" } */ ++ ++/* { dg-final { scan-assembler-times "tbegin\\." 1 } } */ ++/* { dg-final { scan-assembler-times "tend\\." 2 } } */ ++/* { dg-final { scan-assembler-times "tabort\\." 2 } } */ ++/* { dg-final { scan-assembler-times "tabortdc\\." 1 } } */ ++/* { dg-final { scan-assembler-times "tabortdci\\." 1 } } */ ++/* { dg-final { scan-assembler-times "tabortwc\\." 1 } } */ ++/* { dg-final { scan-assembler-times "tabortwci\\." 2 } } */ ++/* { dg-final { scan-assembler-times "tcheck\\." 1 } } */ ++/* { dg-final { scan-assembler-times "trechkpt\\." 1 } } */ ++/* { dg-final { scan-assembler-times "treclaim\\." 1 } } */ ++/* { dg-final { scan-assembler-times "tsr\\." 3 } } */ ++/* { dg-final { scan-assembler-times "mfspr" 4 } } */ ++/* { dg-final { scan-assembler-times "mtspr" 4 } } */ ++ ++void use_builtins (long *p, char code, long *a, long *b) ++{ ++ p[0] = __builtin_tbegin (0); ++ p[1] = __builtin_tend (0); ++ p[2] = __builtin_tendall (); ++ p[3] = __builtin_tabort (0); ++ p[4] = __builtin_tabort (code); ++ ++ p[5] = __builtin_tabortdc (0xf, a[5], b[5]); ++ p[6] = __builtin_tabortdci (0xf, a[6], 13); ++ p[7] = __builtin_tabortwc (0xf, a[7], b[7]); ++ p[8] = __builtin_tabortwci (0xf, a[8], 13); ++ ++ p[9] = __builtin_tcheck (5); ++ p[10] = __builtin_trechkpt (); ++ p[11] = __builtin_treclaim (0); ++ p[12] = __builtin_tresume (); ++ p[13] = __builtin_tsuspend (); ++ p[14] = __builtin_tsr (0); ++ p[15] = __builtin_ttest (); /* This expands to a tabortwci. */ ++ ++ ++ p[16] = __builtin_get_texasr (); ++ p[17] = __builtin_get_texasru (); ++ p[18] = __builtin_get_tfhar (); ++ p[19] = __builtin_get_tfiar (); ++ ++ __builtin_set_texasr (a[20]); ++ __builtin_set_texasru (a[21]); ++ __builtin_set_tfhar (a[22]); ++ __builtin_set_tfiar (a[23]); ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/bool.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler "eqv" } } */ ++/* { dg-final { scan-assembler "nand" } } */ ++/* { dg-final { scan-assembler "nor" } } */ ++ ++#ifndef TYPE ++#define TYPE unsigned long ++#endif ++ ++TYPE op1 (TYPE a, TYPE b) { return ~(a ^ b); } /* eqv */ ++TYPE op2 (TYPE a, TYPE b) { return ~(a & b); } /* nand */ ++TYPE op3 (TYPE a, TYPE b) { return ~(a | b); } /* nor */ ++ +--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p5.c +@@ -0,0 +1,32 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */ ++/* { dg-final { scan-assembler "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]eqv " } } */ ++/* { dg-final { scan-assembler "\[ \t\]orc " } } */ ++/* { dg-final { scan-assembler "\[ \t\]nand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ ++ ++#ifndef TYPE ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++ ++#include "bool2.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/fusion.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/fusion.c +@@ -0,0 +1,24 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */ ++ ++#define LARGE 0x12345 ++ ++int fusion_uchar (unsigned char *p){ return p[LARGE]; } ++int fusion_schar (signed char *p){ return p[LARGE]; } ++int fusion_ushort (unsigned short *p){ return p[LARGE]; } ++int fusion_short (short *p){ return p[LARGE]; } ++int fusion_int (int *p){ return p[LARGE]; } ++unsigned fusion_uns (unsigned *p){ return p[LARGE]; } ++ ++vector double fusion_vector (vector double *p) { return p[2]; } ++ ++/* { dg-final { scan-assembler-times "gpr load fusion" 6 } } */ ++/* { dg-final { scan-assembler-times "vector load fusion" 1 } } */ ++/* { dg-final { scan-assembler-times "lbz" 2 } } */ ++/* { dg-final { scan-assembler-times "extsb" 1 } } */ ++/* { dg-final { scan-assembler-times "lhz" 2 } } */ ++/* { dg-final { scan-assembler-times "extsh" 1 } } */ ++/* { dg-final { scan-assembler-times "lwz" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c +@@ -107,8 +107,10 @@ + long a1; + long a2; + long a3; ++#if _CALL_ELF != 2 + long a4; + long a5; ++#endif + parm_t slot[100]; + } stack_frame_t; + +@@ -119,6 +121,12 @@ + vector int v; + } vector_int_t; + ++#ifdef __LITTLE_ENDIAN__ ++#define MAKE_SLOT(x, y) ((long)x | ((long)y << 32)) ++#else ++#define MAKE_SLOT(x, y) ((long)y | ((long)x << 32)) ++#endif ++ + /* Paramter passing. + s : gpr 3 + v : vpr 2 +@@ -226,8 +234,8 @@ + sp = __builtin_frame_address(0); + sp = sp->backchain; + +- if (sp->slot[2].l != 0x100000002ULL +- || sp->slot[4].l != 0x500000006ULL) ++ if (sp->slot[2].l != MAKE_SLOT (1, 2) ++ || sp->slot[4].l != MAKE_SLOT (5, 6)) + abort(); + } + +@@ -268,8 +276,8 @@ + sp = __builtin_frame_address(0); + sp = sp->backchain; + +- if (sp->slot[4].l != 0x100000002ULL +- || sp->slot[6].l != 0x500000006ULL) ++ if (sp->slot[4].l != MAKE_SLOT (1, 2) ++ || sp->slot[6].l != MAKE_SLOT (5, 6)) + abort(); + } + +@@ -296,8 +304,8 @@ + sp = __builtin_frame_address(0); + sp = sp->backchain; + +- if (sp->slot[4].l != 0x100000002ULL +- || sp->slot[6].l != 0x500000006ULL) ++ if (sp->slot[4].l != MAKE_SLOT (1, 2) ++ || sp->slot[6].l != MAKE_SLOT (5, 6)) + abort(); + } + +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler "mtvsrd" } } */ ++/* { dg-final { scan-assembler "mfvsrd" } } */ ++ ++/* Check code generation for direct move for long types. */ ++ ++#define TYPE long ++#define IS_INT 1 ++#define NO_ALTIVEC 1 ++#define VSX_REG_ATTR "d" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c +@@ -0,0 +1,15 @@ ++/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target p8vector_hw } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++/* Check whether we get the right bits for direct move at runtime. */ ++ ++#define TYPE double ++#define IS_FLOAT 1 ++#define NO_ALTIVEC 1 ++#define DO_MAIN ++#define VSX_REG_ATTR "ws" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c +@@ -0,0 +1,32 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++#include ++ ++typedef vector int v_sign; ++typedef vector unsigned int v_uns; ++ ++v_sign even_sign (v_sign a, v_sign b) ++{ ++ return vec_vmrgew (a, b); ++} ++ ++v_uns even_uns (v_uns a, v_uns b) ++{ ++ return vec_vmrgew (a, b); ++} ++ ++v_sign odd_sign (v_sign a, v_sign b) ++{ ++ return vec_vmrgow (a, b); ++} ++ ++v_uns odd_uns (v_uns a, v_uns b) ++{ ++ return vec_vmrgow (a, b); ++} ++ ++/* { dg-final { scan-assembler-times "vmrgew" 2 } } */ ++/* { dg-final { scan-assembler-times "vmrgow" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/bool2.h ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool2.h +@@ -0,0 +1,29 @@ ++/* Test various logical operations. */ ++ ++TYPE arg1 (TYPE p, TYPE q) { return p & q; } /* AND */ ++TYPE arg2 (TYPE p, TYPE q) { return p | q; } /* OR */ ++TYPE arg3 (TYPE p, TYPE q) { return p ^ q; } /* XOR */ ++TYPE arg4 (TYPE p) { return ~ p; } /* NOR */ ++TYPE arg5 (TYPE p, TYPE q) { return ~(p & q); } /* NAND */ ++TYPE arg6 (TYPE p, TYPE q) { return ~(p | q); } /* NOR */ ++TYPE arg7 (TYPE p, TYPE q) { return ~(p ^ q); } /* EQV */ ++TYPE arg8 (TYPE p, TYPE q) { return (~p) & q; } /* ANDC */ ++TYPE arg9 (TYPE p, TYPE q) { return (~p) | q; } /* ORC */ ++TYPE arg10(TYPE p, TYPE q) { return (~p) ^ q; } /* EQV */ ++TYPE arg11(TYPE p, TYPE q) { return p & (~q); } /* ANDC */ ++TYPE arg12(TYPE p, TYPE q) { return p | (~q); } /* ORC */ ++TYPE arg13(TYPE p, TYPE q) { return p ^ (~q); } /* EQV */ ++ ++void ptr1 (TYPE *p) { p[0] = p[1] & p[2]; } /* AND */ ++void ptr2 (TYPE *p) { p[0] = p[1] | p[2]; } /* OR */ ++void ptr3 (TYPE *p) { p[0] = p[1] ^ p[2]; } /* XOR */ ++void ptr4 (TYPE *p) { p[0] = ~p[1]; } /* NOR */ ++void ptr5 (TYPE *p) { p[0] = ~(p[1] & p[2]); } /* NAND */ ++void ptr6 (TYPE *p) { p[0] = ~(p[1] | p[2]); } /* NOR */ ++void ptr7 (TYPE *p) { p[0] = ~(p[1] ^ p[2]); } /* EQV */ ++void ptr8 (TYPE *p) { p[0] = ~(p[1]) & p[2]; } /* ANDC */ ++void ptr9 (TYPE *p) { p[0] = (~p[1]) | p[2]; } /* ORC */ ++void ptr10(TYPE *p) { p[0] = (~p[1]) ^ p[2]; } /* EQV */ ++void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); } /* ANDC */ ++void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); } /* ORC */ ++void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); } /* EQV */ +--- a/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr48258-1.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ + /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ + /* { dg-require-effective-target powerpc_vsx_ok } */ + /* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */ + /* { dg-final { scan-assembler-times "xvaddsp" 3 } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c +@@ -33,15 +33,27 @@ + + + /* Wrapper to save the GPRs and FPRs and then jump to the real function. */ ++#if _CALL_ELF != 2 ++#define FUNC_START(NAME) \ ++ "\t.globl\t" NAME "\n\t" \ ++ ".section \".opd\",\"aw\"\n\t" \ ++ ".align 3\n" \ ++ NAME ":\n\t" \ ++ ".quad .L." NAME ",.TOC.@tocbase,0\n\t" \ ++ ".text\n\t" \ ++ ".type " NAME ", @function\n" \ ++ ".L." NAME ":\n\t" ++#else ++#define FUNC_START(NAME) \ ++ "\t.globl\t" NAME "\n\t" \ ++ ".text\n\t" \ ++ NAME ":\n" \ ++ "0:\taddis 2,12,(.TOC.-0b)@ha\n\t" \ ++ "addi 2,2,(.TOC.-0b)@l\n\t" \ ++ ".localentry " NAME ",.-" NAME "\n\t" ++#endif + #define WRAPPER(NAME) \ +-__asm__ ("\t.globl\t" #NAME "_asm\n\t" \ +- ".section \".opd\",\"aw\"\n\t" \ +- ".align 3\n" \ +- #NAME "_asm:\n\t" \ +- ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \ +- ".text\n\t" \ +- ".type " #NAME "_asm, @function\n" \ +- ".L." #NAME "_asm:\n\t" \ ++__asm__ (FUNC_START (#NAME "_asm") \ + "ld 11,gparms@got(2)\n\t" \ + "std 3,0(11)\n\t" \ + "std 4,8(11)\n\t" \ +@@ -75,8 +87,10 @@ + long a1; + long a2; + long a3; ++#if _CALL_ELF != 2 + long a4; + long a5; ++#endif + unsigned long slot[100]; + } stack_frame_t; + +--- a/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c +@@ -0,0 +1,15 @@ ++/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target p8vector_hw } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++/* Check whether we get the right bits for direct move at runtime. */ ++ ++#define TYPE long ++#define IS_INT 1 ++#define NO_ALTIVEC 1 ++#define DO_MAIN ++#define VSX_REG_ATTR "d" ++ ++#include "direct-move.h" +--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-float0.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7" } */ ++/* { dg-final { scan-assembler "xxlxor" } } */ ++ ++/* Test that we generate xxlor to clear a SFmode register. */ ++ ++float sum (float *p, unsigned long n) ++{ ++ float sum = 0.0f; /* generate xxlxor instead of load */ ++ while (n-- > 0) ++ sum += *p++; ++ ++ return sum; ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c +@@ -5,8 +5,7 @@ + /* { dg-final { scan-assembler-times "fabs" 3 } } */ + /* { dg-final { scan-assembler-times "fnabs" 3 } } */ + /* { dg-final { scan-assembler-times "fsel" 3 } } */ +-/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */ +-/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */ ++/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */ + + double normal1 (double, double); + double power5 (double, double) __attribute__((__target__("cpu=power5"))); +--- a/src/gcc/testsuite/gcc.target/powerpc/bool3.h ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool3.h +@@ -0,0 +1,186 @@ ++/* Test forcing 128-bit logical types into GPR registers. */ ++ ++#if defined(NO_ASM) ++#define FORCE_REG1(X) ++#define FORCE_REG2(X,Y) ++ ++#else ++#if defined(USE_ALTIVEC) ++#define REG_CLASS "+v" ++#define PRINT_REG1 "# altivec reg %0" ++#define PRINT_REG2 "# altivec reg %0, %1" ++ ++#elif defined(USE_FPR) ++#define REG_CLASS "+d" ++#define PRINT_REG1 "# fpr reg %0" ++#define PRINT_REG2 "# fpr reg %0, %1" ++ ++#elif defined(USE_VSX) ++#define REG_CLASS "+wa" ++#define PRINT_REG1 "# vsx reg %x0" ++#define PRINT_REG2 "# vsx reg %x0, %x1" ++ ++#else ++#define REG_CLASS "+r" ++#define PRINT_REG1 "# gpr reg %0" ++#define PRINT_REG2 "# gpr reg %0, %1" ++#endif ++ ++#define FORCE_REG1(X) __asm__ (PRINT_REG1 : REG_CLASS (X)) ++#define FORCE_REG2(X,Y) __asm__ (PRINT_REG2 : REG_CLASS (X), REG_CLASS (Y)) ++#endif ++ ++void ptr1 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = a & b; /* AND */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr2 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = a | b; /* OR */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr3 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = a ^ b; /* XOR */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr4 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b; ++ ++ FORCE_REG1 (a); ++ b = ~a; /* NOR */ ++ FORCE_REG1 (b); ++ p[0] = b; ++} ++ ++void ptr5 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = ~(a & b); /* NAND */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr6 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = ~(a | b); /* AND */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr7 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = ~(a ^ b); /* EQV */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr8 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = (~a) & b; /* ANDC */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr9 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = (~a) | b; /* ORC */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr10 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = (~a) ^ b; /* EQV */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr11 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = a & (~b); /* ANDC */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr12 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = a | (~b); /* ORC */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} ++ ++void ptr13 (TYPE *p) ++{ ++ TYPE a = p[1]; ++ TYPE b = p[2]; ++ TYPE c; ++ ++ FORCE_REG2 (a, b); ++ c = a ^ (~b); /* AND */ ++ FORCE_REG1 (c); ++ p[0] = c; ++} +--- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c +@@ -19,19 +19,6 @@ + return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, }); + } + +-V p2(V x, V y) +-{ +- return __builtin_shuffle(x, y, +- (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 }); +- +-} +- +-V p4(V x, V y) +-{ +- return __builtin_shuffle(x, y, +- (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 }); +-} +- + V h1(V x, V y) + { + return __builtin_shuffle(x, y, +@@ -72,5 +59,3 @@ + /* { dg-final { scan-assembler "vspltb" } } */ + /* { dg-final { scan-assembler "vsplth" } } */ + /* { dg-final { scan-assembler "vspltw" } } */ +-/* { dg-final { scan-assembler "vpkuhum" } } */ +-/* { dg-final { scan-assembler "vpkuwum" } } */ +--- a/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c ++++ b/src/gcc/testsuite/gcc.target/powerpc/bool2-p7.c +@@ -0,0 +1,31 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-O2 -mcpu=power7" } */ ++/* { dg-final { scan-assembler-not "\[ \t\]and " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]or " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxland " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */ ++/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ ++/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ ++ ++#ifndef TYPE ++typedef int v4si __attribute__ ((vector_size (16))); ++#define TYPE v4si ++#endif ++ ++#include "bool2.h" +--- a/src/gcc/testsuite/ChangeLog.ibm ++++ b/src/gcc/testsuite/ChangeLog.ibm +@@ -0,0 +1,389 @@ ++2013-11-22 Michael Meissner ++ ++ Backport from mainline ++ 2013-11-22 Michael Meissner ++ ++ PR target/59054 ++ * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to ++ specify an appropriate register class for VSX operations. ++ (load_vsx): Use it. ++ (load_gpr_to_vsx): Likewise. ++ (load_vsx_to_gpr): Likewise. ++ * gcc.target/powerpc/direct-move-vint1.c: Use an appropriate ++ register class for VSX registers that the type can handle. Remove ++ checks for explicit number of instructions generated, just check ++ if the instruction is generated. ++ * gcc.target/powerpc/direct-move-vint2.c: Likewise. ++ * gcc.target/powerpc/direct-move-float1.c: Likewise. ++ * gcc.target/powerpc/direct-move-float2.c: Likewise. ++ * gcc.target/powerpc/direct-move-double1.c: Likewise. ++ * gcc.target/powerpc/direct-move-double2.c: Likewise. ++ * gcc.target/powerpc/direct-move-long1.c: Likewise. ++ * gcc.target/powerpc/direct-move-long2.c: Likewise. ++ ++ * gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now. ++ * gcc.target/powerpc/bool3-p7.c: Likewise. ++ * gcc.target/powerpc/bool3-p8.c: Likewise. ++ ++ * gcc.target/powerpc/p8vector-ldst.c: Just check that the ++ appropriate instructions are generated, don't check the count. ++ ++ 2013-11-12 Michael Meissner ++ ++ PR target/59054 ++ * gcc.target/powerpc/pr59054.c: New test. ++ ++2013-11-20 Bill Schmidt ++ ++ Backport from mainline r205146 ++ 2013-11-20 Bill Schmidt ++ ++ * gcc.target/powerpc/pr48258-1.c: Skip for little endian. ++ ++2013-11-20 Ulrich Weigand ++ ++ Backport from mainline r205106: ++ ++ 2013-11-20 Ulrich Weigand ++ ++ * gcc.target/powerpc/darwin-longlong.c (msw): Make endian-safe. ++ ++2013-11-19 Ulrich Weigand ++ ++ Backport from mainline r205046: ++ ++ 2013-11-19 Ulrich Weigand ++ ++ * gcc.target/powerpc/ppc64-abi-2.c (MAKE_SLOT): New macro to ++ construct parameter slot value in endian-independent way. ++ (fcevv, fciievv, fcvevv): Use it. ++ ++2013-11-15 Bill Schmidt ++ ++ Backport from mainline r204862 ++ 2013-11-15 Bill Schmidt ++ ++ * gcc.dg/vmx/3b-15.c: Revise for little endian. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204808: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * gcc.target/powerpc/ppc64-abi-1.c (stack_frame_t): Remove ++ compiler and linker field if _CALL_ELF == 2. ++ * gcc.target/powerpc/ppc64-abi-2.c (stack_frame_t): Likewise. ++ * gcc.target/powerpc/ppc64-abi-dfp-1.c (stack_frame_t): Likewise. ++ * gcc.dg/stack-usage-1.c (SIZE): Update value for _CALL_ELF == 2. ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * gcc.target/powerpc/ppc64-abi-dfp-1.c (FUNC_START): New macro. ++ (WRAPPER): Use it. ++ * gcc.target/powerpc/no-r11-1.c: Skip on powerpc_elfv2. ++ * gcc.target/powerpc/no-r11-2.c: Skip on powerpc_elfv2. ++ * gcc.target/powerpc/no-r11-3.c: Skip on powerpc_elfv2. ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * lib/target-supports.exp (check_effective_target_powerpc_elfv2): ++ New function. ++ * gcc.target/powerpc/pr57949-1.c: Disable for powerpc_elfv2. ++ * gcc.target/powerpc/pr57949-2.c: Likewise. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204799: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * g++.dg/eh/ppc64-sighandle-cr.C: New test. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r201750. ++ Note: Default setting of -mcompat-align-parm inverted! ++ ++ 2013-08-14 Bill Schmidt ++ ++ PR target/57949 ++ * gcc.target/powerpc/pr57949-1.c: New. ++ * gcc.target/powerpc/pr57949-2.c: New. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r201040 and r201929: ++ ++ 2013-08-22 Michael Meissner ++ ++ * gcc.target/powerpc/pr57744.c: Declare abort. ++ ++ 2013-07-18 Pat Haugen ++ ++ * gcc.target/powerpc/pr57744.c: Fix typo. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204321 ++ 2013-11-02 Bill Schmidt ++ ++ * gcc.dg/vmx/vec-set.c: New. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204138 ++ 2013-10-28 Bill Schmidt ++ ++ * gcc.dg/vmx/gcc-bug-i.c: Add little endian variant. ++ * gcc.dg/vmx/eg-5.c: Likewise. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203930 ++ 2013-10-22 Bill Schmidt ++ ++ * gcc.target/powerpc/altivec-perm-1.c: Move the two vector pack ++ tests into... ++ * gcc.target/powerpc/altivec-perm-3.c: ...this new test, which is ++ restricted to big-endian targets. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203246 ++ 2013-10-07 Bill Schmidt ++ ++ * gcc.target/powerpc/pr43154.c: Skip for ppc64 little endian. ++ * gcc.target/powerpc/fusion.c: Likewise. ++ ++2013-10-21 Bill Schmidt ++ ++ Backport from mainline ++ 2013-04-05 Bill Schmidt ++ ++ PR target/56843 ++ * gcc.target/powerpc/recip-1.c: Modify expected output. ++ * gcc.target/powerpc/recip-3.c: Likewise. ++ * gcc.target/powerpc/recip-4.c: Likewise. ++ * gcc.target/powerpc/recip-5.c: Add expected output for iterations. ++ ++2013-10-17 Michael Meissner ++ ++ Back port from mainline ++ 2013-10-03 Michael Meissner ++ ++ * gcc.target/powerpc/p8vector-fp.c: New test for floating point ++ scalar operations when using -mupper-regs-sf and -mupper-regs-df. ++ * gcc.target/powerpc/ppc-target-1.c: Update tests to allow either ++ VSX scalar operations or the traditional floating point form of ++ the instruction. ++ * gcc.target/powerpc/ppc-target-2.c: Likewise. ++ * gcc.target/powerpc/recip-3.c: Likewise. ++ * gcc.target/powerpc/recip-5.c: Likewise. ++ * gcc.target/powerpc/pr72747.c: Likewise. ++ * gcc.target/powerpc/vsx-builtin-3.c: Likewise. ++ ++ Back port from mainline ++ 2013-09-27 Michael Meissner ++ ++ * gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf ++ and -mupper-regs-df. ++ ++ Back port from mainline ++ 2013-10-17 Michael Meissner ++ ++ PR target/58673 ++ * gcc.target/powerpc/pr58673-1.c: New file to test whether ++ -mquad-word + -mno-vsx-timode causes errors. ++ * gcc.target/powerpc/pr58673-2.c: Likewise. ++ ++2013-08-19 Peter Bergner ++ ++ Back port from mainline ++ 2013-08-19 Peter Bergner ++ ++ * gcc.target/powerpc/dfp-dd-2.c: New test. ++ * gcc.target/powerpc/dfp-td-2.c: Likewise. ++ * gcc.target/powerpc/dfp-td-3.c: Likewise. ++ ++2013-08-16 Michael Meissner ++ ++ Backport from trunk. ++ 2013-07-23 Michael Meissner ++ ++ * gcc.target/powerpc/bool2.h: New file, test the code generation ++ of logical operations for power5, altivec, power7, and power8 systems. ++ * gcc.target/powerpc/bool2-p5.c: Likewise. ++ * gcc.target/powerpc/bool2-av.c: Likewise. ++ * gcc.target/powerpc/bool2-p7.c: Likewise. ++ * gcc.target/powerpc/bool2-p8.c: Likewise. ++ * gcc.target/powerpc/bool3.h: Likewise. ++ * gcc.target/powerpc/bool3-av.c: Likewise. ++ * gcc.target/powerpc/bool2-p7.c: Likewise. ++ * gcc.target/powerpc/bool2-p8.c: Likewise. ++ ++2013-08-16 Michael Meissner ++ ++ Backport from trunk. ++ 2013-07-31 Michael Meissner ++ ++ * gcc.target/powerpc/fusion.c: New file, test power8 fusion support. ++ ++2013-08-05 Michael Meissner ++ ++ Back port from mainline: ++ 2013-06-06 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * lib/target-supports.exp (check_p8vector_hw_available) Add power8 ++ support. ++ (check_effective_target_powerpc_p8vector_ok): Likewise. ++ (is-effective-target): Likewise. ++ (check_vect_support_and_set_flags): Likewise. ++ ++2013-08-04 Peter Bergner ++ ++ Back port from mainline ++ 2013-08-01 Fabien Chêne ++ Peter Bergner ++ ++ PR c++/54537 ++ * g++.dg/overload/using3.C: New. ++ * g++.dg/overload/using2.C: Adjust. ++ * g++.dg/lookup/using9.C: Likewise. ++ ++2013-07-31 Michael Meissner ++ ++ Back port from mainline ++ 2013-07-31 Michael Meissner ++ ++ * gcc.target/powerpc/fusion.c: New file, test power8 fusion ++ support. ++ ++2013-07-15 Peter Bergner ++ ++ Back port from mainline ++ 2013-07-15 Peter Bergner ++ ++ * lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New ++ function to test if HTM is available. ++ * gcc.target/powerpc/htm-xl-intrin-1.c: New test. ++ * gcc.target/powerpc/htm-builtin-1.c: New test. ++ ++2013-06-28 Michael Meissner ++ ++ Back port from the trunk ++ 2013-06-28 Michael Meissner ++ ++ PR target/57744 ++ * gcc.target/powerpc/pr57744.c: New test to make sure lqarx and ++ stqcx. get even registers. ++ ++2013-06-12 Michael Meissner ++ ++ Back port from the trunk ++ ++ 2013-06-12 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic ++ load/store instructions on power7, power8. ++ * gcc.target/powerpc/atomic-p8.c: Likewise. ++ ++2013-06-11 Michael Meissner ++ ++ Back port from the trunk ++ ++ 2013-06-11 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic ++ load/store instructions on power7, power8. ++ * gcc.target/powerpc/atomic-p8.c: Likewise. ++ ++ Back port from the trunk ++ ++ 2013-06-10 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * gcc.target/powerpc/direct-move-vint1.c: New tests for power8 ++ direct move instructions. ++ * gcc.target/powerpc/direct-move-vint2.c: Likewise. ++ * gcc.target/powerpc/direct-move.h: Likewise. ++ * gcc.target/powerpc/direct-move-float1.c: Likewise. ++ * gcc.target/powerpc/direct-move-float2.c: Likewise. ++ * gcc.target/powerpc/direct-move-double1.c: Likewise. ++ * gcc.target/powerpc/direct-move-double2.c: Likewise. ++ * gcc.target/powerpc/direct-move-long1.c: Likewise. ++ * gcc.target/powerpc/direct-move-long2.c: Likewise. ++ ++2013-06-06 Michael Meissner ++ ++ Backport from the trunk ++ ++ 2013-06-06 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * gcc.target/powerpc/p8vector-builtin-1.c: New test to test ++ power8 builtin functions. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c: New ++ tests to test power8 auto-vectorization. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c: Likewise. ++ * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c: Likewise. ++ ++ * gcc.target/powerpc/crypto-builtin-1.c: Use effective target ++ powerpc_p8vector_ok instead of powerpc_vsx_ok. ++ ++ * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests. ++ ++ * lib/target-supports.exp (check_p8vector_hw_available) Add power8 ++ support. ++ (check_effective_target_powerpc_p8vector_ok): Likewise. ++ (is-effective-target): Likewise. ++ (check_vect_support_and_set_flags): Likewise. ++ ++2013-06-06 Peter Bergner ++ ++ Backport from trunk ++ ++ 2013-05-22 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8 ++ crypto builtins. ++ ++2013-05-06 Michael Meissner ++ ++ Backport from trunk ++ 2013-05-03 Michael Meissner ++ ++ PR target/57150 ++ * gcc.target/powerpc/pr57150.c: New file. ++ ++2013-03-20 Michael Meissner ++ ++ Backport from mainline ++ 2013-03-20 Michael Meissner ++ ++ * gcc.target/powerpc/mmfpgpr.c: New test. ++ * gcc.target/powerpc/sd-vsx.c: Likewise. ++ * gcc.target/powerpc/sd-pwr6.c: Likewise. ++ * gcc.target/powerpc/vsx-float0.c: Likewise. ++ ++2013-03-20 Michael Meissner ++ ++ Clone branch from gcc-4_8-branch, subversion id 196835. +--- a/src/gcc/testsuite/lib/target-supports.exp ++++ b/src/gcc/testsuite/lib/target-supports.exp +@@ -1311,6 +1311,32 @@ + return 0 + } + ++# Return 1 if the target supports executing power8 vector instructions, 0 ++# otherwise. Cache the result. ++ ++proc check_p8vector_hw_available { } { ++ return [check_cached_effective_target p8vector_hw_available { ++ # Some simulators are known to not support VSX/power8 instructions. ++ # For now, disable on Darwin ++ if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} { ++ expr 0 ++ } else { ++ set options "-mpower8-vector" ++ check_runtime_nocache p8vector_hw_available { ++ int main() ++ { ++ #ifdef __MACH__ ++ asm volatile ("xxlorc vs0,vs0,vs0"); ++ #else ++ asm volatile ("xxlorc 0,0,0"); ++ #endif ++ return 0; ++ } ++ } $options ++ } ++ }] ++} ++ + # Return 1 if the target supports executing VSX instructions, 0 + # otherwise. Cache the result. + +@@ -2672,6 +2698,33 @@ + } + } + ++# Return 1 if this is a PowerPC target supporting -mpower8-vector ++ ++proc check_effective_target_powerpc_p8vector_ok { } { ++ if { ([istarget powerpc*-*-*] ++ && ![istarget powerpc-*-linux*paired*]) ++ || [istarget rs6000-*-*] } { ++ # AltiVec is not supported on AIX before 5.3. ++ if { [istarget powerpc*-*-aix4*] ++ || [istarget powerpc*-*-aix5.1*] ++ || [istarget powerpc*-*-aix5.2*] } { ++ return 0 ++ } ++ return [check_no_compiler_messages powerpc_p8vector_ok object { ++ int main (void) { ++#ifdef __MACH__ ++ asm volatile ("xxlorc vs0,vs0,vs0"); ++#else ++ asm volatile ("xxlorc 0,0,0"); ++#endif ++ return 0; ++ } ++ } "-mpower8-vector"] ++ } else { ++ return 0 ++ } ++} ++ + # Return 1 if this is a PowerPC target supporting -mvsx + + proc check_effective_target_powerpc_vsx_ok { } { +@@ -2699,6 +2752,27 @@ + } + } + ++# Return 1 if this is a PowerPC target supporting -mhtm ++ ++proc check_effective_target_powerpc_htm_ok { } { ++ if { ([istarget powerpc*-*-*] ++ && ![istarget powerpc-*-linux*paired*]) ++ || [istarget rs6000-*-*] } { ++ # HTM is not supported on AIX yet. ++ if { [istarget powerpc*-*-aix*] } { ++ return 0 ++ } ++ return [check_no_compiler_messages powerpc_htm_ok object { ++ int main (void) { ++ asm volatile ("tbegin. 0"); ++ return 0; ++ } ++ } "-mhtm"] ++ } else { ++ return 0 ++ } ++} ++ + # Return 1 if this is a PowerPC target supporting -mcpu=cell. + + proc check_effective_target_powerpc_ppu_ok { } { +@@ -2794,6 +2868,22 @@ + } + } + ++# Return 1 if this is a PowerPC target using the ELFv2 ABI. ++ ++proc check_effective_target_powerpc_elfv2 { } { ++ if { [istarget powerpc*-*-*] } { ++ return [check_no_compiler_messages powerpc_elfv2 object { ++ #if _CALL_ELF != 2 ++ #error not ELF v2 ABI ++ #else ++ int dummy; ++ #endif ++ }] ++ } else { ++ return 0 ++ } ++} ++ + # Return 1 if this is a SPU target with a toolchain that + # supports automatic overlay generation. + +@@ -4499,6 +4589,7 @@ + switch $arg { + "vmx_hw" { set selected [check_vmx_hw_available] } + "vsx_hw" { set selected [check_vsx_hw_available] } ++ "p8vector_hw" { set selected [check_p8vector_hw_available] } + "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] } + "named_sections" { set selected [check_named_sections_available] } + "gc_sections" { set selected [check_gc_sections_available] } +@@ -4520,6 +4611,7 @@ + switch $arg { + "vmx_hw" { return 1 } + "vsx_hw" { return 1 } ++ "p8vector_hw" { return 1 } + "ppc_recip_hw" { return 1 } + "named_sections" { return 1 } + "gc_sections" { return 1 } +@@ -5077,7 +5169,9 @@ + } + + lappend DEFAULT_VECTCFLAGS "-maltivec" +- if [check_vsx_hw_available] { ++ if [check_p8vector_hw_available] { ++ lappend DEFAULT_VECTCFLAGS "-mpower8-vector" "-mno-allow-movmisalign" ++ } elseif [check_vsx_hw_available] { + lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign" + } + +--- a/src/gcc/testsuite/gcc.dg/vmx/3b-15.c ++++ b/src/gcc/testsuite/gcc.dg/vmx/3b-15.c +@@ -3,7 +3,11 @@ + vector unsigned char + f (vector unsigned char a, vector unsigned char b, vector unsigned char c) + { ++#ifdef __BIG_ENDIAN__ + return vec_perm(a,b,c); ++#else ++ return vec_perm(b,a,c); ++#endif + } + + static void test() +@@ -12,8 +16,13 @@ + 8,9,10,11,12,13,14,15}), + ((vector unsigned char){70,71,72,73,74,75,76,77, + 78,79,80,81,82,83,84,85}), ++#ifdef __BIG_ENDIAN__ + ((vector unsigned char){0x1,0x14,0x18,0x10,0x16,0x15,0x19,0x1a, + 0x1c,0x1c,0x1c,0x12,0x8,0x1d,0x1b,0xe})), ++#else ++ ((vector unsigned char){0x1e,0xb,0x7,0xf,0x9,0xa,0x6,0x5, ++ 0x3,0x3,0x3,0xd,0x17,0x2,0x4,0x11})), ++#endif + ((vector unsigned char){1,74,78,70,76,75,79,80,82,82,82,72,8,83,81,14})), + "f"); + } +--- a/src/gcc/testsuite/gcc.dg/vmx/vec-set.c ++++ b/src/gcc/testsuite/gcc.dg/vmx/vec-set.c +@@ -0,0 +1,14 @@ ++#include "harness.h" ++ ++vector short ++vec_set (short m) ++{ ++ return (vector short){m, 0, 0, 0, 0, 0, 0, 0}; ++} ++ ++static void test() ++{ ++ check (vec_all_eq (vec_set (7), ++ ((vector short){7, 0, 0, 0, 0, 0, 0, 0})), ++ "vec_set"); ++} +--- a/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c ++++ b/src/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c +@@ -13,12 +13,27 @@ + #define DO_INLINE __attribute__ ((always_inline)) + #define DONT_INLINE __attribute__ ((noinline)) + ++#ifdef __LITTLE_ENDIAN__ ++static inline DO_INLINE int inline_me(vector signed short data) ++{ ++ union {vector signed short v; signed short s[8];} u; ++ signed short x; ++ unsigned char x1, x2; ++ ++ u.v = data; ++ x = u.s[7]; ++ x1 = (x >> 8) & 0xff; ++ x2 = x & 0xff; ++ return ((x2 << 8) | x1); ++} ++#else + static inline DO_INLINE int inline_me(vector signed short data) + { + union {vector signed short v; signed short s[8];} u; + u.v = data; + return u.s[7]; + } ++#endif + + static DONT_INLINE int foo(vector signed short data) + { +--- a/src/gcc/testsuite/gcc.dg/vmx/eg-5.c ++++ b/src/gcc/testsuite/gcc.dg/vmx/eg-5.c +@@ -7,10 +7,17 @@ + /* Set result to a vector of f32 0's */ + vector float result = ((vector float){0.,0.,0.,0.}); + ++#ifdef __LITTLE_ENDIAN__ ++ result = vec_madd (c0, vec_splat (v, 3), result); ++ result = vec_madd (c1, vec_splat (v, 2), result); ++ result = vec_madd (c2, vec_splat (v, 1), result); ++ result = vec_madd (c3, vec_splat (v, 0), result); ++#else + result = vec_madd (c0, vec_splat (v, 0), result); + result = vec_madd (c1, vec_splat (v, 1), result); + result = vec_madd (c2, vec_splat (v, 2), result); + result = vec_madd (c3, vec_splat (v, 3), result); ++#endif + + return result; + } +--- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c ++++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c +@@ -38,7 +38,11 @@ + # endif + #elif defined (__powerpc64__) || defined (__ppc64__) || defined (__POWERPC64__) \ + || defined (__PPC64__) +-# define SIZE 180 ++# if _CALL_ELF == 2 ++# define SIZE 208 ++# else ++# define SIZE 180 ++# endif + #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) \ + || defined (__POWERPC__) || defined (PPC) || defined (_IBMR2) + # if defined (__ALTIVEC__) +--- a/src/gcc/testsuite/g++.dg/lookup/using9.C ++++ b/src/gcc/testsuite/g++.dg/lookup/using9.C +@@ -21,11 +21,11 @@ + f('h'); + f(1); // { dg-error "ambiguous" } + // { dg-message "candidate" "candidate note" { target *-*-* } 22 } +- void f(int); // { dg-error "previous using declaration" } ++ void f(int); // { dg-error "previous declaration" } + } + + void m() + { + void f(int); +- using B::f; // { dg-error "already declared" } ++ using B::f; // { dg-error "previous declaration" } + } +--- a/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C ++++ b/src/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C +@@ -0,0 +1,54 @@ ++// { dg-do run { target { powerpc64*-*-linux* } } } ++// { dg-options "-fexceptions -fnon-call-exceptions" } ++ ++#include ++#include ++#include ++ ++#define SET_CR(R,V) __asm__ __volatile__ ("mtcrf %0,%1" : : "n" (1<<(7-R)), "r" (V<<(4*(7-R))) : "cr" #R) ++#define GET_CR(R) ({ int tmp; __asm__ __volatile__ ("mfcr %0" : "=r" (tmp)); (tmp >> 4*(7-R)) & 15; }) ++ ++void sighandler (int signo, siginfo_t * si, void * uc) ++{ ++ SET_CR(2, 3); ++ SET_CR(3, 2); ++ SET_CR(4, 1); ++ ++ throw 0; ++} ++ ++float test (float a, float b) __attribute__ ((__noinline__)); ++float test (float a, float b) ++{ ++ float x; ++ asm ("mtcrf %1,%2" : "=f" (x) : "n" (1 << (7-3)), "r" (0), "0" (b) : "cr3"); ++ return a / x; ++} ++ ++int main () ++{ ++ struct sigaction sa; ++ int status; ++ ++ sa.sa_sigaction = sighandler; ++ sa.sa_flags = SA_SIGINFO; ++ ++ status = sigaction (SIGFPE, & sa, NULL); ++ ++ feenableexcept (FE_DIVBYZERO); ++ ++ SET_CR(2, 6); ++ SET_CR(3, 9); ++ SET_CR(4, 12); ++ ++ try { ++ test (1, 0); ++ } ++ catch (...) { ++ return GET_CR(2) != 6 || GET_CR(3) != 9 || GET_CR(4) != 12; ++ } ++ ++ return 1; ++} ++ ++ +--- a/src/gcc/testsuite/g++.dg/overload/using3.C ++++ b/src/gcc/testsuite/g++.dg/overload/using3.C +@@ -0,0 +1,16 @@ ++// { dg-do compile } ++ ++namespace a ++{ ++ void f(int); ++} ++ ++namespace b ++{ ++ void f(int); // { dg-message "previous" } ++ void g() ++ { ++ f (3); ++ } ++ using a::f; // { dg-error "conflicts" } ++} +--- a/src/gcc/testsuite/g++.dg/overload/using2.C ++++ b/src/gcc/testsuite/g++.dg/overload/using2.C +@@ -45,7 +45,7 @@ + extern "C" void exit (int) throw (); + extern "C" void *malloc (__SIZE_TYPE__) throw () __attribute__((malloc)); + +- void abort (void) throw (); ++ void abort (void) throw (); // { dg-message "previous" } + void _exit (int) throw (); // { dg-error "conflicts" "conflicts" } + // { dg-message "void _exit" "_exit" { target *-*-* } 49 } + +@@ -54,14 +54,14 @@ + // { dg-message "void C1" "C1" { target *-*-* } 53 } + + extern "C" void c2 (void) throw (); +- void C2 (void) throw (); ++ void C2 (void) throw (); // { dg-message "previous" } + + int C3 (int) throw (); + + using std::malloc; +-using std::abort; // { dg-error "already declared" } ++using std::abort; // { dg-error "conflicts" } + using std::c2; +-using std::C2; // { dg-error "already declared" } ++using std::C2; // { dg-error "conflicts" } + + using std::c3; using other::c3; + using std::C3; using other::C3; +--- a/src/gcc/cp/ChangeLog.ibm ++++ b/src/gcc/cp/ChangeLog.ibm +@@ -0,0 +1,11 @@ ++2013-08-04 Peter Bergner ++ ++ Back port from mainline ++ 2013-08-01 Fabien Chêne ++ ++ PR c++/54537 ++ * cp-tree.h: Check OVL_USED with OVERLOAD_CHECK. ++ * name-lookup.c (do_nonmember_using_decl): Make sure we have an ++ OVERLOAD before calling OVL_USED. Call diagnose_name_conflict ++ instead of issuing an error without mentioning the conflicting ++ declaration. +--- a/src/gcc/cp/cp-tree.h ++++ b/src/gcc/cp/cp-tree.h +@@ -331,7 +331,7 @@ + /* If set, this was imported in a using declaration. + This is not to confuse with being used somewhere, which + is not important for this node. */ +-#define OVL_USED(NODE) TREE_USED (NODE) ++#define OVL_USED(NODE) TREE_USED (OVERLOAD_CHECK (NODE)) + /* If set, this OVERLOAD was created for argument-dependent lookup + and can be freed afterward. */ + #define OVL_ARG_DEPENDENT(NODE) TREE_LANG_FLAG_0 (OVERLOAD_CHECK (NODE)) +--- a/src/gcc/cp/name-lookup.c ++++ b/src/gcc/cp/name-lookup.c +@@ -2268,8 +2268,7 @@ + && compparms (TYPE_ARG_TYPES (TREE_TYPE (fn)), + TYPE_ARG_TYPES (TREE_TYPE (decl))) + && ! decls_match (fn, decl)) +- error ("%q#D conflicts with previous using declaration %q#D", +- decl, fn); ++ diagnose_name_conflict (decl, fn); + + dup = duplicate_decls (decl, fn, is_friend); + /* If DECL was a redeclaration of FN -- even an invalid +@@ -2501,7 +2500,7 @@ + if (new_fn == old_fn) + /* The function already exists in the current namespace. */ + break; +- else if (OVL_USED (tmp1)) ++ else if (TREE_CODE (tmp1) == OVERLOAD && OVL_USED (tmp1)) + continue; /* this is a using decl */ + else if (compparms (TYPE_ARG_TYPES (TREE_TYPE (new_fn)), + TYPE_ARG_TYPES (TREE_TYPE (old_fn)))) +@@ -2516,7 +2515,7 @@ + break; + else + { +- error ("%qD is already declared in this scope", name); ++ diagnose_name_conflict (new_fn, old_fn); + break; + } + } +--- a/src/gcc/builtins.def ++++ b/src/gcc/builtins.def +@@ -252,6 +252,9 @@ + DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) ++DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) ++DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) ++DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) + DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) + DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) + DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) +--- a/src/gcc/expr.h ++++ b/src/gcc/expr.h +@@ -521,8 +521,8 @@ + rtx, int); + #endif + +-extern void locate_and_pad_parm (enum machine_mode, tree, int, int, tree, +- struct args_size *, ++extern void locate_and_pad_parm (enum machine_mode, tree, int, int, int, ++ tree, struct args_size *, + struct locate_and_pad_arg_data *); + + /* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */ +--- a/src/gcc/function.c ++++ b/src/gcc/function.c +@@ -2507,6 +2507,7 @@ + } + + locate_and_pad_parm (data->promoted_mode, data->passed_type, in_regs, ++ all->reg_parm_stack_space, + entry_parm ? data->partial : 0, current_function_decl, + &all->stack_args_size, &data->locate); + +@@ -3485,11 +3486,7 @@ + /* Adjust function incoming argument size for alignment and + minimum length. */ + +-#ifdef REG_PARM_STACK_SPACE +- crtl->args.size = MAX (crtl->args.size, +- REG_PARM_STACK_SPACE (fndecl)); +-#endif +- ++ crtl->args.size = MAX (crtl->args.size, all.reg_parm_stack_space); + crtl->args.size = CEIL_ROUND (crtl->args.size, + PARM_BOUNDARY / BITS_PER_UNIT); + +@@ -3693,6 +3690,9 @@ + IN_REGS is nonzero if the argument will be passed in registers. It will + never be set if REG_PARM_STACK_SPACE is not defined. + ++ REG_PARM_STACK_SPACE is the number of bytes of stack space reserved ++ for arguments which are passed in registers. ++ + FNDECL is the function in which the argument was defined. + + There are two types of rounding that are done. The first, controlled by +@@ -3713,19 +3713,16 @@ + + void + locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs, +- int partial, tree fndecl ATTRIBUTE_UNUSED, ++ int reg_parm_stack_space, int partial, ++ tree fndecl ATTRIBUTE_UNUSED, + struct args_size *initial_offset_ptr, + struct locate_and_pad_arg_data *locate) + { + tree sizetree; + enum direction where_pad; + unsigned int boundary, round_boundary; +- int reg_parm_stack_space = 0; + int part_size_in_regs; + +-#ifdef REG_PARM_STACK_SPACE +- reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl); +- + /* If we have found a stack parm before we reach the end of the + area reserved for registers, skip that area. */ + if (! in_regs) +@@ -3743,7 +3740,6 @@ + initial_offset_ptr->constant = reg_parm_stack_space; + } + } +-#endif /* REG_PARM_STACK_SPACE */ + + part_size_in_regs = (reg_parm_stack_space == 0 ? partial : 0); + +@@ -3806,11 +3802,7 @@ + + locate->slot_offset.constant += part_size_in_regs; + +- if (!in_regs +-#ifdef REG_PARM_STACK_SPACE +- || REG_PARM_STACK_SPACE (fndecl) > 0 +-#endif +- ) ++ if (!in_regs || reg_parm_stack_space > 0) + pad_to_arg_alignment (&locate->slot_offset, boundary, + &locate->alignment_pad); + +@@ -3830,11 +3822,7 @@ + pad_below (&locate->offset, passed_mode, sizetree); + + #else /* !ARGS_GROW_DOWNWARD */ +- if (!in_regs +-#ifdef REG_PARM_STACK_SPACE +- || REG_PARM_STACK_SPACE (fndecl) > 0 +-#endif +- ) ++ if (!in_regs || reg_parm_stack_space > 0) + pad_to_arg_alignment (initial_offset_ptr, boundary, + &locate->alignment_pad); + locate->slot_offset = *initial_offset_ptr; +@@ -5093,6 +5081,7 @@ + amount. BLKmode results are handled using the group load/store + machinery. */ + if (TYPE_MODE (TREE_TYPE (decl_result)) != BLKmode ++ && REG_P (real_decl_rtl) + && targetm.calls.return_in_msb (TREE_TYPE (decl_result))) + { + emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl), +--- a/src/gcc/ChangeLog.ibm ++++ b/src/gcc/ChangeLog.ibm +@@ -0,0 +1,2429 @@ ++2013-11-24 Bill Schmidt ++ ++ Backport from mainline r205333 ++ 2013-11-24 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Correct ++ for little endian. ++ ++2013-11-23 Alan Modra ++ ++ Apply mainline r205299. ++ * config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX. ++ ++2013-11-22 Michael Meissner ++ ++ Backport from mainline ++ 2013-11-12 Michael Meissner ++ ++ PR target/59054 ++ * config/rs6000/rs6000.md (movdi_internal32): Eliminate ++ constraints that would allow DImode into the traditional Altivec ++ registers, but cause undesirable code generation when loading 0 as ++ a constant. ++ (movdi_internal64): Likewise. ++ (cmp_fpr): Do not use %x for CR register output. ++ (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and ++ -mallow-upper-sf debug switches are used. ++ ++2013-11-21 Bill Schmidt ++ ++ Backport from mainline r205241 ++ 2013-11-21 Bill Schmidt ++ ++ * config/rs6000/vector.md (vec_pack_trunc_v2df): Revert previous ++ little endian change. ++ (vec_pack_sfix_trunc_v2df): Likewise. ++ (vec_pack_ufix_trunc_v2df): Likewise. ++ * config/rs6000/rs6000.c (rs6000_expand_interleave): Correct ++ double checking of endianness. ++ ++2013-11-21 Peter Bergner ++ ++ Backport from mainline r205233. ++ 2013-11-21 Peter Bergner ++ ++ * doc/extend.texi: Document htm builtins. ++ ++2013-11-20 Bill Schmidt ++ ++ Backport from mainline r205146 ++ 2013-11-20 Bill Schmidt ++ ++ * config/rs6000/vsx.md (vsx_set_): Adjust for little endian. ++ (vsx_extract_): Likewise. ++ (*vsx_extract__one_le): New LE variant on ++ *vsx_extract__zero. ++ (vsx_extract_v4sf): Adjust for little endian. ++ ++2013-11-20 Ulrich Weigand ++ ++ Backport from mainline r205123: ++ ++ 2013-11-20 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not ++ allow subregs of TDmode in FPRs of smaller size in little-endian. ++ (rs6000_split_multireg_move): When splitting an access to TDmode ++ in FPRs, do not use simplify_gen_subreg. ++ ++2013-11-19 Bill Schmidt ++ ++ Backport from mainline r205080 ++ 2013-11-19 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Adjust ++ V16QI vector splat case for little endian. ++ ++2013-11-20 Alan Modra ++ ++ Apply mainline r205060. ++ * config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty. ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Default ++ to strict alignment on older processors when little-endian. ++ * config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8 ++ for ELFv2. ++ ++2013-11-19 Ulrich Weigand ++ ++ Backport from mainline r205045: ++ ++ 2013-11-19 Ulrich Weigand ++ ++ * config/rs6000/vector.md ("mov"): Do not call ++ rs6000_emit_le_vsx_move to move into or out of GPRs. ++ * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Assert ++ source and destination are not GPR hard regs. ++ ++2013-11-18 Peter Bergner ++ ++ Merge up to 204974. ++ * REVISION: Update subversion id. ++ ++2013-11-17 Ulrich Weigand ++ ++ Backport from mainline r204927: ++ ++ 2013-11-17 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_emit_move): Use low word of ++ sdmode_stack_slot also in little-endian mode. ++ ++2013-11-17 Bill Schmidt ++ ++ Backport from mainline r204920 ++ 2011-11-17 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (rs6000_frame_related): Add split_reg ++ parameter and use it in REG_FRAME_RELATED_EXPR note. ++ (emit_frame_save): Call rs6000_frame_related with extra NULL_RTX ++ parameter. ++ (rs6000_emit_prologue): Likewise, but for little endian VSX ++ stores, pass the source register of the store instead. ++ ++2013-11-15 Bill Schmidt ++ ++ Backport from mainline r204862 ++ 2013-11-15 Bill Schmidt ++ ++ * config/rs6000/altivec.md (UNSPEC_VPERM_X, UNSPEC_VPERM_UNS_X): ++ Remove. ++ (altivec_vperm_): Revert earlier little endian change. ++ (*altivec_vperm__internal): Remove. ++ (altivec_vperm__uns): Revert earlier little endian change. ++ (*altivec_vperm__uns_internal): Remove. ++ * config/rs6000/vector.md (vec_realign_load_): Revise ++ commentary. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204842: ++ ++ 2013-11-15 Ulrich Weigand ++ ++ * doc/invoke.texi (-mabi=elfv1, -mabi=elfv2): Document. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204809: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/sysv4le.h (LINUX64_DEFAULT_ABI_ELFv2): Define. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204808: ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * config/rs6000/rs6000.h (RS6000_SAVE_AREA): Handle ABI_ELFv2. ++ (RS6000_SAVE_TOC): Remove. ++ (RS6000_TOC_SAVE_SLOT): New macro. ++ * config/rs6000/rs6000.c (rs6000_parm_offset): New function. ++ (rs6000_parm_start): Use it. ++ (rs6000_function_arg_advance_1): Likewise. ++ (rs6000_emit_prologue): Use RS6000_TOC_SAVE_SLOT. ++ (rs6000_emit_epilogue): Likewise. ++ (rs6000_call_aix): Likewise. ++ (rs6000_output_function_prologue): Do not save/restore r11 ++ around calling _mcount for ABI_ELFv2. ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * config/rs6000/rs6000-protos.h (rs6000_reg_parm_stack_space): ++ Add prototype. ++ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Remove. ++ (REG_PARM_STACK_SPACE): Call rs6000_reg_parm_stack_space. ++ * config/rs6000/rs6000.c (rs6000_parm_needs_stack): New function. ++ (rs6000_function_parms_need_stack): Likewise. ++ (rs6000_reg_parm_stack_space): Likewise. ++ (rs6000_function_arg): Do not replace BLKmode by Pmode when ++ returning a register argument. ++ ++ 2013-11-14 Ulrich Weigand ++ Michael Gschwind ++ ++ * config/rs6000/rs6000.h (FP_ARG_MAX_RETURN): New macro. ++ (ALTIVEC_ARG_MAX_RETURN): Likewise. ++ (FUNCTION_VALUE_REGNO_P): Use them. ++ * config/rs6000/rs6000.c (TARGET_RETURN_IN_MSB): Define. ++ (rs6000_return_in_msb): New function. ++ (rs6000_return_in_memory): Handle ELFv2 homogeneous aggregates. ++ Handle aggregates of up to 16 bytes for ELFv2. ++ (rs6000_function_value): Handle ELFv2 homogeneous aggregates. ++ ++ 2013-11-14 Ulrich Weigand ++ Michael Gschwind ++ ++ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define. ++ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function. ++ (rs6000_discover_homogeneous_aggregate): Likewise. ++ (rs6000_function_arg_boundary): Handle homogeneous aggregates. ++ (rs6000_function_arg_advance_1): Likewise. ++ (rs6000_function_arg): Likewise. ++ (rs6000_arg_partial_bytes): Likewise. ++ (rs6000_psave_function_arg): Handle BLKmode arguments. ++ ++ 2013-11-14 Ulrich Weigand ++ Michael Gschwind ++ ++ * config/rs6000/rs6000.h (AGGR_ARG_NUM_REG): Define. ++ * config/rs6000/rs6000.c (rs6000_aggregate_candidate): New function. ++ (rs6000_discover_homogeneous_aggregate): Likewise. ++ (rs6000_function_arg_boundary): Handle homogeneous aggregates. ++ (rs6000_function_arg_advance_1): Likewise. ++ (rs6000_function_arg): Likewise. ++ (rs6000_arg_partial_bytes): Likewise. ++ (rs6000_psave_function_arg): Handle BLKmode arguments. ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (machine_function): New member ++ r2_setup_needed. ++ (rs6000_emit_prologue): Set r2_setup_needed if necessary. ++ (rs6000_output_mi_thunk): Set r2_setup_needed. ++ (rs6000_output_function_prologue): Output global entry point ++ prologue and local entry point marker if needed for ABI_ELFv2. ++ Output -mprofile-kernel code here. ++ (output_function_profiler): Do not output -mprofile-kernel ++ code here; moved to rs6000_output_function_prologue. ++ (rs6000_file_start): Output ".abiversion 2" for ABI_ELFv2. ++ ++ (rs6000_emit_move): Do not handle dot symbols for ABI_ELFv2. ++ (rs6000_output_function_entry): Likewise. ++ (rs6000_assemble_integer): Likewise. ++ (rs6000_elf_encode_section_info): Likewise. ++ (rs6000_elf_declare_function_name): Do not create dot symbols ++ or .opd section for ABI_ELFv2. ++ ++ (rs6000_trampoline_size): Update for ABI_ELFv2 trampolines. ++ (rs6000_trampoline_init): Likewise. ++ (rs6000_elf_file_end): Call file_end_indicate_exec_stack ++ for ABI_ELFv2. ++ ++ (rs6000_call_aix): Handle ELFv2 indirect calls. Do not check ++ for function descriptors in ABI_ELFv2. ++ ++ * config/rs6000/rs6000.md ("*call_indirect_aix"): Support ++ on ABI_AIX only, not ABI_ELFv2. ++ ("*call_value_indirect_aix"): Likewise. ++ ("*call_indirect_elfv2"): New pattern. ++ ("*call_value_indirect_elfv2"): Likewise. ++ ++ * config/rs6000/predicates.md ("symbol_ref_operand"): Do not ++ check for function descriptors in ABI_ELFv2. ++ ("current_file_function_operand"): Likewise. ++ ++ * config/rs6000/ppc-asm.h [__powerpc64__ && _CALL_ELF == 2]: ++ (toc): Undefine. ++ (FUNC_NAME): Define ELFv2 variant. ++ (JUMP_TARGET): Likewise. ++ (FUNC_START): Likewise. ++ (HIDDEN_FUNC): Likewise. ++ (FUNC_END): Likeiwse. ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config.gcc [powerpc*-*-* | rs6000-*-*]: Support --with-abi=elfv1 ++ and --with-abi=elfv2. ++ * config/rs6000/option-defaults.h (OPTION_DEFAULT_SPECS): Add "abi". ++ * config/rs6000/rs6000.opt (mabi=elfv1): New option. ++ (mabi=elfv2): Likewise. ++ * config/rs6000/rs6000-opts.h (enum rs6000_abi): Add ABI_ELFv2. ++ * config/rs6000/linux64.h (DEFAULT_ABI): Do not hard-code to AIX_ABI ++ if !RS6000_BI_ARCH. ++ (ELFv2_ABI_CHECK): New macro. ++ (SUBSUBTARGET_OVERRIDE_OPTIONS): Use it to decide whether to set ++ rs6000_current_abi to ABI_AIX or ABI_ELFv2. ++ (GLIBC_DYNAMIC_LINKER64): Support ELFv2 ld.so version. ++ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Predefine ++ _CALL_ELF and __STRUCT_PARM_ALIGN__ if appropriate. ++ ++ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Handle ABI_ELFv2. ++ (debug_stack_info): Likewise. ++ (rs6000_file_start): Treat ABI_ELFv2 the same as ABI_AIX. ++ (rs6000_legitimize_tls_address): Likewise. ++ (rs6000_conditional_register_usage): Likewise. ++ (rs6000_emit_move): Likewise. ++ (init_cumulative_args): Likewise. ++ (rs6000_function_arg_advance_1): Likewise. ++ (rs6000_function_arg): Likewise. ++ (rs6000_arg_partial_bytes): Likewise. ++ (rs6000_output_function_entry): Likewise. ++ (rs6000_assemble_integer): Likewise. ++ (rs6000_savres_strategy): Likewise. ++ (rs6000_stack_info): Likewise. ++ (rs6000_function_ok_for_sibcall): Likewise. ++ (rs6000_emit_load_toc_table): Likewise. ++ (rs6000_savres_routine_name): Likewise. ++ (ptr_regno_for_savres): Likewise. ++ (rs6000_emit_prologue): Likewise. ++ (rs6000_emit_epilogue): Likewise. ++ (rs6000_output_function_epilogue): Likewise. ++ (output_profile_hook): Likewise. ++ (output_function_profiler): Likewise. ++ (rs6000_trampoline_size): Likewise. ++ (rs6000_trampoline_init): Likewise. ++ (rs6000_elf_output_toc_section_asm_op): Likewise. ++ (rs6000_elf_encode_section_info): Likewise. ++ (rs6000_elf_reloc_rw_mask): Likewise. ++ (rs6000_elf_declare_function_name): Likewise. ++ (rs6000_function_arg_boundary): Treat ABI_ELFv2 the same as ABI_AIX, ++ except that rs6000_compat_align_parm is always assumed false. ++ (rs6000_gimplify_va_arg): Likewise. ++ (rs6000_call_aix): Update comment. ++ (rs6000_sibcall_aix): Likewise. ++ * config/rs6000/rs6000.md ("tls_gd_aix"): ++ Treat ABI_ELFv2 the same as ABI_AIX. ++ ("*tls_gd_call_aix"): Likewise. ++ ("tls_ld_aix"): Likewise. ++ ("*tls_ld_call_aix"): Likewise. ++ ("load_toc_aix_si"): Likewise. ++ ("load_toc_aix_di"): Likewise. ++ ("call"): Likewise. ++ ("call_value"): Likewise. ++ ("*call_local_aix"): Likewise. ++ ("*call_value_local_aix"): Likewise. ++ ("*call_nonlocal_aix"): Likewise. ++ ("*call_value_nonlocal_aix"): Likewise. ++ ("*call_indirect_aix"): Likewise. ++ ("*call_value_indirect_aix"): Likewise. ++ ("sibcall"): Likewise. ++ ("sibcall_value"): Likewise. ++ ("*sibcall_aix"): Likewise. ++ ("*sibcall_value_aix"): Likewise. ++ * config/rs6000/predicates.md ("symbol_ref_operand"): Likewise. ++ ("current_file_function_operand"): Likewise. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204807: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_arg_partial_bytes): Simplify logic ++ by making use of the fact that for vector / floating point arguments ++ passed both in VRs/FPRs and in the fixed parameter area, the partial ++ bytes mechanism is in fact not used. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204806: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_psave_function_arg): New function. ++ (rs6000_finish_function_arg): Likewise. ++ (rs6000_function_arg): Use rs6000_psave_function_arg and ++ rs6000_finish_function_arg to handle both vector and floating ++ point arguments that are also passed in GPRs / the stack. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204805: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (USE_FP_FOR_ARG_P): Remove TYPE argument. ++ (USE_ALTIVEC_FOR_ARG_P): Likewise. ++ (rs6000_darwin64_record_arg_advance_recurse): Update uses. ++ (rs6000_function_arg_advance_1):Likewise. ++ (rs6000_darwin64_record_arg_recurse): Likewise. ++ (rs6000_function_arg): Likewise. ++ (rs6000_arg_partial_bytes): Likewise. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204804: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Replace ++ "DEFAULT_ABI != ABI_AIX" test by testing for ABI_V4 or ABI_DARWIN. ++ (rs6000_savres_strategy): Likewise. ++ (rs6000_return_addr): Likewise. ++ (rs6000_emit_load_toc_table): Replace "DEFAULT_ABI != ABI_AIX" by ++ testing for ABI_V4 (since ABI_DARWIN is impossible here). ++ (rs6000_emit_prologue): Likewise. ++ (legitimate_lo_sum_address_p): Simplify DEFAULT_ABI test. ++ (rs6000_elf_declare_function_name): Remove duplicated test. ++ * config/rs6000/rs6000.md ("load_toc_v4_PIC_1"): Explicitly test ++ for ABI_V4 (instead of "DEFAULT_ABI != ABI_AIX" test). ++ ("load_toc_v4_PIC_1_normal"): Likewise. ++ ("load_toc_v4_PIC_1_476"): Likewise. ++ ("load_toc_v4_PIC_1b"): Likewise. ++ ("load_toc_v4_PIC_1b_normal"): Likewise. ++ ("load_toc_v4_PIC_1b_476"): Likewise. ++ ("load_toc_v4_PIC_2"): Likewise. ++ ("load_toc_v4_PIC_3b"): Likewise. ++ ("load_toc_v4_PIC_3c"): Likewise. ++ * config/rs6000/rs6000.h (RS6000_REG_SAVE): Simplify DEFAULT_ABI test. ++ (RS6000_SAVE_AREA): Likewise. ++ (FP_ARG_MAX_REG): Likewise. ++ (RETURN_ADDRESS_OFFSET): Likewise. ++ * config/rs6000/sysv.h (TARGET_TOC): Test for ABI_V4 instead ++ of ABI_AIX. ++ (SUBTARGET_OVERRIDE_OPTIONS): Likewise. ++ (MINIMAL_TOC_SECTION_ASM_OP): Likewise. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204803: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_call_indirect_aix): Rename to ... ++ (rs6000_call_aix): ... this. Handle both direct and indirect calls. ++ Create call insn directly instead of via various gen_... routines. ++ Mention special registers used by the call in CALL_INSN_FUNCTION_USAGE. ++ (rs6000_sibcall_aix): New function. ++ * config/rs6000/rs6000.md (TOC_SAVE_OFFSET_32BIT): Remove. ++ (TOC_SAVE_OFFSET_64BIT): Likewise. ++ (AIX_FUNC_DESC_TOC_32BIT): Likewise. ++ (AIX_FUNC_DESC_TOC_64BIT): Likewise. ++ (AIX_FUNC_DESC_SC_32BIT): Likewise. ++ (AIX_FUNC_DESC_SC_64BIT): Likewise. ++ ("call" expander): Call rs6000_call_aix. ++ ("call_value" expander): Likewise. ++ ("call_indirect_aix"): Replace this pattern ... ++ ("call_indirect_aix_nor11"): ... and this pattern ... ++ ("*call_indirect_aix"): ... by this insn pattern. ++ ("call_value_indirect_aix"): Replace this pattern ... ++ ("call_value_indirect_aix_nor11"): ... and this pattern ... ++ ("*call_value_indirect_aix"): ... by this insn pattern. ++ ("*call_nonlocal_aix32", "*call_nonlocal_aix64"): Replace by ... ++ ("*call_nonlocal_aix"): ... this pattern. ++ ("*call_value_nonlocal_aix32", "*call_value_nonlocal_aix64"): Replace ++ ("*call_value_nonlocal_aix"): ... by this pattern. ++ ("*call_local_aix"): New insn pattern. ++ ("*call_value_local_aix"): Likewise. ++ ("sibcall" expander): Call rs6000_sibcall_aix. ++ ("sibcall_value" expander): Likewise. Move earlier in file. ++ ("*sibcall_nonlocal_aix"): Replace by ... ++ ("*sibcall_aix"): ... this pattern. ++ ("*sibcall_value_nonlocal_aix"): Replace by ... ++ ("*sibcall_value_aix"): ... this pattern. ++ * config/rs6000/rs6000-protos.h (rs6000_call_indirect_aix): Remove. ++ (rs6000_call_aix): Add prototype. ++ (rs6000_sibcall_aix): Likewise. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204799: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * config/rs6000/rs6000.c (rs6000_emit_prologue): Do not place a ++ RTX_FRAME_RELATED_P marker on the UNSPEC_MOVESI_FROM_CR insn. ++ Instead, add USEs of all modified call-saved CR fields to the ++ insn storing the result to the stack slot, and provide an ++ appropriate REG_FRAME_RELATED_EXPR for that insn. ++ * config/rs6000/rs6000.md ("*crsave"): New insn pattern. ++ * config/rs6000/predicates.md ("crsave_operation"): New predicate. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204798: ++ ++ 2013-11-14 Ulrich Weigand ++ Alan Modra ++ ++ * function.c (assign_parms): Use all.reg_parm_stack_space instead ++ of re-evaluating REG_PARM_STACK_SPACE target macro. ++ (locate_and_pad_parm): New parameter REG_PARM_STACK_SPACE. Use it ++ instead of evaluating target macro REG_PARM_STACK_SPACE every time. ++ (assign_parm_find_entry_rtl): Update call. ++ * calls.c (initialize_argument_information): Update call. ++ (emit_library_call_value_1): Likewise. ++ * expr.h (locate_and_pad_parm): Update prototype. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r204797: ++ ++ 2013-11-14 Ulrich Weigand ++ ++ * calls.c (store_unaligned_arguments_into_pseudos): Skip PARALLEL ++ arguments. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r197003: ++ ++ 2013-03-23 Eric Botcazou ++ ++ * calls.c (expand_call): Add missing guard to code handling return ++ of non-BLKmode structures in MSB. ++ * function.c (expand_function_end): Likewise. ++ ++2013-11-15 Ulrich Weigand ++ ++ Backport from mainline r201750. ++ Note: Default setting of -mcompat-align-parm inverted! ++ ++ 2013-08-14 Bill Schmidt ++ ++ PR target/57949 ++ * doc/invoke.texi: Add documentation of mcompat-align-parm ++ option. ++ * config/rs6000/rs6000.opt: Add mcompat-align-parm option. ++ * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX ++ and Linux, correct BLKmode alignment when 128-bit alignment is ++ required and compatibility flag is not set. ++ (rs6000_gimplify_va_arg): For AIX and Linux, honor specified ++ alignment for zero-size arguments when compatibility flag is not ++ set. ++ ++2013-11-12 Bill Schmidt ++ ++ * configure: Regenerate. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204441 ++ 2013-11-05 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): ++ Remove restriction against use of VSX instructions when generating ++ code for little endian mode. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204440 ++ 2013-11-05 Bill Schmidt ++ ++ * config/rs6000/altivec.md (mulv4si3): Ensure we generate vmulouh ++ for both big and little endian. ++ (mulv8hi3): Swap input operands for merge high and merge low ++ instructions for little endian. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204439 ++ 2013-11-05 Bill Schmidt ++ ++ * config/rs6000/altivec.md (vec_widen_umult_even_v16qi): Change ++ define_insn to define_expand that uses even patterns for big ++ endian and odd patterns for little endian. ++ (vec_widen_smult_even_v16qi): Likewise. ++ (vec_widen_umult_even_v8hi): Likewise. ++ (vec_widen_smult_even_v8hi): Likewise. ++ (vec_widen_umult_odd_v16qi): Likewise. ++ (vec_widen_smult_odd_v16qi): Likewise. ++ (vec_widen_umult_odd_v8hi): Likewise. ++ (vec_widen_smult_odd_v8hi): Likewise. ++ (altivec_vmuleub): New define_insn. ++ (altivec_vmuloub): Likewise. ++ (altivec_vmulesb): Likewise. ++ (altivec_vmulosb): Likewise. ++ (altivec_vmuleuh): Likewise. ++ (altivec_vmulouh): Likewise. ++ (altivec_vmulesh): Likewise. ++ (altivec_vmulosh): Likewise. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204395 ++ 2013-11-05 Bill Schmidt ++ ++ * config/rs6000/vector.md (vec_pack_sfix_trunc_v2df): Adjust for ++ little endian. ++ (vec_pack_ufix_trunc_v2df): Likewise. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204363 ++ 2013-11-04 Bill Schmidt ++ ++ * config/rs6000/altivec.md (vec_widen_umult_hi_v16qi): Swap ++ arguments to merge instruction for little endian. ++ (vec_widen_umult_lo_v16qi): Likewise. ++ (vec_widen_smult_hi_v16qi): Likewise. ++ (vec_widen_smult_lo_v16qi): Likewise. ++ (vec_widen_umult_hi_v8hi): Likewise. ++ (vec_widen_umult_lo_v8hi): Likewise. ++ (vec_widen_smult_hi_v8hi): Likewise. ++ (vec_widen_smult_lo_v8hi): Likewise. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204350 ++ 2013-11-04 Bill Schmidt ++ ++ * config/rs6000/vsx.md (*vsx_le_perm_store_ for VSX_D): ++ Replace the define_insn_and_split with a define_insn and two ++ define_splits, with the split after reload re-permuting the source ++ register to its original value. ++ (*vsx_le_perm_store_ for VSX_W): Likewise. ++ (*vsx_le_perm_store_v8hi): Likewise. ++ (*vsx_le_perm_store_v16qi): Likewise. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204321 ++ 2013-11-04 Bill Schmidt ++ ++ * config/rs6000/vector.md (vec_pack_trunc_v2df): Adjust for ++ little endian. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r204321 ++ 2013-11-02 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (rs6000_expand_vector_set): Adjust for ++ little endian. ++ ++2013-11-10 Bill Schmidt ++ ++ Backport from mainline r203980 ++ 2013-10-23 Bill Schmidt ++ ++ * config/rs6000/altivec.md (mulv8hi3): Adjust for little endian. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203930 ++ 2013-10-22 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse ++ meaning of merge-high and merge-low masks for little endian; avoid ++ use of vector-pack masks for little endian for mismatched modes. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203877 ++ 2013-10-20 Bill Schmidt ++ ++ * config/rs6000/altivec.md (vec_unpacku_hi_v16qi): Adjust for ++ little endian. ++ (vec_unpacku_hi_v8hi): Likewise. ++ (vec_unpacku_lo_v16qi): Likewise. ++ (vec_unpacku_lo_v8hi): Likewise. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203863 ++ 2013-10-19 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (vspltis_constant): Make sure we check ++ all elements for both endian flavors. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203714 ++ 2013-10-16 Bill Schmidt ++ ++ * gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for ++ endianness. ++ (vec_unpacks_lo_v4sf): Likewise. ++ (vec_unpacks_float_hi_v4si): Likewise. ++ (vec_unpacks_float_lo_v4si): Likewise. ++ (vec_unpacku_float_hi_v4si): Likewise. ++ (vec_unpacku_float_lo_v4si): Likewise. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203713 ++ 2013-10-16 Bill Schmidt ++ ++ * config/rs6000/vsx.md (vsx_concat_): Adjust output for LE. ++ (vsx_concat_v2sf): Likewise. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203458 ++ 2013-10-11 Bill Schmidt ++ ++ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to ++ handle vector float as well. ++ (*vsx_le_perm_load_v4si): Likewise. ++ (*vsx_le_perm_store_v2di): Likewise. ++ (*vsx_le_perm_store_v4si): Likewise. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203457 ++ 2013-10-11 Bill Schmidt ++ ++ * config/rs6000/vector.md (vec_realign_load): Generate vperm ++ directly to circumvent subtract from splat{31} workaround. ++ * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_le): New ++ prototype. ++ * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): New. ++ * config/rs6000/altivec.md (define_c_enum "unspec"): Add ++ UNSPEC_VPERM_X and UNSPEC_VPERM_UNS_X. ++ (altivec_vperm_): Convert to define_insn_and_split to ++ separate big and little endian logic. ++ (*altivec_vperm__internal): New define_insn. ++ (altivec_vperm__uns): Convert to define_insn_and_split to ++ separate big and little endian logic. ++ (*altivec_vperm__uns_internal): New define_insn. ++ (vec_permv16qi): Add little endian logic. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203247 ++ 2013-10-07 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const_le): New. ++ (altivec_expand_vec_perm_const): Call it. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r203246 ++ 2013-10-07 Bill Schmidt ++ ++ * config/rs6000/vector.md (mov): Emit permuted move ++ sequences for LE VSX loads and stores at expand time. ++ * config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_move): New ++ prototype. ++ * config/rs6000/rs6000.c (rs6000_const_vec): New. ++ (rs6000_gen_le_vsx_permute): New. ++ (rs6000_gen_le_vsx_load): New. ++ (rs6000_gen_le_vsx_store): New. ++ (rs6000_gen_le_vsx_move): New. ++ * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): New. ++ (*vsx_le_perm_load_v4si): New. ++ (*vsx_le_perm_load_v8hi): New. ++ (*vsx_le_perm_load_v16qi): New. ++ (*vsx_le_perm_store_v2di): New. ++ (*vsx_le_perm_store_v4si): New. ++ (*vsx_le_perm_store_v8hi): New. ++ (*vsx_le_perm_store_v16qi): New. ++ (*vsx_xxpermdi2_le_): New. ++ (*vsx_xxpermdi4_le_): New. ++ (*vsx_xxpermdi8_le_V8HI): New. ++ (*vsx_xxpermdi16_le_V16QI): New. ++ (*vsx_lxvd2x2_le_): New. ++ (*vsx_lxvd2x4_le_): New. ++ (*vsx_lxvd2x8_le_V8HI): New. ++ (*vsx_lxvd2x16_le_V16QI): New. ++ (*vsx_stxvd2x2_le_): New. ++ (*vsx_stxvd2x4_le_): New. ++ (*vsx_stxvd2x8_le_V8HI): New. ++ (*vsx_stxvd2x16_le_V16QI): New. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r201235 ++ 2013-07-24 Bill Schmidt ++ Anton Blanchard ++ ++ * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian. ++ (altivec_vpksss): Likewise. ++ (altivec_vpksus): Likewise. ++ (altivec_vpkuus): Likewise. ++ (altivec_vpkuum): Likewise. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r201208 ++ 2013-07-24 Bill Schmidt ++ Anton Blanchard ++ ++ * config/rs6000/vector.md (vec_realign_load_): Reorder input ++ operands to vperm for little endian. ++ * config/rs6000/rs6000.c (rs6000_expand_builtin): Use lvsr instead ++ of lvsl to create the control mask for a vperm for little endian. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r201195 ++ 2013-07-23 Bill Schmidt ++ Anton Blanchard ++ ++ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse ++ two operands for little-endian. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r201193 ++ 2013-07-23 Bill Schmidt ++ Anton Blanchard ++ ++ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct ++ selection of field for vector splat in little endian mode. ++ ++2013-11-08 Bill Schmidt ++ ++ Backport from mainline r201149 ++ 2013-07-22 Bill Schmidt ++ Anton Blanchard ++ ++ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix ++ endianness when selecting field to splat. ++ ++2013-10-21 Bill Schmidt ++ ++ Backport from mainline ++ 2013-04-05 Bill Schmidt ++ ++ PR target/56843 ++ * config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove. ++ (rs6000_emit_swdiv_low_precision): Remove. ++ (rs6000_emit_swdiv): Rewrite to handle between one and four ++ iterations of Newton-Raphson generally; modify required number of ++ iterations for some cases. ++ * config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove. ++ ++2013-10-17 Michael Meissner ++ ++ Backport from mainline ++ 2013-10-17 Michael Meissner ++ ++ * config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new ++ fields to the reg_addr array that describes the valid addressing ++ mode for any register, general purpose registers, floating point ++ registers, and Altivec registers. ++ (FIRST_RELOAD_REG_CLASS): Likewise. ++ (LAST_RELOAD_REG_CLASS): Likewise. ++ (struct reload_reg_map_type): Likewise. ++ (reload_reg_map_type): Likewise. ++ (RELOAD_REG_VALID): Likewise. ++ (RELOAD_REG_MULTIPLE): Likewise. ++ (RELOAD_REG_INDEXED): Likewise. ++ (RELOAD_REG_OFFSET): Likewise. ++ (RELOAD_REG_PRE_INCDEC): Likewise. ++ (RELOAD_REG_PRE_MODIFY): Likewise. ++ (reg_addr): Likewise. ++ (mode_supports_pre_incdec_p): New helper functions to say whether ++ a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY. ++ (mode_supports_pre_modify_p): Likewise. ++ (rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to ++ print the valid address mode bits for each mode. ++ (rs6000_debug_print_mode): Likewise. ++ (rs6000_debug_reg_global): Likewise. ++ (rs6000_setup_reg_addr_masks): New function to set up the address ++ mask bits for each type. ++ (rs6000_init_hard_regno_mode_ok): Use memset to clear arrays. ++ Call rs6000_setup_reg_addr_masks to set up the address mask bits. ++ (rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and ++ mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and ++ PRE_MODIFY are supported. ++ (rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec ++ registers, instead of {src,dest}_av_p. ++ (rs6000_print_options_internal): Tweak the debug output slightly. ++ ++ Backport from mainline ++ 2013-10-03 Michael Meissner ++ ++ * config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2, ++ ceildf2, btruncdf2, instead of vsx_* name. ++ ++ * config/rs6000/vsx.md (vsx_add3): Change arithmetic ++ iterators to only do V2DF and V4SF here. Move the DF code to ++ rs6000.md where it is combined with SF mode. Replace with ++ just 'v' since only vector operations are handled with these insns ++ after moving the DF support to rs6000.md. ++ (vsx_sub3): Likewise. ++ (vsx_mul3): Likewise. ++ (vsx_div3): Likewise. ++ (vsx_fre2): Likewise. ++ (vsx_neg2): Likewise. ++ (vsx_abs2): Likewise. ++ (vsx_nabs2): Likewise. ++ (vsx_smax3): Likewise. ++ (vsx_smin3): Likewise. ++ (vsx_sqrt2): Likewise. ++ (vsx_rsqrte2): Likewise. ++ (vsx_fms4): Likewise. ++ (vsx_nfma4): Likewise. ++ (vsx_copysign3): Likewise. ++ (vsx_btrunc2): Likewise. ++ (vsx_floor2): Likewise. ++ (vsx_ceil2): Likewise. ++ (vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md. ++ (vsx_sminsf3): Likewise. ++ (vsx_fmadf4): Likewise. ++ (vsx_fmsdf4): Likewise. ++ (vsx_nfmadf4): Likewise. ++ (vsx_nfmsdf4): Likewise. ++ (vsx_cmpdf_internal1): Likewise. ++ ++ * config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it ++ simpler to select whether a target has SPE or traditional floating ++ point support in iterators. ++ (TARGET_DF_SPE): Likewise. ++ (TARGET_SF_FPR): Likewise. ++ (TARGET_DF_FPR): Likewise. ++ (TARGET_SF_INSN): Macros to say whether floating point support ++ exists for a given operation for expanders. ++ (TARGET_DF_INSN): Likewise. ++ ++ * config/rs6000/rs6000.c (Ftrad): New mode attributes to allow ++ combining of SF/DF mode operations, using both traditional and VSX ++ registers. ++ (Fvsx): Likewise. ++ (Ff): Likewise. ++ (Fv): Likewise. ++ (Fs): Likewise. ++ (Ffre): Likewise. ++ (FFRE): Likewise. ++ (abs2): Combine SF/DF modes using traditional floating point ++ instructions. Add support for using the upper DF registers with ++ VSX support, and SF registers with power8-vector support. Update ++ expanders for operations supported by both the SPE and traditional ++ floating point units. ++ (abs2_fpr): Likewise. ++ (nabs2): Likewise. ++ (nabs2_fpr): Likewise. ++ (neg2): Likewise. ++ (neg2_fpr): Likewise. ++ (add3): Likewise. ++ (add3_fpr): Likewise. ++ (sub3): Likewise. ++ (sub3_fpr): Likewise. ++ (mul3): Likewise. ++ (mul3_fpr): Likewise. ++ (div3): Likewise. ++ (div3_fpr): Likewise. ++ (sqrt3): Likewise. ++ (sqrt3_fpr): Likewise. ++ (fre): Likewise. ++ (rsqrt2): Likewise. ++ (cmp_fpr): Likewise. ++ (smax3): Likewise. ++ (smin3): Likewise. ++ (smax3_vsx): Likewise. ++ (smin3_vsx): Likewise. ++ (negsf2): Delete SF operations that are merged with DF. ++ (abssf2): Likewise. ++ (addsf3): Likewise. ++ (subsf3): Likewise. ++ (mulsf3): Likewise. ++ (divsf3): Likewise. ++ (fres): Likewise. ++ (fmasf4_fpr): Likewise. ++ (fmssf4_fpr): Likewise. ++ (nfmasf4_fpr): Likewise. ++ (nfmssf4_fpr): Likewise. ++ (sqrtsf2): Likewise. ++ (rsqrtsf_internal1): Likewise. ++ (smaxsf3): Likewise. ++ (sminsf3): Likewise. ++ (cmpsf_internal1): Likewise. ++ (copysign3_fcpsgn): Add VSX/power8-vector support. ++ (negdf2): Delete DF operations that are merged with SF. ++ (absdf2): Likewise. ++ (nabsdf2): Likewise. ++ (adddf3): Likewise. ++ (subdf3): Likewise. ++ (muldf3): Likewise. ++ (divdf3): Likewise. ++ (fred): Likewise. ++ (rsqrtdf_internal1): Likewise. ++ (fmadf4_fpr): Likewise. ++ (fmsdf4_fpr): Likewise. ++ (nfmadf4_fpr): Likewise. ++ (nfmsdf4_fpr): Likewise. ++ (sqrtdf2): Likewise. ++ (smaxdf3): Likewise. ++ (smindf3): Likewise. ++ (cmpdf_internal1): Likewise. ++ (lrintdi2): Use TARGET__FPR macro. ++ (btrunc2): Delete separate expander, and combine with the ++ insn and add VSX instruction support. Use TARGET__FPR. ++ (btrunc2_fpr): Likewise. ++ (ceil2): Likewise. ++ (ceil2_fpr): Likewise. ++ (floor2): Likewise. ++ (floor2_fpr): Likewise. ++ (fma4_fpr): Combine SF and DF fused multiply/add support. ++ Add support for using the upper registers with VSX and ++ power8-vector. Move insns to be closer to the define_expands. On ++ VSX systems, prefer the traditional form of FMA over the VSX ++ version, since the traditional form allows the target not to ++ overlap with the inputs. ++ (fms4_fpr): Likewise. ++ (nfma4_fpr): Likewise. ++ (nfms4_fpr): Likewise. ++ ++ Backport from mainline ++ 2013-09-27 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow ++ DFmode, DImode, and SFmode in the upper VSX registers based on the ++ -mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS ++ if -mpower8-vector. Combine -mvsx-timode handling with the rest ++ of the VSX register handling. ++ ++ * config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters. ++ (f32_sv): Likewise. ++ (zero_extendsidi2_lfiwzx): Add support for loading into the ++ Altivec registers with -mpower8-vector. Use wu/wv constraints to ++ only do VSX memory options on Altivec registers. ++ (extendsidi2_lfiwax): Likewise. ++ (extendsfdf2_fpr): Likewise. ++ (mov_hardfloat, SF/SD modes): Likewise. ++ (mov_hardfloat32, DF/DD modes): Likewise. ++ (mov_hardfloat64, DF/DD modes): Likewise. ++ (movdi_internal64): Likewise. ++ ++ Backport from mainline ++ 2013-09-23 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine ++ reload helper function arrays into a single array reg_addr. ++ (reload_fpr_gpr): Likewise. ++ (reload_gpr_vsx): Likewise. ++ (reload_vsx_gpr): Likewise. ++ (struct rs6000_reg_addr): Likewise. ++ (reg_addr): Likewise. ++ (rs6000_debug_reg_global): Change rs6000_vector_reload, ++ reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr. ++ (rs6000_init_hard_regno_mode_ok): Likewise. ++ (rs6000_secondary_reload_direct_move): Likewise. ++ (rs6000_secondary_reload): Likewise. ++ ++ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new ++ constraints: wu, ww, and wy. Repurpose wv constraint added during ++ power8 changes. Put wg constraint in alphabetical order. ++ ++ * config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch ++ for future work to add ISA 2.07 VSX single precision support. ++ (-mvsx-scalar-double): Change default from -1 to 1, update ++ documentation comment. ++ (-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df. ++ (-mupper-regs-df): New debug switch to control whether DF values ++ can go in the traditional Altivec registers. ++ (-mupper-regs-sf): New debug switch to control whether SF values ++ can go in the traditional Altivec registers. ++ ++ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww, ++ and wy constraints. ++ (rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for ++ loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df. ++ Add new constraints, wu/ww/wy. Repurpose wv constraint. ++ (rs6000_debug_legitimate_address_p): Print if we are running ++ before, during, or after reload. ++ (rs6000_secondary_reload): Add a comment. ++ (rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf. ++ ++ * config/rs6000/constraints.md (wa constraint): Sort w ++ constraints. Update documentation string. ++ (wd constraint): Likewise. ++ (wf constraint): Likewise. ++ (wg constraint): Likewise. ++ (wn constraint): Likewise. ++ (ws constraint): Likewise. ++ (wt constraint): Likewise. ++ (wx constraint): Likewise. ++ (wz constraint): Likewise. ++ (wu constraint): New constraint for ISA 2.07 SFmode scalar ++ instructions. ++ (ww constraint): Likewise. ++ (wy constraint): Likewise. ++ (wv constraint): Repurpose ISA 2.07 constraint that did not use in ++ the previous submissions. ++ * doc/md.texi (PowerPC and IBM RS6000): Likewise. ++ ++ Backport from mainline ++ 2013-10-17 Michael Meissner ++ ++ PR target/58673 ++ * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only ++ restrict TImode addresses to single indirect registers if both ++ -mquad-memory and -mvsx-timode are used. ++ (rs6000_output_move_128bit): Use quad_load_store_p to determine if ++ we should emit load/store quad. Remove using %y for quad memory ++ addresses. ++ ++ * config/rs6000/rs6000.md (mov_ppc64, TI/PTImode): Add ++ constraints to allow load/store quad on machines where TImode is ++ not allowed in VSX registers. Use 'n' instead of 'F' constraint ++ for TImode to load integer constants. ++ ++2013-10-02 Michael Meissner ++ ++ Backport from mainline ++ 2013-10-02 Michael Meissner ++ ++ PR target/58587 ++ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off ++ setting -mvsx-timode by default until the underlying problem is ++ fixed. ++ (RS6000_CPU, power7 defaults): Likewise. ++ ++2013-08-19 Peter Bergner ++ ++ Backport from mainline ++ 2013-08-19 Peter Bergner ++ Jakub Jelinek ++ ++ * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin. ++ (BUILT_IN_FABSD64): Likewise. ++ (BUILT_IN_FABSD128): Likewise. ++ * builtins.c (expand_builtin): Add support for ++ new DFP ABS builtins. ++ (fold_builtin_1): Likewise. ++ * config/rs6000/dfp.md ++ (*negtd2_fpr): Handle ++ non-overlapping destination ++ and source operands. ++ (*abstd2_fpr): ++ Likewise. ++ (*nabstd2_fpr): ++ Likewise. ++ ++2013-08-16 Michael Meissner ++ ++ Backport from trunk ++ 2013-08-16 Michael Meissner ++ ++ PR target/58160 ++ * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the ++ memory rtx to contain ZERO_EXTEND and SIGN_EXTEND. ++ ++ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands ++ array instead of each individual operand as a separate argument. ++ (emit_fusion_gpr_load): Likewise. ++ (expand_fusion_gpr_load): Add new function declaration. ++ ++ * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling ++ signature to have the operands passed as an array, instead of as ++ separate arguments. Allow ZERO_EXTEND to be in the memory ++ address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not ++ depend on the register live/dead flags when peepholes are run. ++ (expand_fusion_gpr_load): New function to be called from the ++ peephole2 pass, to change the register that addis sets to be the ++ target register. ++ (emit_fusion_gpr_load): Change the calling signature to have the ++ operands passed as an array, instead of as separate arguments. ++ Allow ZERO_EXTEND to be in the memory address, and also ++ SIGN_EXTEND if -mpower8-fusion-sign. ++ ++ * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused ++ unspec enumeration. ++ (power8 fusion peephole/peephole2): Rework the fusion peepholes to ++ adjust the register addis loads up in the peephole2 pass. Do not ++ depend on the register live/dead state when the peephole pass is ++ done. ++ ++ Backport from trunk ++ 2013-07-23 Michael Meissner ++ ++ * config/rs6000/vector.md (xor3): Move 128-bit boolean ++ expanders to rs6000.md. ++ (ior3): Likewise. ++ (and3): Likewise. ++ (one_cmpl2): Likewise. ++ (nor3): Likewise. ++ (andc3): Likewise. ++ (eqv3): Likewise. ++ (nand3): Likewise. ++ (orc3): Likewise. ++ ++ * config/rs6000/rs6000-protos.h (rs6000_split_logical): New ++ declaration. ++ ++ * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support ++ to split multi-word logical operations. ++ (rs6000_split_logical_di): Likewise. ++ (rs6000_split_logical): Likewise. ++ ++ * config/rs6000/vsx.md (VSX_L2): Delete, no longer used. ++ (vsx_and3_32bit): Move 128-bit logical insns to rs6000.md, ++ and allow TImode operations in 32-bit. ++ (vsx_and3_64bit): Likewise. ++ (vsx_ior3_32bit): Likewise. ++ (vsx_ior3_64bit): Likewise. ++ (vsx_xor3_32bit): Likewise. ++ (vsx_xor3_64bit): Likewise. ++ (vsx_one_cmpl2_32bit): Likewise. ++ (vsx_one_cmpl2_64bit): Likewise. ++ (vsx_nor3_32bit): Likewise. ++ (vsx_nor3_64bit): Likewise. ++ (vsx_andc3_32bit): Likewise. ++ (vsx_andc3_64bit): Likewise. ++ (vsx_eqv3_32bit): Likewise. ++ (vsx_eqv3_64bit): Likewise. ++ (vsx_nand3_32bit): Likewise. ++ (vsx_nand3_64bit): Likewise. ++ (vsx_orc3_32bit): Likewise. ++ (vsx_orc3_64bit): Likewise. ++ ++ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector ++ logical types in GPRs. ++ ++ * config/rs6000/altivec.md (altivec_and3): Move 128-bit ++ logical insns to rs6000.md, and allow TImode operations in ++ 32-bit. ++ (altivec_ior3): Likewise. ++ (altivec_xor3): Likewise. ++ (altivec_one_cmpl2): Likewise. ++ (altivec_nor3): Likewise. ++ (altivec_andc3): Likewise. ++ ++ * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode ++ attributes for moving the 128-bit logical operations into ++ rs6000.md. ++ (BOOL_REGS_OUTPUT): Likewise. ++ (BOOL_REGS_OP1): Likewise. ++ (BOOL_REGS_OP2): Likewise. ++ (BOOL_REGS_UNARY): Likewise. ++ (BOOL_REGS_AND_CR0): Likewise. ++ (one_cmpl2): Add support for DI logical operations on ++ 32-bit, splitting the operations to 32-bit. ++ (anddi3): Likewise. ++ (iordi3): Likewise. ++ (xordi3): Likewise. ++ (and3, 128-bit types): Rewrite 2013-06-06 logical operator ++ changes to combine the 32/64-bit code, allow logical operations on ++ TI mode in 32-bit, and to use similar match_operator patterns like ++ scalar mode uses. Combine the Altivec and VSX code for logical ++ operations, and move it here. ++ (ior3, 128-bit types): Likewise. ++ (xor3, 128-bit types): Likewise. ++ (one_cmpl3, 128-bit types): Likewise. ++ (nor3, 128-bit types): Likewise. ++ (andc3, 128-bit types): Likewise. ++ (eqv3, 128-bit types): Likewise. ++ (nand3, 128-bit types): Likewise. ++ (orc3, 128-bit types): Likewise. ++ (and3_internal): Likewise. ++ (bool3_internal): Likewise. ++ (boolc3_internal1): Likewise. ++ (boolc3_internal2): Likewise. ++ (boolcc3_internal1): Likewise. ++ (boolcc3_internal2): Likewise. ++ (eqv3_internal1): Likewise. ++ (eqv3_internal2): Likewise. ++ (one_cmpl13_internal): Likewise. ++ ++2013-07-31 Michael Meissner ++ ++ Backport from mainline ++ 2013-07-31 Michael Meissner ++ ++ * config/rs6000/predicates.md (fusion_gpr_addis): New predicates ++ to support power8 load fusion. ++ (fusion_gpr_mem_load): Likewise. ++ ++ * config/rs6000/rs6000-modes.def (PTImode): Update a comment. ++ ++ * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New ++ declarations for power8 load fusion. ++ (emit_fusion_gpr_load): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): If ++ tuning for power8, turn on fusion mode by default. Turn on sign ++ extending fusion mode if normal fusion mode is on, and we are at ++ -O2 or -O3. ++ (fusion_gpr_load_p): New function, return true if we can fuse an ++ addis instruction with a dependent load to a GPR. ++ (emit_fusion_gpr_load): Emit the instructions for power8 load ++ fusion to GPRs. ++ ++ * config/rs6000/vsx.md (VSX_M2): New iterator for fusion ++ peepholes. ++ (VSX load fusion peepholes): New peepholes to fuse together an ++ addi instruction with a VSX load instruction. ++ ++ * config/rs6000/rs6000.md (GPR load fusion peepholes): New ++ peepholes to fuse an addis instruction with a load to a GPR base ++ register. If we are supporting sign extending fusions, convert ++ sign extending loads to zero extending loads and add an explicit ++ sign extension. ++ ++2013-07-19 Pat Haugen ++ ++ Backport from mainline ++ 2013-07-18 Pat Haugen ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag ++ interaction for new Power8 flags and VSX. ++ ++2013-07-17 Peter Bergner ++ ++ Backport from mainline ++ 2013-07-17 Iain Sandoe ++ ++ * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers. ++ ++2013-07-16 Peter Bergner ++ ++ Merge up to 200989. ++ * REVISION: Update subversion id. ++ ++2013-07-16 Peter Bergner ++ ++ Backport from mainline ++ 2013-07-16 Peter Bergner ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not ++ enable extra ISA flags with TARGET_HTM. ++ ++ 2013-07-16 Jakub Jelinek ++ Peter Bergner ++ ++ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM ++ registers in the comment. ++ (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers. ++ (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS ++ rather than FIRST_PSEUDO_REGISTERS. ++ ++2013-07-15 Peter Bergner ++ ++ Backport from mainline ++ 2013-07-15 Peter Bergner ++ ++ * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h. ++ * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md. ++ * config/rs6000/rs6000.opt: Add -mhtm option. ++ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM. ++ (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM. ++ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define ++ __HTM__ if the HTM instructions are available. ++ * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand, ++ htm_spr_reg_operand): New define_predicates. ++ * config/rs6000/rs6000.md (define_attr "type"): Add htm. ++ (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants. ++ Include htm.md. ++ * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2, ++ BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining ++ HTM builtin functions. ++ * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro. ++ (rs6000_reg_names, alt_reg_names): Add HTM SPR register names. ++ (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions. ++ (rs6000_builtin_mask_calculate): Likewise. ++ (rs6000_option_override_internal): Likewise. ++ (bdesc_htm): Add new HTM builtin support. ++ (htm_spr_num): New function. ++ (htm_spr_regno): Likewise. ++ (rs6000_htm_spr_icode): Likewise. ++ (htm_expand_builtin): Likewise. ++ (htm_init_builtins): Likewise. ++ (rs6000_expand_builtin): Add support for HTM builtin functions. ++ (rs6000_init_builtins): Likewise. ++ (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option. ++ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm. ++ (TARGET_HTM, MASK_HTM): Define macros. ++ (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers. ++ (FIXED_REGISTERS): Likewise. ++ (CALL_USED_REGISTERS): Likewise. ++ (CALL_REALLY_USED_REGISTERS): Likewise. ++ (REG_ALLOC_ORDER): Likewise. ++ (enum reg_class): Likewise. ++ (REG_CLASS_NAMES): Likewise. ++ (REG_CLASS_CONTENTS): Likewise. ++ (REGISTER_NAMES): Likewise. ++ (ADDITIONAL_REGISTER_NAMES): Likewise. ++ (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT, ++ RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros. ++ (RS6000_BTM_COMMON): Add RS6000_BTM_HTM. ++ * config/rs6000/htm.md: New file. ++ * config/rs6000/htmintrin.h: New file. ++ * config/rs6000/htmxlintrin.h: New file. ++ ++2013-06-28 Michael Meissner ++ ++ Back port from the trunk ++ 2013-06-28 Michael Meissner ++ ++ PR target/57744 ++ * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode ++ to tie with any other modes. Eliminate Altivec vector mode tests, ++ since these are a subset of ALTIVEC or VSX vector modes. Simplify ++ code, to return 0 if testing MODE2 for a condition, if we've ++ already tested MODE1 for the same condition. ++ ++2013-06-28 Pat Haugen ++ ++ * config/rs6000/rs6000.md (define_insn ""): Fix insn type. ++ ++2013-06-26 Pat Haugen ++ ++ Back port from the trunk ++ 2013-06-26 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * config/rs6000/power8.md: New. ++ * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor ++ setting for power8 entry. ++ * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md. ++ * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust ++ test for Power4/Power5 only. ++ (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8 ++ support. ++ (force_new_group): Adjust comment. ++ * config/rs6000/rs6000.md: Include power8.md. ++ ++2013-06-14 Michael Meissner ++ ++ Back port from the trunk ++ 2013-06-14 Michael Meissner ++ ++ PR target/57615 ++ * config/rs6000/rs6000.md (mov_ppc64): Call ++ rs6000_output_move_128bit to handle emitting quad memory ++ operations. Set attribute length to 8 bytes. ++ ++2013-06-13 Michael Meissner ++ ++ Back port from the trunk ++ 2013-06-13 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Move ++ test for clearing quad memory on 32-bit later. ++ ++2013-06-12 Michael Meissner ++ ++ Back port from the trunk ++ ++ Backport from mainline ++ 2013-06-12 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * config/rs6000/rs6000.c (emit_load_locked): Add support for ++ power8 byte, half-word, and quad-word atomic instructions. ++ (emit_store_conditional): Likewise. ++ (rs6000_expand_atomic_compare_and_swap): Likewise. ++ (rs6000_expand_atomic_op): Likewise. ++ ++ * config/rs6000/sync.md (larx): Add new modes for power8. ++ (stcx): Likewise. ++ (AINT): New mode iterator to include TImode as well as normal ++ integer modes on power8. ++ (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so ++ that VSX registers are not considered. Use AINT mode iterator ++ instead of INT1 to allow inclusion of quad word atomic operations ++ on power8. ++ (load_locked): Likewise. ++ (store_conditional): Likewise. ++ (atomic_compare_and_swap): Likewise. ++ (atomic_exchange): Likewise. ++ (atomic_nand): Likewise. ++ (atomic_fetch_): Likewise. ++ (atomic_nand_fetch): Likewise. ++ (mem_thread_fence): Use gen_loadsync_ instead of enumerating ++ each type. ++ (ATOMIC): On power8, add QImode, HImode modes. ++ (load_locked_si): Varients of load_locked for QI/HI ++ modes that promote to SImode. ++ (load_lockedti): Convert TImode arguments to PTImode, so that we ++ get a guaranteed even/odd register pair. ++ (load_lockedpti): Likewise. ++ (store_conditionalti): Likewise. ++ (store_conditionalpti): Likewise. ++ ++ * config/rs6000/rs6000.md (QHI): New mode iterator for power8 ++ atomic load/store instructions. ++ (HSI): Likewise. ++ ++2013-06-11 Michael Meissner ++ ++ Back port from the trunk ++ ++ 2013-06-11 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * config/rs6000/rs6000.c (emit_load_locked): Add support for ++ power8 byte, half-word, and quad-word atomic instructions. ++ (emit_store_conditional): Likewise. ++ (rs6000_expand_atomic_compare_and_swap): Likewise. ++ (rs6000_expand_atomic_op): Likewise. ++ ++ * config/rs6000/sync.md (larx): Add new modes for power8. ++ (stcx): Likewise. ++ (AINT): New mode iterator to include TImode as well as normal ++ integer modes on power8. ++ (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so ++ that VSX registers are not considered. Use AINT mode iterator ++ instead of INT1 to allow inclusion of quad word atomic operations ++ on power8. ++ (load_locked): Likewise. ++ (store_conditional): Likewise. ++ (atomic_compare_and_swap): Likewise. ++ (atomic_exchange): Likewise. ++ (atomic_nand): Likewise. ++ (atomic_fetch_): Likewise. ++ (atomic_nand_fetch): Likewise. ++ (mem_thread_fence): Use gen_loadsync_ instead of enumerating ++ each type. ++ (ATOMIC): On power8, add QImode, HImode modes. ++ (load_locked_si): Varients of load_locked for QI/HI ++ modes that promote to SImode. ++ (load_lockedti): Convert TImode arguments to PTImode, so that we ++ get a guaranteed even/odd register pair. ++ (load_lockedpti): Likewise. ++ (store_conditionalti): Likewise. ++ (store_conditionalpti): Likewise. ++ ++ * config/rs6000/rs6000.md (QHI): New mode iterator for power8 ++ atomic load/store instructions. ++ (HSI): Likewise. ++ ++ PR target/57589 ++ * config/rs6000/driver-rs6000.c (elf_platform): Make buffer static ++ to allow returning address to AT_PLATFORM name. ++ ++ Back port from the trunk ++ ++ 2013-06-10 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * config/rs6000/vector.md (GPR move splitter): Do not split moves ++ of vectors in GPRS if they are direct moves or quad word load or ++ store moves. ++ ++ * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add ++ declaration. ++ (direct_move_p): Likewise. ++ (quad_load_store_p): Likewise. ++ ++ * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register ++ classes into bins based on the physical register type. ++ (reg_class_to_reg_type): Likewise. ++ (IS_STD_REG_TYPE): Likewise. ++ (IS_FP_VECT_REG_TYPE): Likewise. ++ (reload_fpr_gpr): Arrays to determine what insn to use if we can ++ use direct move instructions. ++ (reload_gpr_vsx): Likewise. ++ (reload_vsx_gpr): Likewise. ++ (rs6000_init_hard_regno_mode_ok): Precalculate the register type ++ information that is a simplification of register classes. Also ++ precalculate direct move reload helpers. ++ (direct_move_p): New function to return true if the operation can ++ be done as a direct move instruciton. ++ (quad_load_store_p): New function to return true if the operation ++ is a quad memory operation. ++ (rs6000_legitimize_address): If quad memory, only allow register ++ indirect for TImode addresses. ++ (rs6000_legitimate_address_p): Likewise. ++ (enum reload_reg_type): Delete, replace with rs6000_reg_type. ++ (rs6000_reload_register_type): Likewise. ++ (register_to_reg_type): Return register type. ++ (rs6000_secondary_reload_simple_move): New helper function for ++ secondary reload and secondary memory needed to identify anything ++ that is a simple move, and does not need reloading. ++ (rs6000_secondary_reload_direct_move): New helper function for ++ secondary reload to identify cases that can be done with several ++ instructions via the direct move instructions. ++ (rs6000_secondary_reload_move): New helper function for secondary ++ reload to identify moves between register types that can be done. ++ (rs6000_secondary_reload): Add support for quad memory operations ++ and for direct move. ++ (rs6000_secondary_memory_needed): Likewise. ++ (rs6000_debug_secondary_memory_needed): Change argument names. ++ (rs6000_output_move_128bit): New function to return the move to ++ use for 128-bit moves, including knowing about the various ++ limitations of quad memory operations. ++ ++ * config/rs6000/vsx.md (vsx_mov): Add support for quad ++ memory operations. call rs6000_output_move_128bit for the actual ++ instruciton(s) to generate. ++ (vsx_movti_64bit): Likewise. ++ ++ * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values. ++ (UNSPEC_P8V_MTVSRWZ): Likewise. ++ (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise. ++ (UNSPEC_P8V_MTVSRD): Likewise. ++ (UNSPEC_P8V_XXPERMDI): Likewise. ++ (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise. ++ (UNSPEC_FUSION_GPR): Likewise. ++ (FMOVE128_GPR): New iterator for direct move. ++ (f32_lv): New mode attribute for load/store of SFmode/SDmode ++ values. ++ (f32_sv): Likewise. ++ (f32_dm): Likewise. ++ (zero_extenddi2_internal1): Add support for power8 32-bit ++ loads and direct move instructions. ++ (zero_extendsidi2_lfiwzx): Likewise. ++ (extendsidi2_lfiwax): Likewise. ++ (extendsidi2_nocell): Likewise. ++ (floatsi2_lfiwax): Likewise. ++ (lfiwax): Likewise. ++ (floatunssi2_lfiwzx): Likewise. ++ (lfiwzx): Likewise. ++ (fix_trunc_stfiwx): Likewise. ++ (fixuns_trunc_stfiwx): Likewise. ++ (mov_hardfloat, 32-bit floating point): Likewise. ++ (mov_hardfloat64, 64-bit floating point): Likewise. ++ (parity2_cmpb): Set length/type attr. ++ (unnamed shift right patterns, mov_internal2): Change type attr ++ for 'mr.' to fast_compare. ++ (bpermd_): Change type attr to popcnt. ++ (p8_fmrgow_): New insns for power8 direct move support. ++ (p8_mtvsrwz_1): Likewise. ++ (p8_mtvsrwz_2): Likewise. ++ (reload_fpr_from_gpr): Likewise. ++ (p8_mtvsrd_1): Likewise. ++ (p8_mtvsrd_2): Likewise. ++ (p8_xxpermdi_): Likewise. ++ (reload_vsx_from_gpr): Likewise. ++ (reload_vsx_from_gprsf): Likewise. ++ (p8_mfvsrd_3_): LIkewise. ++ (reload_gpr_from_vsx): Likewise. ++ (reload_gpr_from_vsxsf): Likewise. ++ (p8_mfvsrd_4_disf): Likewise. ++ (multi-word GPR splits): Do not split direct moves or quad memory ++ operations. ++ ++2013-06-06 Michael Meissner ++ ++ Backport from the trunk ++ ++ 2013-06-06 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): ++ Document new power8 builtins. ++ ++ * config/rs6000/vector.md (and3): Add a clobber/scratch of a ++ condition code register, to allow 128-bit logical operations to be ++ done in the VSX or GPR registers. ++ (nor3): Use the canonical form for nor. ++ (eqv3): Add expanders for power8 xxleqv, xxlnand, xxlorc, ++ vclz*, and vpopcnt* vector instructions. ++ (nand3): Likewise. ++ (orc3): Likewise. ++ (clz2): LIkewise. ++ (popcount2): Likewise. ++ ++ * config/rs6000/predicates.md (int_reg_operand): Rework tests so ++ that only the GPRs are recognized. ++ ++ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add ++ support for new power8 builtins. ++ ++ * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8 ++ builtin functions. ++ (xscvdpspn): Likewise. ++ (vclz): Likewise. ++ (vclzb): Likewise. ++ (vclzh): Likewise. ++ (vclzw): Likewise. ++ (vclzd): Likewise. ++ (vpopcnt): Likewise. ++ (vpopcntb): Likewise. ++ (vpopcnth): Likewise. ++ (vpopcntw): Likewise. ++ (vpopcntd): Likewise. ++ (vgbbd): Likewise. ++ (vmrgew): Likewise. ++ (vmrgow): Likewise. ++ (eqv): Likewise. ++ (eqv_v16qi3): Likewise. ++ (eqv_v8hi3): Likewise. ++ (eqv_v4si3): Likewise. ++ (eqv_v2di3): Likewise. ++ (eqv_v4sf3): Likewise. ++ (eqv_v2df3): Likewise. ++ (nand): Likewise. ++ (nand_v16qi3): Likewise. ++ (nand_v8hi3): Likewise. ++ (nand_v4si3): Likewise. ++ (nand_v2di3): Likewise. ++ (nand_v4sf3): Likewise. ++ (nand_v2df3): Likewise. ++ (orc): Likewise. ++ (orc_v16qi3): Likewise. ++ (orc_v8hi3): Likewise. ++ (orc_v4si3): Likewise. ++ (orc_v2di3): Likewise. ++ (orc_v4sf3): Likewise. ++ (orc_v2df3): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Only ++ allow power8 quad mode in 64-bit. ++ (rs6000_builtin_vectorized_function): Add support to vectorize ++ ISA 2.07 count leading zeros, population count builtins. ++ (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form ++ V4SF vectors instead of xscvdpsp to avoid IEEE related traps. ++ (builtin_function_type): Add vgbbd builtin function which takes an ++ unsigned argument. ++ (altivec_expand_vec_perm_const): Add support for new power8 merge ++ instructions. ++ ++ * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types, ++ that does not include TImdoe for use with 32-bit. ++ (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn ++ instructions. ++ (UNSPEC_VSX_CVDPSPN): Likewise. ++ (vsx_xscvdpspn): Likewise. ++ (vsx_xscvspdpn): Likewise. ++ (vsx_xscvdpspn_scalar): Likewise. ++ (vsx_xscvspdpn_directmove): Likewise. ++ (vsx_and3): Split logical operations into 32-bit and ++ 64-bit. Add support to do logical operations on TImode as well as ++ VSX vector types. Allow logical operations to be done in either ++ VSX registers or in general purpose registers in 64-bit mode. Add ++ splitters if GPRs were used. For AND, add clobber of CCmode to ++ allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL ++ encoding. ++ (vsx_and3_32bit): Likewise. ++ (vsx_and3_64bit): Likewise. ++ (vsx_ior3): Likewise. ++ (vsx_ior3_32bit): Likewise. ++ (vsx_ior3_64bit): Likewise. ++ (vsx_xor3): Likewise. ++ (vsx_xor3_32bit): Likewise. ++ (vsx_xor3_64bit): Likewise. ++ (vsx_one_cmpl2): Likewise. ++ (vsx_one_cmpl2_32bit): Likewise. ++ (vsx_one_cmpl2_64bit): Likewise. ++ (vsx_nor3): Likewise. ++ (vsx_nor3_32bit): Likewise. ++ (vsx_nor3_64bit): Likewise. ++ (vsx_andc3): Likewise. ++ (vsx_andc3_32bit): Likewise. ++ (vsx_andc3_64bit): Likewise. ++ (vsx_eqv3_32bit): Add support for power8 xxleqv, xxlnand, ++ and xxlorc instructions. ++ (vsx_eqv3_64bit): Likewise. ++ (vsx_nand3_32bit): Likewise. ++ (vsx_nand3_64bit): Likewise. ++ (vsx_orc3_32bit): Likewise. ++ (vsx_orc3_64bit): Likewise. ++ ++ * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment. ++ ++ * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd ++ instruction. ++ (p8_vmrgew): Add power8 vmrgew and vmrgow instructions. ++ (p8_vmrgow): Likewise. ++ (altivec_and3): Add clobber of CCmode to allow AND using ++ GPRs to be split under VSX. ++ (p8v_clz2): Add power8 count leading zero support. ++ (p8v_popcount2): Add power8 population count support. ++ (p8v_vgbbd): Add power8 gather bits by bytes by doubleword ++ support. ++ ++ * config/rs6000/rs6000.md (eqv3): Add support for powerp eqv ++ instruction. ++ ++ * config/rs6000/altivec.h (vec_eqv): Add defines to export power8 ++ builtin functions. ++ (vec_nand): Likewise. ++ (vec_vclz): Likewise. ++ (vec_vclzb): Likewise. ++ (vec_vclzd): Likewise. ++ (vec_vclzh): Likewise. ++ (vec_vclzw): Likewise. ++ (vec_vgbbd): Likewise. ++ (vec_vmrgew): Likewise. ++ (vec_vmrgow): Likewise. ++ (vec_vpopcnt): Likewise. ++ (vec_vpopcntb): Likewise. ++ (vec_vpopcntd): Likewise. ++ (vec_vpopcnth): Likewise. ++ (vec_vpopcntw): Likewise. ++ ++2013-06-06 Peter Bergner ++ ++ Merge up to 199753. ++ * REVISION: Update subversion id. ++ ++2013-06-06 Peter Bergner ++ ++ Backport from trunk ++ ++ 2013-05-29 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI ++ instructions. ++ (VEC_A): Likewise. ++ (VEC_C): Likewise. ++ (vrotl3): Likewise. ++ (vashl3): Likewise. ++ (vlshr3): Likewise. ++ (vashr3): Likewise. ++ ++ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add ++ support for power8 V2DI builtins. ++ ++ * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for ++ power8 V2DI builtins. ++ (vupkhsw): Likewise. ++ (vupklsw): Likewise. ++ (vaddudm): Likewise. ++ (vminsd): Likewise. ++ (vmaxsd): Likewise. ++ (vminud): Likewise. ++ (vmaxud): Likewise. ++ (vpkudum): Likewise. ++ (vpksdss): Likewise. ++ (vpkudus): Likewise. ++ (vpksdus): Likewise. ++ (vrld): Likewise. ++ (vsld): Likewise. ++ (vsrd): Likewise. ++ (vsrad): Likewise. ++ (vsubudm): Likewise. ++ (vcmpequd): Likewise. ++ (vcmpgtsd): Likewise. ++ (vcmpgtud): Likewise. ++ (vcmpequd_p): Likewise. ++ (vcmpgtsd_p): Likewise. ++ (vcmpgtud_p): Likewise. ++ (vupkhsw): Likewise. ++ (vupklsw): Likewise. ++ (vaddudm): Likewise. ++ (vmaxsd): Likewise. ++ (vmaxud): Likewise. ++ (vminsd): Likewise. ++ (vminud): Likewise. ++ (vpksdss): Likewise. ++ (vpksdus): Likewise. ++ (vpkudum): Likewise. ++ (vpkudus): Likewise. ++ (vrld): Likewise. ++ (vsld): Likewise. ++ (vsrad): Likewise. ++ (vsrd): Likewise. ++ (vsubudm): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add ++ support for power8 V2DI instructions. ++ ++ * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for ++ power8 V2DI instructions. Combine pack and unpack insns to use an ++ iterator for each mode. Check whether a particular mode supports ++ Altivec instructions instead of just checking TARGET_ALTIVEC. ++ (UNSPEC_VPKUWUM): Likewise. ++ (UNSPEC_VPKSHSS): Likewise. ++ (UNSPEC_VPKSWSS): Likewise. ++ (UNSPEC_VPKUHUS): Likewise. ++ (UNSPEC_VPKSHUS): Likewise. ++ (UNSPEC_VPKUWUS): Likewise. ++ (UNSPEC_VPKSWUS): Likewise. ++ (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise. ++ (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise. ++ (UNSPEC_VPACK_UNS_UNS_SAT): Likewise. ++ (UNSPEC_VPACK_UNS_UNS_MOD): Likewise. ++ (UNSPEC_VUPKHSB): Likewise. ++ (UNSPEC_VUNPACK_HI_SIGN): Likewise. ++ (UNSPEC_VUNPACK_LO_SIGN): Likewise. ++ (UNSPEC_VUPKHSH): Likewise. ++ (UNSPEC_VUPKLSB): Likewise. ++ (UNSPEC_VUPKLSH): Likewise. ++ (VI2): Likewise. ++ (VI_char): Likewise. ++ (VI_scalar): Likewise. ++ (VI_unit): Likewise. ++ (VP): Likewise. ++ (VP_small): Likewise. ++ (VP_small_lc): Likewise. ++ (VU_char): Likewise. ++ (add3): Likewise. ++ (altivec_vaddcuw): Likewise. ++ (altivec_vaddus): Likewise. ++ (altivec_vaddss): Likewise. ++ (sub3): Likewise. ++ (altivec_vsubcuw): Likewise. ++ (altivec_vsubus): Likewise. ++ (altivec_vsubss): Likewise. ++ (altivec_vavgs): Likewise. ++ (altivec_vcmpbfp): Likewise. ++ (altivec_eq): Likewise. ++ (altivec_gt): Likewise. ++ (altivec_gtu): Likewise. ++ (umax3): Likewise. ++ (smax3): Likewise. ++ (umin3): Likewise. ++ (smin3): Likewise. ++ (altivec_vpkuhum): Likewise. ++ (altivec_vpkuwum): Likewise. ++ (altivec_vpkshss): Likewise. ++ (altivec_vpkswss): Likewise. ++ (altivec_vpkuhus): Likewise. ++ (altivec_vpkshus): Likewise. ++ (altivec_vpkuwus): Likewise. ++ (altivec_vpkswus): Likewise. ++ (altivec_vpksss): Likewise. ++ (altivec_vpksus): Likewise. ++ (altivec_vpkuus): Likewise. ++ (altivec_vpkuum): Likewise. ++ (altivec_vrl): Likewise. ++ (altivec_vsl): Likewise. ++ (altivec_vsr): Likewise. ++ (altivec_vsra): Likewise. ++ (altivec_vsldoi_): Likewise. ++ (altivec_vupkhsb): Likewise. ++ (altivec_vupkhs): Likewise. ++ (altivec_vupkls): Likewise. ++ (altivec_vupkhsh): Likewise. ++ (altivec_vupklsb): Likewise. ++ (altivec_vupklsh): Likewise. ++ (altivec_vcmpequ_p): Likewise. ++ (altivec_vcmpgts_p): Likewise. ++ (altivec_vcmpgtu_p): Likewise. ++ (abs2): Likewise. ++ (vec_unpacks_hi_v16qi): Likewise. ++ (vec_unpacks_hi_v8hi): Likewise. ++ (vec_unpacks_lo_v16qi): Likewise. ++ (vec_unpacks_hi_): Likewise. ++ (vec_unpacks_lo_v8hi): Likewise. ++ (vec_unpacks_lo_): Likewise. ++ (vec_pack_trunc_v8h): Likewise. ++ (vec_pack_trunc_v4si): Likewise. ++ (vec_pack_trunc_): Likewise. ++ ++ * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8 ++ V2DI builtins. ++ (vec_vmaxsd): Likewise. ++ (vec_vmaxud): Likewise. ++ (vec_vminsd): Likewise. ++ (vec_vminud): Likewise. ++ (vec_vpksdss): Likewise. ++ (vec_vpksdus): Likewise. ++ (vec_vpkudum): Likewise. ++ (vec_vpkudus): Likewise. ++ (vec_vrld): Likewise. ++ (vec_vsld): Likewise. ++ (vec_vsrad): Likewise. ++ (vec_vsrd): Likewise. ++ (vec_vsubudm): Likewise. ++ (vec_vupkhsw): Likewise. ++ (vec_vupklsw): Likewise. ++ ++ 2013-05-22 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add ++ documentation for the power8 crypto builtins. ++ ++ * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md. ++ ++ * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support ++ macros for defining power8 builtin functions. ++ (BU_P8V_AV_2): Likewise. ++ (BU_P8V_AV_P): Likewise. ++ (BU_P8V_VSX_1): Likewise. ++ (BU_P8V_OVERLOAD_1): Likewise. ++ (BU_P8V_OVERLOAD_2): Likewise. ++ (BU_CRYPTO_1): Likewise. ++ (BU_CRYPTO_2): Likewise. ++ (BU_CRYPTO_3): Likewise. ++ (BU_CRYPTO_OVERLOAD_1): Likewise. ++ (BU_CRYPTO_OVERLOAD_2): Likewise. ++ (XSCVSPDP): Fix typo, point to the correct instruction. ++ (VCIPHER): Add power8 crypto builtins. ++ (VCIPHERLAST): Likewise. ++ (VNCIPHER): Likewise. ++ (VNCIPHERLAST): Likewise. ++ (VPMSUMB): Likewise. ++ (VPMSUMH): Likewise. ++ (VPMSUMW): Likewise. ++ (VPERMXOR_V2DI): Likewise. ++ (VPERMXOR_V4SI: Likewise. ++ (VPERMXOR_V8HI: Likewise. ++ (VPERMXOR_V16QI: Likewise. ++ (VSHASIGMAW): Likewise. ++ (VSHASIGMAD): Likewise. ++ (VPMSUM): Likewise. ++ (VPERMXOR): Likewise. ++ (VSHASIGMA): Likewise. ++ ++ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define ++ __CRYPTO__ if the crypto instructions are available. ++ (altivec_overloaded_builtins): Add support for overloaded power8 ++ builtins. ++ ++ * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add ++ support for power8 crypto builtins. ++ (builtin_function_type): Likewise. ++ (altivec_init_builtins): Add support for builtins that take vector ++ long long (V2DI) arguments. ++ ++ * config/rs6000/crypto.md: New file, define power8 crypto ++ instructions. ++ ++ 2013-05-22 Michael Meissner ++ Pat Haugen ++ Peter Bergner ++ ++ * doc/invoke.texi (Option Summary): Add power8 options. ++ (RS/6000 and PowerPC Options): Likewise. ++ ++ * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use ++ constraints.md instead of rs6000.h. Reorder w* constraints. Add ++ wm, wn, wr documentation. ++ ++ * gcc/config/rs6000/constraints.md (wm): New constraint for VSX ++ registers if direct move instructions are enabled. ++ (wn): New constraint for no registers. ++ (wq): New constraint for quad word even GPR registers. ++ (wr): New constraint if 64-bit instructions are enabled. ++ (wv): New constraint if power8 vector instructions are enabled. ++ (wQ): New constraint for quad word memory locations. ++ ++ * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New ++ constraint for 0..15 for crypto instructions. ++ (gpc_reg_operand): If VSX allow registers in VSX registers as well ++ as GPR and floating point registers. ++ (int_reg_operand): New predicate to match only GPR registers. ++ (base_reg_operand): New predicate to match base registers. ++ (quad_int_reg_operand): New predicate to match even GPR registers ++ for quad memory operations. ++ (vsx_reg_or_cint_operand): New predicate to allow vector logical ++ operations in both GPR and VSX registers. ++ (quad_memory_operand): New predicate for quad memory operations. ++ (reg_or_indexed_operand): New predicate for direct move support. ++ ++ * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): ++ Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS. ++ (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8). ++ (POWERPC_MASKS): Add power8 options. ++ (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the ++ various options. ++ ++ * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): ++ Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8. ++ ++ * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation. ++ (-mpower8-fusion): New power8 options. ++ (-mpower8-fusion-sign): Likewise. ++ (-mpower8-vector): Likewise. ++ (-mcrypto): Likewise. ++ (-mdirect-move): Likewise. ++ (-mquad-memory): Likewise. ++ ++ * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for ++ power8. ++ (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR ++ registers. ++ (rs6000_debug_reg_print): Print the base register class if ++ -mdebug=reg. ++ (rs6000_debug_vector_unit): Add p8_vector. ++ (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint ++ definitions. Also print fusion state. ++ (rs6000_init_hard_regno_mode_ok): Set up power8 constraints. ++ (rs6000_builtin_mask_calculate): Add power8 builtin support. ++ (rs6000_option_override_internal): Add support for power8. ++ (rs6000_common_init_builtins): Add debugging for skipped builtins ++ if -mdebug=builtin. ++ (rs6000_adjust_cost): Add power8 support. ++ (rs6000_issue_rate): Likewise. ++ (insn_must_be_first_in_group): Likewise. ++ (insn_must_be_last_in_group): Likewise. ++ (force_new_group): Likewise. ++ (rs6000_register_move_cost): Likewise. ++ (rs6000_opt_masks): Likewise. ++ ++ * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a ++ power8 capable assembler, default to power7 options. ++ (TARGET_DIRECT_MOVE): Likewise. ++ (TARGET_CRYPTO): Likewise. ++ (TARGET_P8_VECTOR): Likewise. ++ (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support. ++ (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise. ++ (VECTOR_MEM_P8_VECTOR_P): Likewise. ++ (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise. ++ (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise. ++ (TARGET_XSCVDPSPN): Likewise. ++ (TARGET_XSCVSPDPN): Likewsie. ++ (TARGET_SYNC_HI_QI): Likewise. ++ (TARGET_SYNC_TI): Likewise. ++ (MASK_CRYPTO): Likewise. ++ (MASK_DIRECT_MOVE): Likewise. ++ (MASK_P8_FUSION): Likewise. ++ (MASK_P8_VECTOR): Likewise. ++ (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the ++ TFmode temporary used by some of the direct move instructions to ++ get two FP temporary registers does not force creation of a stack ++ frame. ++ (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs. ++ (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so ++ that any VSX registers are tieable, even if they are also an ++ Altivec vector mode. ++ (r6000_reg_class_enum): Add wm, wr, wv constraints. ++ (RS6000_BTM_P8_VECTOR): Power8 builtin support. ++ (RS6000_BTM_CRYPTO): Likewise. ++ (RS6000_BTM_COMMON): Likewise. ++ ++ * config/rs6000/rs6000.md (cpu attribute): Add power8. ++ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise. ++ (enum rs6000_vector): Add power8 vector support. ++ ++2013-05-06 Michael Meissner ++ ++ Merge up to 198656. ++ * REVISION: Update subversion id. ++ ++ Backport from trunk ++ 2013-05-03 Michael Meissner ++ ++ PR target/57150 ++ * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Use DFmode ++ to save TFmode registers and DImode to save TImode registers for ++ caller save operations. ++ (HARD_REGNO_CALL_PART_CLOBBERED): TFmode and TDmode do not need to ++ mark being partially clobbered since they only use the first ++ double word. ++ ++ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): TFmode ++ and TDmode only use the upper 64-bits of each VSX register. ++ ++2013-04-09 Michael Meissner ++ ++ Merge up to 197642. ++ * REVISION: Update subversion id. ++ ++2013-03-20 Michael Meissner ++ ++ Backport from mainline ++ 2013-03-20 Pat Haugen ++ ++ * config/rs6000/predicates.md (indexed_address, update_address_mem ++ update_indexed_address_mem): New predicates. ++ * config/rs6000/vsx.md (vsx_extract__zero): Set correct "type" ++ attribute for load/store instructions. ++ * config/rs6000/dfp.md (movsd_store): Likewise. ++ (movsd_load): Likewise. ++ * config/rs6000/rs6000.md (zero_extenddi2_internal1): Likewise. ++ (unnamed HI->DI extend define_insn): Likewise. ++ (unnamed SI->DI extend define_insn): Likewise. ++ (unnamed QI->SI extend define_insn): Likewise. ++ (unnamed QI->HI extend define_insn): Likewise. ++ (unnamed HI->SI extend define_insn): Likewise. ++ (unnamed HI->SI extend define_insn): Likewise. ++ (extendsfdf2_fpr): Likewise. ++ (movsi_internal1): Likewise. ++ (movsi_internal1_single): Likewise. ++ (movhi_internal): Likewise. ++ (movqi_internal): Likewise. ++ (movcc_internal1): Correct mnemonic for stw insn. Set correct "type" ++ attribute for load/store instructions. ++ (mov_hardfloat): Set correct "type" attribute for load/store ++ instructions. ++ (mov_softfloat): Likewise. ++ (mov_hardfloat32): Likewise. ++ (mov_hardfloat64): Likewise. ++ (mov_softfloat64): Likewise. ++ (movdi_internal32): Likewise. ++ (movdi_internal64): Likewise. ++ (probe_stack_): Likewise. ++ ++ Backport from mainline ++ 2013-03-20 Michael Meissner ++ ++ * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary ++ floating point, and decimal floating point to reload iterator. ++ ++ * config/rs6000/constraints.md (wl constraint): New constraints to ++ return FLOAT_REGS if certain options are used to reduce the number ++ of separate patterns that exist in the file. ++ (wx constraint): Likewise. ++ (wz constraint): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If ++ -mdebug=reg, print wg, wl, wx, and wz constraints. ++ (rs6000_init_hard_regno_mode_ok): Initialize new constraints. ++ Initialize the reload functions for 64-bit binary/decimal floating ++ point types. ++ (reg_offset_addressing_ok_p): If we are on a power7 or later, use ++ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't ++ create the buffer on the stack to overcome not having a 32-bit ++ load and store. ++ (rs6000_emit_move): Likewise. ++ (rs6000_secondary_memory_needed_rtx): Likewise. ++ (rs6000_alloc_sdmode_stack_slot): Likewise. ++ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f ++ via xxlxor, just like DFmode 0.0. ++ ++ * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro, ++ define as 1 if we are running on a power7 or newer. ++ (enum r6000_reg_class_enum): Add new constraints. ++ ++ * config/rs6000/dfp.md (movsd): Delete, combine with binary ++ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves ++ with other moves by using conditional constraits (wg). Use LFIWZX ++ and STFIWX for loading SDmode on power7. Use xxlxor to create ++ 0.0f. ++ (movsd splitter): Likewise. ++ (movsd_hardfloat): Likewise. ++ (movsd_softfloat): Likewise. ++ ++ * config/rs6000/rs6000.md (FMOVE32): New iterators to combine ++ binary and decimal floating point moves. ++ (fmove_ok): New attributes to combine binary and decimal floating ++ point moves, and to combine power6x (mfpgpr) moves along normal ++ floating moves. ++ (real_value_to_target): Likewise. ++ (f32_lr): Likewise. ++ (f32_lm): Likewise. ++ (f32_li): Likewise. ++ (f32_sr): Likewise. ++ (f32_sm): Likewise. ++ (f32_si): Likewise. ++ (movsf): Combine binary and decimal floating point moves. Combine ++ power6x (mfpgpr) moves with other moves by using conditional ++ constraits (wg). Use LFIWZX and STFIWX for loading SDmode on ++ power7. ++ (mov for SFmode/SDmode); Likewise. ++ (SFmode/SDmode splitters): Likewise. ++ (movsf_hardfloat): Likewise. ++ (mov_hardfloat for SFmode/SDmode): Likewise. ++ (movsf_softfloat): Likewise. ++ (mov_softfloat for SFmode/SDmode): Likewise. ++ ++ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl, ++ wx and wz constraints. ++ ++ * config/rs6000/constraints.md (wg constraint): New constraint to ++ return FLOAT_REGS if -mmfpgpr (power6x) was used. ++ ++ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg ++ constraint. ++ ++ * config/rs6000/rs6000.c (rs6000_debug_reg_global): If ++ -mdebug=reg, print wg, wl, wx, and wz constraints. ++ (rs6000_init_hard_regno_mode_ok): Initialize new constraints. ++ Initialize the reload functions for 64-bit binary/decimal floating ++ point types. ++ (reg_offset_addressing_ok_p): If we are on a power7 or later, use ++ LFIWZX and STFIWX to load/store 32-bit decimal types, and don't ++ create the buffer on the stack to overcome not having a 32-bit ++ load and store. ++ (rs6000_emit_move): Likewise. ++ (rs6000_secondary_memory_needed_rtx): Likewise. ++ (rs6000_alloc_sdmode_stack_slot): Likewise. ++ (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f ++ via xxlxor, just like DFmode 0.0. ++ ++ ++ * config/rs6000/dfp.md (movdd): Delete, combine with binary ++ floating point moves in rs6000.md. Combine power6x (mfpgpr) moves ++ with other moves by using conditional constraits (wg). Use LFIWZX ++ and STFIWX for loading SDmode on power7. ++ (movdd splitters): Likewise. ++ (movdd_hardfloat32): Likewise. ++ (movdd_softfloat32): Likewise. ++ (movdd_hardfloat64_mfpgpr): Likewise. ++ (movdd_hardfloat64): Likewise. ++ (movdd_softfloat64): Likewise. ++ ++ * config/rs6000/rs6000.md (FMOVE64): New iterators to combine ++ 64-bit binary and decimal floating point moves. ++ (FMOVE64X): Likewise. ++ (movdf): Combine 64-bit binary and decimal floating point moves. ++ Combine power6x (mfpgpr) moves with other moves by using ++ conditional constraits (wg). ++ (mov for DFmode/DDmode): Likewise. ++ (DFmode/DDmode splitters): Likewise. ++ (movdf_hardfloat32): Likewise. ++ (mov_hardfloat32 for DFmode/DDmode): Likewise. ++ (movdf_softfloat32): Likewise. ++ (movdf_hardfloat64_mfpgpr): Likewise. ++ (movdf_hardfloat64): Likewise. ++ (mov_hardfloat64 for DFmode/DDmode): Likewise. ++ (movdf_softfloat64): Likewise. ++ (mov_softfloat64 for DFmode/DDmode): Likewise. ++ (reload__load): Move to later in the file so they aren't in ++ the middle of the floating point move insns. ++ (reload__store): Likewise. ++ ++ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg ++ constraint. ++ ++ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg ++ constraint if -mdebug=reg. ++ (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if ++ -mfpgpr. Enable using dd reload support if needed. ++ ++ * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit ++ binary and decimal floating point moves in rs6000.md. ++ (movtd_internal): Likewise. ++ ++ * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and ++ decimal floating point moves. ++ (movtf): Likewise. ++ (movtf_internal): Likewise. ++ (mov_internal, TDmode/TFmode): Likewise. ++ (movtf_softfloat): Likewise. ++ (mov_softfloat, TDmode/TFmode): Likewise. ++ ++ * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with ++ movdi_internal64, using wg constraint for move direct operations. ++ (movdi_internal64): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print ++ MODES_TIEABLE_P for selected modes. Print the numerical value of ++ the various virtual registers. Use GPR/FPR first/last values, ++ instead of hard coding the register numbers. Print which modes ++ have reload functions registered. ++ (rs6000_option_override_internal): If -mdebug=reg, trace the ++ options settings before/after setting cpu, target and subtarget ++ settings. ++ (rs6000_secondary_reload_trace): Improve the RTL dump for ++ -mdebug=addr and for secondary reload failures in ++ rs6000_secondary_reload_inner. ++ (rs6000_secondary_reload_fail): Likewise. ++ (rs6000_secondary_reload_inner): Likewise. ++ ++ * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience ++ macros for first/last GPR and FPR registers. ++ (LAST_GPR_REGNO): Likewise. ++ (FIRST_FPR_REGNO): Likewise. ++ (LAST_FPR_REGNO): Likewise. ++ ++ * config/rs6000/vector.md (mul3): Use the combined macro ++ VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to ++ VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P. ++ (vcond): Likewise. ++ (vcondu): Likewise. ++ (vector_gtu): Likewise. ++ (vector_gte): Likewise. ++ (xor3): Don't allow logical operations on TImode in 32-bit ++ to prevent the compiler from converting DImode operations to ++ TImode. ++ (ior3): Likewise. ++ (and3): Likewise. ++ (one_cmpl2): Likewise. ++ (nor3): Likewise. ++ (andc3): Likewise. ++ ++ * config/rs6000/constraints.md (wt constraint): New constraint ++ that returns VSX_REGS if TImode is allowed in VSX registers. ++ ++ * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy ++ constant under VSX. ++ ++ * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is ++ similar to TImode, but it is restricted to being in the GPRs. ++ ++ * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow ++ TImode to occupy a single VSX register. ++ ++ * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to ++ -mvsx-timode for power7/power8. ++ (power7 cpu): Likewise. ++ (power8 cpu): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make ++ sure that TFmode/TDmode take up two registers if they are ever ++ allowed in the upper VSX registers. ++ (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX ++ registers. ++ (rs6000_init_hard_regno_mode_ok): Likewise. ++ (rs6000_debug_reg_global): Add debugging for PTImode and wt ++ constraint. Print if LRA is turned on. ++ (rs6000_option_override_internal): Give an error if -mvsx-timode ++ and VSX is not enabled. ++ (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If ++ -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode ++ to reg+offset addressing. Use PTImode when checking offset ++ addresses for validity. ++ (reg_offset_addressing_ok_p): Likewise. ++ (rs6000_legitimate_offset_address_p): Likewise. ++ (rs6000_legitimize_address): Likewise. ++ (rs6000_legitimize_reload_address): Likewise. ++ (rs6000_legitimate_address_p): Likewise. ++ (rs6000_eliminate_indexed_memrefs): Likewise. ++ (rs6000_emit_move): Likewise. ++ (rs6000_secondary_reload): Likewise. ++ (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit ++ reloads to fpr registers to continue to use reg+offset addressing, ++ but 64-bit reloads to altivec registers need reg+reg addressing. ++ Drop test for PRE_MODIFY, since VSX loads/stores no longer support ++ it. Treat LO_SUM like a PLUS operation. ++ (rs6000_secondary_reload_class): If type is 64-bit, prefer to use ++ FLOAT_REGS instead of VSX_RGS to allow use of reg+offset ++ addressing. ++ (rs6000_cannot_change_mode_class): Do not allow TImode in VSX ++ registers to share a register with a smaller sized type, since VSX ++ puts scalars in the upper 64-bits. ++ (print_operand): Add support for PTImode. ++ (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of ++ VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX ++ registers, but don't have arithmetic support. ++ (rs6000_memory_move_cost): Add test for VSX. ++ (rs6000_opt_masks): Add -mvsx-timode. ++ ++ * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves ++ for TImode. ++ (VSs): Likewise. ++ (VSr): Use wt constraint for TImode. ++ (VSv): Drop TImode support. ++ (vsx_movti): Delete, replace with versions for 32-bit and 64-bit. ++ (vsx_movti_64bit): Likewise. ++ (vsx_movti_32bit): Likewise. ++ (vec_store_): Use VSX iterator instead of vector iterator. ++ (vsx_and3): Delete use of '?' constraint on inputs, just put ++ one '?' on the appropriate output constraint. Do not allow TImode ++ logical operations on 32-bit systems. ++ (vsx_ior3): Likewise. ++ (vsx_xor3): Likewise. ++ (vsx_one_cmpl2): Likewise. ++ (vsx_nor3): Likewise. ++ (vsx_andc3): Likewise. ++ (vsx_concat_): Likewise. ++ (vsx_xxpermdi_): Fix thinko for non V2DF/V2DI modes. ++ ++ * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from ++ OPTION_MASK_VSX_TIMODE. ++ (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. ++ (STACK_SAVEAREA_MODE): Use PTImode instead of TImode. ++ ++ * config/rs6000/rs6000.md (INT mode attribute): Add PTImode. ++ (TI2 iterator): New iterator for TImode, PTImode. ++ (wd mode attribute): Add values for vector types. ++ (movti_string): Replace TI move operations with operations for ++ TImode and PTImode. Add support for TImode being allowed in VSX ++ registers. ++ (mov_string, TImode/PTImode): Likewise. ++ (movti_ppc64): Likewise. ++ (mov_ppc64, TImode/PTImode): Likewise. ++ (TI mode splitters): Likewise. ++ ++ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt ++ constraint. ++ ++2013-03-20 Michael Meissner ++ ++ Clone branch from gcc-4_8-branch, subversion id 196835. ++ * REVISION: New file, track subversion id. ++ +--- a/src/gcc/calls.c ++++ b/src/gcc/calls.c +@@ -983,6 +983,7 @@ + + for (i = 0; i < num_actuals; i++) + if (args[i].reg != 0 && ! args[i].pass_on_stack ++ && GET_CODE (args[i].reg) != PARALLEL + && args[i].mode == BLKmode + && MEM_P (args[i].value) + && (MEM_ALIGN (args[i].value) +@@ -1327,6 +1328,7 @@ + #else + args[i].reg != 0, + #endif ++ reg_parm_stack_space, + args[i].pass_on_stack ? 0 : args[i].partial, + fndecl, args_size, &args[i].locate); + #ifdef BLOCK_REG_PADDING +@@ -3171,7 +3173,9 @@ + group load/store machinery below. */ + if (!structure_value_addr + && !pcc_struct_value ++ && TYPE_MODE (rettype) != VOIDmode + && TYPE_MODE (rettype) != BLKmode ++ && REG_P (valreg) + && targetm.calls.return_in_msb (rettype)) + { + if (shift_return_value (TYPE_MODE (rettype), false, valreg)) +@@ -3734,7 +3738,8 @@ + #else + argvec[count].reg != 0, + #endif +- 0, NULL_TREE, &args_size, &argvec[count].locate); ++ reg_parm_stack_space, 0, ++ NULL_TREE, &args_size, &argvec[count].locate); + + if (argvec[count].reg == 0 || argvec[count].partial != 0 + || reg_parm_stack_space > 0) +@@ -3821,7 +3826,7 @@ + #else + argvec[count].reg != 0, + #endif +- argvec[count].partial, ++ reg_parm_stack_space, argvec[count].partial, + NULL_TREE, &args_size, &argvec[count].locate); + args_size.constant += argvec[count].locate.size.constant; + gcc_assert (!argvec[count].locate.size.var); +--- a/src/gcc/REVISION ++++ b/src/gcc/REVISION +@@ -0,0 +1 @@ ++[ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 204974] +--- a/src/gcc/config.gcc ++++ b/src/gcc/config.gcc +@@ -420,7 +420,7 @@ + ;; + powerpc*-*-*) + cpu_type=rs6000 +- extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h" ++ extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h" + need_64bit_hwint=yes + case x$with_cpu in + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) +@@ -3494,7 +3494,7 @@ + ;; + + powerpc*-*-* | rs6000-*-*) +- supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64" ++ supported_defaults="abi cpu cpu_32 cpu_64 float tune tune_32 tune_64" + + for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do + eval "val=\$with_$which" +@@ -3531,6 +3531,16 @@ + ;; + esac + done ++ ++ case "$with_abi" in ++ "" | elfv1 | elfv2 ) ++ #OK ++ ;; ++ *) ++ echo "Unknown ABI used in --with-abi=$with_abi" ++ exit 1 ++ ;; ++ esac + ;; + + s390*-*-*) +--- a/src/gcc/config/rs6000/power8.md ++++ b/src/gcc/config/rs6000/power8.md +@@ -0,0 +1,373 @@ ++;; Scheduling description for IBM POWER8 processor. ++;; Copyright (C) 2013 Free Software Foundation, Inc. ++;; ++;; Contributed by Pat Haugen (pthaugen@us.ibm.com). ++ ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 3, or (at your ++;; option) any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "power8fxu,power8lsu,power8vsu,power8misc") ++ ++(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu") ++(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu") ++(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu") ++(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu") ++(define_cpu_unit "bpu_power8,cru_power8" "power8misc") ++(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\ ++ du5_power8,du6_power8" "power8misc") ++ ++ ++; Dispatch group reservations ++(define_reservation "DU_any_power8" ++ "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\ ++ du5_power8") ++ ++; 2-way Cracked instructions go in slots 0-1 ++; (can also have a second in slots 3-4 if insns are adjacent) ++(define_reservation "DU_cracked_power8" ++ "du0_power8+du1_power8") ++ ++; Insns that are first in group ++(define_reservation "DU_first_power8" ++ "du0_power8") ++ ++; Insns that are first and last in group ++(define_reservation "DU_both_power8" ++ "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\ ++ du5_power8+du6_power8") ++ ++; Dispatch slots are allocated in order conforming to program order. ++(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\ ++ du5_power8,du6_power8") ++(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\ ++ du6_power8") ++(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8") ++(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8") ++(absence_set "du4_power8" "du5_power8,du6_power8") ++(absence_set "du5_power8" "du6_power8") ++ ++ ++; Execution unit reservations ++(define_reservation "FXU_power8" ++ "fxu0_power8|fxu1_power8") ++ ++(define_reservation "LU_power8" ++ "lu0_power8|lu1_power8") ++ ++(define_reservation "LSU_power8" ++ "lsu0_power8|lsu1_power8") ++ ++(define_reservation "LU_or_LSU_power8" ++ "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8") ++ ++(define_reservation "VSU_power8" ++ "vsu0_power8|vsu1_power8") ++ ++ ++; LS Unit ++(define_insn_reservation "power8-load" 3 ++ (and (eq_attr "type" "load") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,LU_or_LSU_power8") ++ ++(define_insn_reservation "power8-load-update" 3 ++ (and (eq_attr "type" "load_u,load_ux") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,LU_or_LSU_power8+FXU_power8") ++ ++(define_insn_reservation "power8-load-ext" 3 ++ (and (eq_attr "type" "load_ext") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,LU_or_LSU_power8,FXU_power8") ++ ++(define_insn_reservation "power8-load-ext-update" 3 ++ (and (eq_attr "type" "load_ext_u,load_ext_ux") ++ (eq_attr "cpu" "power8")) ++ "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") ++ ++(define_insn_reservation "power8-fpload" 5 ++ (and (eq_attr "type" "fpload,vecload") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,LU_power8") ++ ++(define_insn_reservation "power8-fpload-update" 5 ++ (and (eq_attr "type" "fpload_u,fpload_ux") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,LU_power8+FXU_power8") ++ ++(define_insn_reservation "power8-store" 5 ; store-forwarding latency ++ (and (eq_attr "type" "store,store_u") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,LSU_power8+LU_power8") ++ ++(define_insn_reservation "power8-store-update-indexed" 5 ++ (and (eq_attr "type" "store_ux") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,LSU_power8+LU_power8") ++ ++(define_insn_reservation "power8-fpstore" 5 ++ (and (eq_attr "type" "fpstore") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,LSU_power8+VSU_power8") ++ ++(define_insn_reservation "power8-fpstore-update" 5 ++ (and (eq_attr "type" "fpstore_u,fpstore_ux") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,LSU_power8+VSU_power8") ++ ++(define_insn_reservation "power8-vecstore" 5 ++ (and (eq_attr "type" "vecstore") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,LSU_power8+VSU_power8") ++ ++(define_insn_reservation "power8-larx" 3 ++ (and (eq_attr "type" "load_l") ++ (eq_attr "cpu" "power8")) ++ "DU_both_power8,LU_or_LSU_power8") ++ ++(define_insn_reservation "power8-stcx" 10 ++ (and (eq_attr "type" "store_c") ++ (eq_attr "cpu" "power8")) ++ "DU_both_power8,LSU_power8+LU_power8") ++ ++(define_insn_reservation "power8-sync" 1 ++ (and (eq_attr "type" "sync,isync") ++ (eq_attr "cpu" "power8")) ++ "DU_both_power8,LSU_power8") ++ ++ ++; FX Unit ++(define_insn_reservation "power8-1cyc" 1 ++ (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ ++ var_shift_rotate,exts,isel") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,FXU_power8") ++ ++; Extra cycle to LU/LSU ++(define_bypass 2 "power8-1cyc" ++ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ ++ power8-vecstore,power8-larx,power8-stcx") ++; "power8-load,power8-load-update,power8-load-ext,\ ++; power8-load-ext-update,power8-fpload,power8-fpload-update,\ ++; power8-store,power8-store-update,power8-store-update-indexed,\ ++; power8-fpstore,power8-fpstore-update,power8-vecstore,\ ++; power8-larx,power8-stcx") ++ ++(define_insn_reservation "power8-2cyc" 2 ++ (and (eq_attr "type" "cntlz,popcnt") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,FXU_power8") ++ ++(define_insn_reservation "power8-two" 2 ++ (and (eq_attr "type" "two") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8") ++ ++(define_insn_reservation "power8-three" 3 ++ (and (eq_attr "type" "three") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8") ++ ++; cmp - Normal compare insns ++(define_insn_reservation "power8-cmp" 2 ++ (and (eq_attr "type" "cmp") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,FXU_power8") ++ ++; fast_compare : add./and./nor./etc ++(define_insn_reservation "power8-fast-compare" 2 ++ (and (eq_attr "type" "fast_compare") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,FXU_power8") ++ ++; compare : rldicl./exts./etc ++; delayed_compare : rlwinm./slwi./etc ++; var_delayed_compare : rlwnm./slw./etc ++(define_insn_reservation "power8-compare" 2 ++ (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,FXU_power8,FXU_power8") ++ ++; Extra cycle to LU/LSU ++(define_bypass 3 "power8-fast-compare,power8-compare" ++ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ ++ power8-vecstore,power8-larx,power8-stcx") ++ ++; 5 cycle CR latency ++(define_bypass 5 "power8-fast-compare,power8-compare" ++ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") ++ ++(define_insn_reservation "power8-mul" 4 ++ (and (eq_attr "type" "imul,imul2,imul3,lmul") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,FXU_power8") ++ ++(define_insn_reservation "power8-mul-compare" 4 ++ (and (eq_attr "type" "imul_compare,lmul_compare") ++ (eq_attr "cpu" "power8")) ++ "DU_cracked_power8,FXU_power8") ++ ++; Extra cycle to LU/LSU ++(define_bypass 5 "power8-mul,power8-mul-compare" ++ "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ ++ power8-vecstore,power8-larx,power8-stcx") ++ ++; 7 cycle CR latency ++(define_bypass 7 "power8-mul,power8-mul-compare" ++ "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") ++ ++; FXU divides are not pipelined ++(define_insn_reservation "power8-idiv" 37 ++ (and (eq_attr "type" "idiv") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,fxu0_power8*37|fxu1_power8*37") ++ ++(define_insn_reservation "power8-ldiv" 68 ++ (and (eq_attr "type" "ldiv") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,fxu0_power8*68|fxu1_power8*68") ++ ++(define_insn_reservation "power8-mtjmpr" 5 ++ (and (eq_attr "type" "mtjmpr") ++ (eq_attr "cpu" "power8")) ++ "DU_first_power8,FXU_power8") ++ ++; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode ++(define_insn_reservation "power8-mtcr" 3 ++ (and (eq_attr "type" "mtcr") ++ (eq_attr "cpu" "power8")) ++ "DU_both_power8,FXU_power8") ++ ++ ++; CR Unit ++(define_insn_reservation "power8-mfjmpr" 5 ++ (and (eq_attr "type" "mfjmpr") ++ (eq_attr "cpu" "power8")) ++ "DU_first_power8,cru_power8+FXU_power8") ++ ++(define_insn_reservation "power8-crlogical" 3 ++ (and (eq_attr "type" "cr_logical,delayed_cr") ++ (eq_attr "cpu" "power8")) ++ "DU_first_power8,cru_power8") ++ ++(define_insn_reservation "power8-mfcr" 5 ++ (and (eq_attr "type" "mfcr") ++ (eq_attr "cpu" "power8")) ++ "DU_both_power8,cru_power8") ++ ++(define_insn_reservation "power8-mfcrf" 3 ++ (and (eq_attr "type" "mfcrf") ++ (eq_attr "cpu" "power8")) ++ "DU_first_power8,cru_power8") ++ ++ ++; BR Unit ++; Branches take dispatch slot 7, but reserve any remaining prior slots to ++; prevent other insns from grabbing them once this is assigned. ++(define_insn_reservation "power8-branch" 3 ++ (and (eq_attr "type" "jmpreg,branch") ++ (eq_attr "cpu" "power8")) ++ "(du6_power8\ ++ |du5_power8+du6_power8\ ++ |du4_power8+du5_power8+du6_power8\ ++ |du3_power8+du4_power8+du5_power8+du6_power8\ ++ |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ ++ |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ ++ |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\ ++ du6_power8),bpu_power8") ++ ++; Branch updating LR/CTR feeding mf[lr|ctr] ++(define_bypass 4 "power8-branch" "power8-mfjmpr") ++ ++ ++; VS Unit (includes FP/VSX/VMX/DFP/Crypto) ++(define_insn_reservation "power8-fp" 6 ++ (and (eq_attr "type" "fp,dmul") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++; Additional 3 cycles for any CR result ++(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch") ++ ++(define_insn_reservation "power8-fpcompare" 8 ++ (and (eq_attr "type" "fpcompare") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-sdiv" 27 ++ (and (eq_attr "type" "sdiv") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-ddiv" 33 ++ (and (eq_attr "type" "ddiv") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-sqrt" 32 ++ (and (eq_attr "type" "ssqrt") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-dsqrt" 44 ++ (and (eq_attr "type" "dsqrt") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-vecsimple" 2 ++ (and (eq_attr "type" "vecperm,vecsimple,veccmp") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-vecnormal" 6 ++ (and (eq_attr "type" "vecfloat,vecdouble") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_bypass 7 "power8-vecnormal" ++ "power8-vecsimple,power8-veccomplex,power8-fpstore*,\ ++ power8-vecstore") ++ ++(define_insn_reservation "power8-veccomplex" 7 ++ (and (eq_attr "type" "veccomplex") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-vecfdiv" 25 ++ (and (eq_attr "type" "vecfdiv") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-vecdiv" 31 ++ (and (eq_attr "type" "vecdiv") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-mffgpr" 5 ++ (and (eq_attr "type" "mffgpr") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-mftgpr" 6 ++ (and (eq_attr "type" "mftgpr") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ ++(define_insn_reservation "power8-crypto" 7 ++ (and (eq_attr "type" "crypto") ++ (eq_attr "cpu" "power8")) ++ "DU_any_power8,VSU_power8") ++ +--- a/src/gcc/config/rs6000/vector.md ++++ b/src/gcc/config/rs6000/vector.md +@@ -24,13 +24,13 @@ + + + ;; Vector int modes +-(define_mode_iterator VEC_I [V16QI V8HI V4SI]) ++(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) + + ;; Vector float modes + (define_mode_iterator VEC_F [V4SF V2DF]) + + ;; Vector arithmetic modes +-(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF]) ++(define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF]) + + ;; Vector modes that need alginment via permutes + (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF]) +@@ -45,7 +45,7 @@ + (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF]) + + ;; Vector comparison modes +-(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF]) ++(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF]) + + ;; Vector init/extract modes + (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF]) +@@ -54,7 +54,7 @@ + (define_mode_iterator VEC_64 [V2DI V2DF]) + + ;; Vector reload iterator +-(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI]) ++(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF SF SD SI DF DD DI TI]) + + ;; Base type from vector mode + (define_mode_attr VEC_base [(V16QI "QI") +@@ -88,7 +88,8 @@ + (smax "smax")]) + + +-;; Vector move instructions. ++;; Vector move instructions. Little-endian VSX loads and stores require ++;; special handling to circumvent "element endianness." + (define_expand "mov" + [(set (match_operand:VEC_M 0 "nonimmediate_operand" "") + (match_operand:VEC_M 1 "any_operand" ""))] +@@ -104,6 +105,16 @@ + && !vlogical_operand (operands[1], mode)) + operands[1] = force_reg (mode, operands[1]); + } ++ if (!BYTES_BIG_ENDIAN ++ && VECTOR_MEM_VSX_P (mode) ++ && mode != TImode ++ && !gpr_or_gpr_p (operands[0], operands[1]) ++ && (memory_operand (operands[0], mode) ++ ^ memory_operand (operands[1], mode))) ++ { ++ rs6000_emit_le_vsx_move (operands[0], operands[1], mode); ++ DONE; ++ } + }) + + ;; Generic vector floating point load/store instructions. These will match +@@ -126,7 +137,9 @@ + (match_operand:VEC_L 1 "input_operand" ""))] + "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) + && reload_completed +- && gpr_or_gpr_p (operands[0], operands[1])" ++ && gpr_or_gpr_p (operands[0], operands[1]) ++ && !direct_move_p (operands[0], operands[1]) ++ && !quad_load_store_p (operands[0], operands[1])" + [(pc)] + { + rs6000_split_multireg_move (operands[0], operands[1]); +@@ -249,7 +262,7 @@ + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] +- "VECTOR_UNIT_VSX_P (mode) || VECTOR_UNIT_ALTIVEC_P (mode)" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + { + if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode)) + { +@@ -395,7 +408,7 @@ + (match_operand:VEC_I 5 "vint_operand" "")]) + (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "VECTOR_UNIT_ALTIVEC_P (mode)" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + " + { + if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], +@@ -451,7 +464,7 @@ + (match_operand:VEC_I 5 "vint_operand" "")]) + (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "VECTOR_UNIT_ALTIVEC_P (mode)" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + " + { + if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], +@@ -505,14 +518,14 @@ + [(set (match_operand:VEC_I 0 "vint_operand" "") + (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "VECTOR_UNIT_ALTIVEC_P (mode)" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "") + + (define_expand "vector_geu" + [(set (match_operand:VEC_I 0 "vint_operand" "") + (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "VECTOR_UNIT_ALTIVEC_P (mode)" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "") + + (define_insn_and_split "*vector_uneq" +@@ -708,48 +721,19 @@ + "") + + +-;; Vector logical instructions +-(define_expand "xor3" +- [(set (match_operand:VEC_L 0 "vlogical_operand" "") +- (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") +- (match_operand:VEC_L 2 "vlogical_operand" "")))] +- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +- "") ++;; Vector count leading zeros ++(define_expand "clz2" ++ [(set (match_operand:VEC_I 0 "register_operand" "") ++ (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] ++ "TARGET_P8_VECTOR") + +-(define_expand "ior3" +- [(set (match_operand:VEC_L 0 "vlogical_operand" "") +- (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") +- (match_operand:VEC_L 2 "vlogical_operand" "")))] +- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +- "") ++;; Vector population count ++(define_expand "popcount2" ++ [(set (match_operand:VEC_I 0 "register_operand" "") ++ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] ++ "TARGET_P8_VECTOR") + +-(define_expand "and3" +- [(set (match_operand:VEC_L 0 "vlogical_operand" "") +- (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") +- (match_operand:VEC_L 2 "vlogical_operand" "")))] +- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +- "") +- +-(define_expand "one_cmpl2" +- [(set (match_operand:VEC_L 0 "vlogical_operand" "") +- (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))] +- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +- "") +- +-(define_expand "nor3" +- [(set (match_operand:VEC_L 0 "vlogical_operand" "") +- (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") +- (match_operand:VEC_L 2 "vlogical_operand" ""))))] +- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +- "") +- +-(define_expand "andc3" +- [(set (match_operand:VEC_L 0 "vlogical_operand" "") +- (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" "")) +- (match_operand:VEC_L 1 "vlogical_operand" "")))] +- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +- "") +- ++ + ;; Same size conversions + (define_expand "float2" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") +@@ -889,7 +873,7 @@ + { + rtx reg = gen_reg_rtx (V4SFmode); + +- rs6000_expand_interleave (reg, operands[1], operands[1], true); ++ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvspdp (operands[0], reg)); + DONE; + }) +@@ -901,7 +885,7 @@ + { + rtx reg = gen_reg_rtx (V4SFmode); + +- rs6000_expand_interleave (reg, operands[1], operands[1], false); ++ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvspdp (operands[0], reg)); + DONE; + }) +@@ -913,7 +897,7 @@ + { + rtx reg = gen_reg_rtx (V4SImode); + +- rs6000_expand_interleave (reg, operands[1], operands[1], true); ++ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg)); + DONE; + }) +@@ -925,7 +909,7 @@ + { + rtx reg = gen_reg_rtx (V4SImode); + +- rs6000_expand_interleave (reg, operands[1], operands[1], false); ++ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg)); + DONE; + }) +@@ -937,7 +921,7 @@ + { + rtx reg = gen_reg_rtx (V4SImode); + +- rs6000_expand_interleave (reg, operands[1], operands[1], true); ++ rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg)); + DONE; + }) +@@ -949,7 +933,7 @@ + { + rtx reg = gen_reg_rtx (V4SImode); + +- rs6000_expand_interleave (reg, operands[1], operands[1], false); ++ rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg)); + DONE; + }) +@@ -963,8 +947,19 @@ + (match_operand:V16QI 3 "vlogical_operand" "")] + "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" + { +- emit_insn (gen_altivec_vperm_ (operands[0], operands[1], operands[2], +- operands[3])); ++ if (BYTES_BIG_ENDIAN) ++ emit_insn (gen_altivec_vperm_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ { ++ /* We have changed lvsr to lvsl, so to complete the transformation ++ of vperm for LE, we must swap the inputs. */ ++ rtx unspec = gen_rtx_UNSPEC (mode, ++ gen_rtvec (3, operands[2], ++ operands[1], operands[3]), ++ UNSPEC_VPERM); ++ emit_move_insn (operands[0], unspec); ++ } + DONE; + }) + +@@ -1064,7 +1059,7 @@ + [(set (match_operand:VEC_I 0 "vint_operand" "") + (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "TARGET_ALTIVEC" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "") + + ;; Expanders for arithmetic shift left on each vector element +@@ -1072,7 +1067,7 @@ + [(set (match_operand:VEC_I 0 "vint_operand" "") + (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "TARGET_ALTIVEC" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "") + + ;; Expanders for logical shift right on each vector element +@@ -1080,7 +1075,7 @@ + [(set (match_operand:VEC_I 0 "vint_operand" "") + (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "TARGET_ALTIVEC" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "") + + ;; Expanders for arithmetic shift right on each vector element +@@ -1088,7 +1083,7 @@ + [(set (match_operand:VEC_I 0 "vint_operand" "") + (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") + (match_operand:VEC_I 2 "vint_operand" "")))] +- "TARGET_ALTIVEC" ++ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "") + + ;; Vector reduction expanders for VSX +--- a/src/gcc/config/rs6000/constraints.md ++++ b/src/gcc/config/rs6000/constraints.md +@@ -52,22 +52,62 @@ + "@internal") + + ;; Use w as a prefix to add VSX modes +-;; vector double (V2DF) ++;; any VSX register ++(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" ++ "Any VSX register if the -mvsx option was used or NO_REGS.") ++ + (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" +- "@internal") ++ "VSX vector register to hold vector double data or NO_REGS.") + +-;; vector float (V4SF) + (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" +- "@internal") ++ "VSX vector register to hold vector float data or NO_REGS.") + +-;; scalar double (DF) ++(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" ++ "If -mmfpgpr was used, a floating point register or NO_REGS.") ++ ++(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" ++ "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") ++ ++(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" ++ "VSX register if direct move instructions are enabled, or NO_REGS.") ++ ++;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use ++;; direct move directly, and movsf can't to move between the register sets. ++;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode ++(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") ++ ++(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" ++ "General purpose register if 64-bit instructions are enabled or NO_REGS.") ++ + (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" +- "@internal") ++ "VSX vector register to hold scalar double values or NO_REGS.") + +-;; any VSX register +-(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" +- "@internal") ++(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" ++ "VSX vector register to hold 128 bit integer or NO_REGS.") + ++(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" ++ "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") ++ ++(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" ++ "Altivec register to use for double loads/stores or NO_REGS.") ++ ++(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" ++ "FP or VSX register to perform float operations under -mvsx or NO_REGS.") ++ ++(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" ++ "Floating point register if the STFIWX instruction is enabled or NO_REGS.") ++ ++(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" ++ "VSX vector register to hold scalar float values or NO_REGS.") ++ ++(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" ++ "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") ++ ++;; Lq/stq validates the address for load/store quad ++(define_memory_constraint "wQ" ++ "Memory operand suitable for the load/store quad instructions" ++ (match_operand 0 "quad_memory_operand")) ++ + ;; Altivec style load/store that ignores the bottom bits of the address + (define_memory_constraint "wZ" + "Indexed or indirect memory operand, ignoring the bottom 4 bits" +--- a/src/gcc/config/rs6000/predicates.md ++++ b/src/gcc/config/rs6000/predicates.md +@@ -124,6 +124,11 @@ + (and (match_code "const_int") + (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) + ++;; Return 1 if op is a unsigned 3-bit constant integer. ++(define_predicate "u3bit_cint_operand" ++ (and (match_code "const_int") ++ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) ++ + ;; Return 1 if op is a unsigned 5-bit constant integer. + (define_predicate "u5bit_cint_operand" + (and (match_code "const_int") +@@ -135,6 +140,11 @@ + (and (match_code "const_int") + (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) + ++;; Return 1 if op is a unsigned 10-bit constant integer. ++(define_predicate "u10bit_cint_operand" ++ (and (match_code "const_int") ++ (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) ++ + ;; Return 1 if op is a constant integer that can fit in a D field. + (define_predicate "short_cint_operand" + (and (match_code "const_int") +@@ -166,6 +176,11 @@ + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) + ++;; Match op = 0..15 ++(define_predicate "const_0_to_15_operand" ++ (and (match_code "const_int") ++ (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) ++ + ;; Return 1 if op is a register that is not special. + (define_predicate "gpc_reg_operand" + (match_operand 0 "register_operand") +@@ -182,9 +197,95 @@ + if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op))) + return 1; + ++ if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) ++ return 1; ++ + return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); + }) + ++;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't ++;; allow floating point or vector registers. ++(define_predicate "int_reg_operand" ++ (match_operand 0 "register_operand") ++{ ++ if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) ++ return 0; ++ ++ if (GET_CODE (op) == SUBREG) ++ op = SUBREG_REG (op); ++ ++ if (!REG_P (op)) ++ return 0; ++ ++ if (REGNO (op) >= FIRST_PSEUDO_REGISTER) ++ return 1; ++ ++ return INT_REGNO_P (REGNO (op)); ++}) ++ ++;; Like int_reg_operand, but only return true for base registers ++(define_predicate "base_reg_operand" ++ (match_operand 0 "int_reg_operand") ++{ ++ if (GET_CODE (op) == SUBREG) ++ op = SUBREG_REG (op); ++ ++ if (!REG_P (op)) ++ return 0; ++ ++ return (REGNO (op) != FIRST_GPR_REGNO); ++}) ++ ++;; Return 1 if op is a HTM specific SPR register. ++(define_predicate "htm_spr_reg_operand" ++ (match_operand 0 "register_operand") ++{ ++ if (!TARGET_HTM) ++ return 0; ++ ++ if (GET_CODE (op) == SUBREG) ++ op = SUBREG_REG (op); ++ ++ if (!REG_P (op)) ++ return 0; ++ ++ switch (REGNO (op)) ++ { ++ case TFHAR_REGNO: ++ case TFIAR_REGNO: ++ case TEXASR_REGNO: ++ return 1; ++ default: ++ break; ++ } ++ ++ /* Unknown SPR. */ ++ return 0; ++}) ++ ++;; Return 1 if op is a general purpose register that is an even register ++;; which suitable for a load/store quad operation ++(define_predicate "quad_int_reg_operand" ++ (match_operand 0 "register_operand") ++{ ++ HOST_WIDE_INT r; ++ ++ if (!TARGET_QUAD_MEMORY) ++ return 0; ++ ++ if (GET_CODE (op) == SUBREG) ++ op = SUBREG_REG (op); ++ ++ if (!REG_P (op)) ++ return 0; ++ ++ r = REGNO (op); ++ if (r >= FIRST_PSEUDO_REGISTER) ++ return 1; ++ ++ return (INT_REGNO_P (r) && ((r & 1) == 0)); ++}) ++ + ;; Return 1 if op is a register that is a condition register field. + (define_predicate "cc_reg_operand" + (match_operand 0 "register_operand") +@@ -315,6 +416,11 @@ + && CONST_DOUBLE_HIGH (op) == 0") + (match_operand 0 "gpc_reg_operand")))) + ++;; Like reg_or_logical_cint_operand, but allow vsx registers ++(define_predicate "vsx_reg_or_cint_operand" ++ (ior (match_operand 0 "vsx_register_operand") ++ (match_operand 0 "reg_or_logical_cint_operand"))) ++ + ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register + ;; with no more than one instruction per word. + (define_predicate "easy_fp_constant" +@@ -333,6 +439,11 @@ + && mode != DImode) + return 1; + ++ /* The constant 0.0 is easy under VSX. */ ++ if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode) ++ && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode)) ++ return 1; ++ + if (DECIMAL_FLOAT_MODE_P (mode)) + return 0; + +@@ -521,6 +632,54 @@ + (and (match_operand 0 "memory_operand") + (match_test "offsettable_nonstrict_memref_p (op)"))) + ++;; Return 1 if the operand is suitable for load/store quad memory. ++(define_predicate "quad_memory_operand" ++ (match_code "mem") ++{ ++ rtx addr, op0, op1; ++ int ret; ++ ++ if (!TARGET_QUAD_MEMORY) ++ ret = 0; ++ ++ else if (!memory_operand (op, mode)) ++ ret = 0; ++ ++ else if (GET_MODE_SIZE (GET_MODE (op)) != 16) ++ ret = 0; ++ ++ else if (MEM_ALIGN (op) < 128) ++ ret = 0; ++ ++ else ++ { ++ addr = XEXP (op, 0); ++ if (int_reg_operand (addr, Pmode)) ++ ret = 1; ++ ++ else if (GET_CODE (addr) != PLUS) ++ ret = 0; ++ ++ else ++ { ++ op0 = XEXP (addr, 0); ++ op1 = XEXP (addr, 1); ++ ret = (int_reg_operand (op0, Pmode) ++ && GET_CODE (op1) == CONST_INT ++ && IN_RANGE (INTVAL (op1), -32768, 32767) ++ && (INTVAL (op1) & 15) == 0); ++ } ++ } ++ ++ if (TARGET_DEBUG_ADDR) ++ { ++ fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false"); ++ debug_rtx (op); ++ } ++ ++ return ret; ++}) ++ + ;; Return 1 if the operand is an indexed or indirect memory operand. + (define_predicate "indexed_or_indirect_operand" + (match_code "mem") +@@ -535,6 +694,19 @@ + return indexed_or_indirect_address (op, mode); + }) + ++;; Like indexed_or_indirect_operand, but also allow a GPR register if direct ++;; moves are supported. ++(define_predicate "reg_or_indexed_operand" ++ (match_code "mem,reg") ++{ ++ if (MEM_P (op)) ++ return indexed_or_indirect_operand (op, mode); ++ else if (TARGET_DIRECT_MOVE) ++ return register_operand (op, mode); ++ return ++ 0; ++}) ++ + ;; Return 1 if the operand is an indexed or indirect memory operand with an + ;; AND -16 in it, used to recognize when we need to switch to Altivec loads + ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, +@@ -560,6 +732,28 @@ + && REG_P (XEXP (op, 1)))") + (match_operand 0 "address_operand"))) + ++;; Return 1 if the operand is an index-form address. ++(define_special_predicate "indexed_address" ++ (match_test "(GET_CODE (op) == PLUS ++ && REG_P (XEXP (op, 0)) ++ && REG_P (XEXP (op, 1)))")) ++ ++;; Return 1 if the operand is a MEM with an update-form address. This may ++;; also include update-indexed form. ++(define_special_predicate "update_address_mem" ++ (match_test "(MEM_P (op) ++ && (GET_CODE (XEXP (op, 0)) == PRE_INC ++ || GET_CODE (XEXP (op, 0)) == PRE_DEC ++ || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) ++ ++;; Return 1 if the operand is a MEM with an update-indexed-form address. Note ++;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the ++;; increment is based on the mode size and will therefor always be a const. ++(define_special_predicate "update_indexed_address_mem" ++ (match_test "(MEM_P (op) ++ && GET_CODE (XEXP (op, 0)) == PRE_MODIFY ++ && indexed_address (XEXP (XEXP (op, 0), 1), mode))")) ++ + ;; Used for the destination of the fix_truncdfsi2 expander. + ;; If stfiwx will be used, the result goes to memory; otherwise, + ;; we're going to emit a store and a load of a subreg, so the dest is a +@@ -883,7 +1077,8 @@ + (and (match_code "symbol_ref") + (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) + && ((SYMBOL_REF_LOCAL_P (op) +- && (DEFAULT_ABI != ABI_AIX ++ && ((DEFAULT_ABI != ABI_AIX ++ && DEFAULT_ABI != ABI_ELFv2) + || !SYMBOL_REF_EXTERNAL_P (op))) + || (op == XEXP (DECL_RTL (current_function_decl), + 0)))"))) +@@ -1364,6 +1559,26 @@ + return 1; + }) + ++;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. ++(define_predicate "crsave_operation" ++ (match_code "parallel") ++{ ++ int count = XVECLEN (op, 0); ++ int i; ++ ++ for (i = 1; i < count; i++) ++ { ++ rtx exp = XVECEXP (op, 0, i); ++ ++ if (GET_CODE (exp) != USE ++ || GET_CODE (XEXP (exp, 0)) != REG ++ || GET_MODE (XEXP (exp, 0)) != CCmode ++ || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) ++ return 0; ++ } ++ return 1; ++}) ++ + ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. + (define_predicate "lmw_operation" + (match_code "parallel") +@@ -1534,3 +1749,99 @@ + + return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; + }) ++ ++;; Match the first insn (addis) in fusing the combination of addis and loads to ++;; GPR registers on power8. ++(define_predicate "fusion_gpr_addis" ++ (match_code "const_int,high,plus") ++{ ++ HOST_WIDE_INT value; ++ rtx int_const; ++ ++ if (GET_CODE (op) == HIGH) ++ return 1; ++ ++ if (CONST_INT_P (op)) ++ int_const = op; ++ ++ else if (GET_CODE (op) == PLUS ++ && base_reg_operand (XEXP (op, 0), Pmode) ++ && CONST_INT_P (XEXP (op, 1))) ++ int_const = XEXP (op, 1); ++ ++ else ++ return 0; ++ ++ /* Power8 currently will only do the fusion if the top 11 bits of the addis ++ value are all 1's or 0's. */ ++ value = INTVAL (int_const); ++ if ((value & (HOST_WIDE_INT)0xffff) != 0) ++ return 0; ++ ++ if ((value & (HOST_WIDE_INT)0xffff0000) == 0) ++ return 0; ++ ++ return (IN_RANGE (value >> 16, -32, 31)); ++}) ++ ++;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis ++;; and loads to GPR registers on power8. ++(define_predicate "fusion_gpr_mem_load" ++ (match_code "mem,sign_extend,zero_extend") ++{ ++ rtx addr; ++ ++ /* Handle sign/zero extend. */ ++ if (GET_CODE (op) == ZERO_EXTEND ++ || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) ++ { ++ op = XEXP (op, 0); ++ mode = GET_MODE (op); ++ } ++ ++ if (!MEM_P (op)) ++ return 0; ++ ++ switch (mode) ++ { ++ case QImode: ++ case HImode: ++ case SImode: ++ break; ++ ++ case DImode: ++ if (!TARGET_POWERPC64) ++ return 0; ++ break; ++ ++ default: ++ return 0; ++ } ++ ++ addr = XEXP (op, 0); ++ if (GET_CODE (addr) == PLUS) ++ { ++ rtx base = XEXP (addr, 0); ++ rtx offset = XEXP (addr, 1); ++ ++ return (base_reg_operand (base, GET_MODE (base)) ++ && satisfies_constraint_I (offset)); ++ } ++ ++ else if (GET_CODE (addr) == LO_SUM) ++ { ++ rtx base = XEXP (addr, 0); ++ rtx offset = XEXP (addr, 1); ++ ++ if (!base_reg_operand (base, GET_MODE (base))) ++ return 0; ++ ++ else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) ++ return small_toc_ref (offset, GET_MODE (offset)); ++ ++ else if (TARGET_ELF && !TARGET_POWERPC64) ++ return CONSTANT_P (offset); ++ } ++ ++ return 0; ++}) +--- a/src/gcc/config/rs6000/ppc-asm.h ++++ b/src/gcc/config/rs6000/ppc-asm.h +@@ -256,7 +256,30 @@ + * the real function with one or two leading periods respectively. + */ + +-#if defined (__powerpc64__) ++#if defined(__powerpc64__) && _CALL_ELF == 2 ++ ++/* Defining "toc" above breaks @toc in assembler code. */ ++#undef toc ++ ++#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name) ++#define JUMP_TARGET(name) FUNC_NAME(name) ++#define FUNC_START(name) \ ++ .type FUNC_NAME(name),@function; \ ++ .globl FUNC_NAME(name); \ ++FUNC_NAME(name): \ ++0: addis 2,12,(.TOC.-0b)@ha; \ ++ addi 2,2,(.TOC.-0b)@l; \ ++ .localentry FUNC_NAME(name),.-FUNC_NAME(name) ++ ++#define HIDDEN_FUNC(name) \ ++ FUNC_START(name) \ ++ .hidden FUNC_NAME(name); ++ ++#define FUNC_END(name) \ ++ .size FUNC_NAME(name),.-FUNC_NAME(name) ++ ++#elif defined (__powerpc64__) ++ + #define FUNC_NAME(name) GLUE(.,name) + #define JUMP_TARGET(name) FUNC_NAME(name) + #define FUNC_START(name) \ +--- a/src/gcc/config/rs6000/htm.md ++++ b/src/gcc/config/rs6000/htm.md +@@ -0,0 +1,366 @@ ++;; Hardware Transactional Memory (HTM) patterns. ++;; Copyright (C) 2013 Free Software Foundation, Inc. ++;; Contributed by Peter Bergner . ++ ++;; This file is part of GCC. ++ ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 3, or (at your ++;; option) any later version. ++ ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++ ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_constants ++ [(TFHAR_SPR 128) ++ (TFIAR_SPR 129) ++ (TEXASR_SPR 130) ++ (TEXASRU_SPR 131) ++ (MAX_HTM_OPERANDS 4) ++ ]) ++ ++;; ++;; UNSPEC_VOLATILE usage ++;; ++ ++(define_c_enum "unspecv" ++ [UNSPECV_HTM_TABORT ++ UNSPECV_HTM_TABORTDC ++ UNSPECV_HTM_TABORTDCI ++ UNSPECV_HTM_TABORTWC ++ UNSPECV_HTM_TABORTWCI ++ UNSPECV_HTM_TBEGIN ++ UNSPECV_HTM_TCHECK ++ UNSPECV_HTM_TEND ++ UNSPECV_HTM_TRECHKPT ++ UNSPECV_HTM_TRECLAIM ++ UNSPECV_HTM_TSR ++ UNSPECV_HTM_MFSPR ++ UNSPECV_HTM_MTSPR ++ ]) ++ ++ ++(define_expand "tabort" ++ [(set (match_dup 2) ++ (unspec_volatile:CC [(match_operand:SI 1 "int_reg_operand" "")] ++ UNSPECV_HTM_TABORT)) ++ (set (match_dup 3) ++ (eq:SI (match_dup 2) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 3)))] ++ "TARGET_HTM" ++{ ++ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tabort_internal" ++ [(set (match_operand:CC 1 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand:SI 0 "int_reg_operand" "r")] ++ UNSPECV_HTM_TABORT))] ++ "TARGET_HTM" ++ "tabort. %0" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tabortdc" ++ [(set (match_dup 4) ++ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") ++ (match_operand:SI 2 "gpc_reg_operand" "r") ++ (match_operand:SI 3 "gpc_reg_operand" "r")] ++ UNSPECV_HTM_TABORTDC)) ++ (set (match_dup 5) ++ (eq:SI (match_dup 4) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 5)))] ++ "TARGET_HTM" ++{ ++ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[5] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tabortdc_internal" ++ [(set (match_operand:CC 3 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") ++ (match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPECV_HTM_TABORTDC))] ++ "TARGET_HTM" ++ "tabortdc. %0,%1,%2" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tabortdci" ++ [(set (match_dup 4) ++ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") ++ (match_operand:SI 2 "gpc_reg_operand" "r") ++ (match_operand 3 "s5bit_cint_operand" "n")] ++ UNSPECV_HTM_TABORTDCI)) ++ (set (match_dup 5) ++ (eq:SI (match_dup 4) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 5)))] ++ "TARGET_HTM" ++{ ++ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[5] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tabortdci_internal" ++ [(set (match_operand:CC 3 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") ++ (match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand 2 "s5bit_cint_operand" "n")] ++ UNSPECV_HTM_TABORTDCI))] ++ "TARGET_HTM" ++ "tabortdci. %0,%1,%2" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tabortwc" ++ [(set (match_dup 4) ++ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") ++ (match_operand:SI 2 "gpc_reg_operand" "r") ++ (match_operand:SI 3 "gpc_reg_operand" "r")] ++ UNSPECV_HTM_TABORTWC)) ++ (set (match_dup 5) ++ (eq:SI (match_dup 4) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 5)))] ++ "TARGET_HTM" ++{ ++ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[5] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tabortwc_internal" ++ [(set (match_operand:CC 3 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") ++ (match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPECV_HTM_TABORTWC))] ++ "TARGET_HTM" ++ "tabortwc. %0,%1,%2" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tabortwci" ++ [(set (match_dup 4) ++ (unspec_volatile:CC [(match_operand 1 "u5bit_cint_operand" "n") ++ (match_operand:SI 2 "gpc_reg_operand" "r") ++ (match_operand 3 "s5bit_cint_operand" "n")] ++ UNSPECV_HTM_TABORTWCI)) ++ (set (match_dup 5) ++ (eq:SI (match_dup 4) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 5)))] ++ "TARGET_HTM" ++{ ++ operands[4] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[5] = gen_reg_rtx (SImode); ++}) ++ ++(define_expand "ttest" ++ [(set (match_dup 1) ++ (unspec_volatile:CC [(const_int 0) ++ (reg:SI 0) ++ (const_int 0)] ++ UNSPECV_HTM_TABORTWCI)) ++ (set (subreg:CC (match_dup 2) 0) (match_dup 1)) ++ (set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 24))) ++ (parallel [(set (match_operand:SI 0 "int_reg_operand" "") ++ (and:SI (match_dup 3) (const_int 15))) ++ (clobber (scratch:CC))])] ++ "TARGET_HTM" ++{ ++ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[2] = gen_reg_rtx (SImode); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tabortwci_internal" ++ [(set (match_operand:CC 3 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") ++ (match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand 2 "s5bit_cint_operand" "n")] ++ UNSPECV_HTM_TABORTWCI))] ++ "TARGET_HTM" ++ "tabortwci. %0,%1,%2" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tbegin" ++ [(set (match_dup 2) ++ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")] ++ UNSPECV_HTM_TBEGIN)) ++ (set (match_dup 3) ++ (eq:SI (match_dup 2) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 3)))] ++ "TARGET_HTM" ++{ ++ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tbegin_internal" ++ [(set (match_operand:CC 1 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] ++ UNSPECV_HTM_TBEGIN))] ++ "TARGET_HTM" ++ "tbegin. %0" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tcheck" ++ [(set (match_dup 2) ++ (unspec_volatile:CC [(match_operand 1 "u3bit_cint_operand" "n")] ++ UNSPECV_HTM_TCHECK)) ++ (set (match_dup 3) ++ (eq:SI (match_dup 2) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 3)))] ++ "TARGET_HTM" ++{ ++ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tcheck_internal" ++ [(set (match_operand:CC 1 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "u3bit_cint_operand" "n")] ++ UNSPECV_HTM_TCHECK))] ++ "TARGET_HTM" ++ "tcheck. %0" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tend" ++ [(set (match_dup 2) ++ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")] ++ UNSPECV_HTM_TEND)) ++ (set (match_dup 3) ++ (eq:SI (match_dup 2) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 3)))] ++ "TARGET_HTM" ++{ ++ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tend_internal" ++ [(set (match_operand:CC 1 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] ++ UNSPECV_HTM_TEND))] ++ "TARGET_HTM" ++ "tend. %0" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "trechkpt" ++ [(set (match_dup 1) ++ (unspec_volatile:CC [(const_int 0)] ++ UNSPECV_HTM_TRECHKPT)) ++ (set (match_dup 2) ++ (eq:SI (match_dup 1) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 2)))] ++ "TARGET_HTM" ++{ ++ operands[1] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[2] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*trechkpt_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(const_int 0)] ++ UNSPECV_HTM_TRECHKPT))] ++ "TARGET_HTM" ++ "trechkpt." ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "treclaim" ++ [(set (match_dup 2) ++ (unspec_volatile:CC [(match_operand:SI 1 "gpc_reg_operand" "r")] ++ UNSPECV_HTM_TRECLAIM)) ++ (set (match_dup 3) ++ (eq:SI (match_dup 2) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 3)))] ++ "TARGET_HTM" ++{ ++ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*treclaim_internal" ++ [(set (match_operand:CC 1 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")] ++ UNSPECV_HTM_TRECLAIM))] ++ "TARGET_HTM" ++ "treclaim. %0" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_expand "tsr" ++ [(set (match_dup 2) ++ (unspec_volatile:CC [(match_operand 1 "const_0_to_1_operand" "n")] ++ UNSPECV_HTM_TSR)) ++ (set (match_dup 3) ++ (eq:SI (match_dup 2) ++ (const_int 0))) ++ (set (match_operand:SI 0 "int_reg_operand" "") ++ (minus:SI (const_int 1) (match_dup 3)))] ++ "TARGET_HTM" ++{ ++ operands[2] = gen_rtx_REG (CCmode, CR0_REGNO); ++ operands[3] = gen_reg_rtx (SImode); ++}) ++ ++(define_insn "*tsr_internal" ++ [(set (match_operand:CC 1 "cc_reg_operand" "=x") ++ (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] ++ UNSPECV_HTM_TSR))] ++ "TARGET_HTM" ++ "tsr. %0" ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_insn "htm_mfspr_" ++ [(set (match_operand:P 0 "gpc_reg_operand" "=r") ++ (unspec_volatile:P [(match_operand 1 "u10bit_cint_operand" "n") ++ (match_operand:P 2 "htm_spr_reg_operand" "")] ++ UNSPECV_HTM_MFSPR))] ++ "TARGET_HTM" ++ "mfspr %0,%1"; ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) ++ ++(define_insn "htm_mtspr_" ++ [(set (match_operand:P 2 "htm_spr_reg_operand" "") ++ (unspec_volatile:P [(match_operand:P 0 "gpc_reg_operand" "r") ++ (match_operand 1 "u10bit_cint_operand" "n")] ++ UNSPECV_HTM_MTSPR))] ++ "TARGET_HTM" ++ "mtspr %1,%0"; ++ [(set_attr "type" "htm") ++ (set_attr "length" "4")]) +--- a/src/gcc/config/rs6000/rs6000-modes.def ++++ b/src/gcc/config/rs6000/rs6000-modes.def +@@ -41,3 +41,8 @@ + VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ + VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ + VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ ++ ++/* Replacement for TImode that only is allowed in GPRs. We also use PTImode ++ for quad memory atomic operations to force getting an even/odd register ++ combination. */ ++PARTIAL_INT_MODE (TI); +--- a/src/gcc/config/rs6000/rs6000-cpus.def ++++ b/src/gcc/config/rs6000/rs6000-cpus.def +@@ -28,7 +28,7 @@ + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +-#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ ++#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ +@@ -38,12 +38,23 @@ + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ ++ /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until ++ PR 58587 is fixed. */ + #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) + #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + ++/* For now, don't provide an embedded version of ISA 2.07. */ ++#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ ++ | OPTION_MASK_P8_FUSION \ ++ | OPTION_MASK_P8_VECTOR \ ++ | OPTION_MASK_CRYPTO \ ++ | OPTION_MASK_DIRECT_MOVE \ ++ | OPTION_MASK_HTM \ ++ | OPTION_MASK_QUAD_MEMORY) ++ + #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + + /* Deal with ports that do not have -mstrict-align. */ +@@ -60,23 +71,30 @@ + /* Mask of all options to set the default isa flags based on -mcpu=. */ + #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_CMPB \ ++ | OPTION_MASK_CRYPTO \ + | OPTION_MASK_DFP \ ++ | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ ++ | OPTION_MASK_HTM \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_UPDATE \ ++ | OPTION_MASK_P8_FUSION \ ++ | OPTION_MASK_P8_VECTOR \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ ++ | OPTION_MASK_QUAD_MEMORY \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ +- | OPTION_MASK_VSX) ++ | OPTION_MASK_VSX \ ++ | OPTION_MASK_VSX_TIMODE) + + #endif + +@@ -166,10 +184,7 @@ + POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF + | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD + | MASK_VSX | MASK_RECIP_PRECISION) +-RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ +- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF +- | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD +- | MASK_VSX | MASK_RECIP_PRECISION) ++RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) + RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) + RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) + RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) +--- a/src/gcc/config/rs6000/htmintrin.h ++++ b/src/gcc/config/rs6000/htmintrin.h +@@ -0,0 +1,131 @@ ++/* Hardware Transactional Memory (HTM) intrinsics. ++ Copyright (C) 2013 Free Software Foundation, Inc. ++ Contributed by Peter Bergner . ++ ++ This file is free software; you can redistribute it and/or modify it under ++ the terms of the GNU General Public License as published by the Free ++ Software Foundation; either version 3 of the License, or (at your option) ++ any later version. ++ ++ This file is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++#ifndef __HTM__ ++# error "HTM instruction set not enabled" ++#endif /* __HTM__ */ ++ ++#ifndef _HTMINTRIN_H ++#define _HTMINTRIN_H ++ ++#include ++ ++typedef uint64_t texasr_t; ++typedef uint32_t texasru_t; ++typedef uint32_t texasrl_t; ++typedef uintptr_t tfiar_t; ++typedef uintptr_t tfhar_t; ++ ++#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) ++#define _HTM_NONTRANSACTIONAL 0x0 ++#define _HTM_SUSPENDED 0x1 ++#define _HTM_TRANSACTIONAL 0x2 ++ ++/* The following macros use the IBM bit numbering for BITNUM ++ as used in the ISA documentation. */ ++ ++#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ ++ (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1)) ++#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \ ++ (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1)) ++ ++#define _TEXASR_FAILURE_CODE(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 7, 8) ++#define _TEXASRU_FAILURE_CODE(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8) ++ ++#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 7, 1) ++#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1) ++ ++#define _TEXASR_DISALLOWED(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 8, 1) ++#define _TEXASRU_DISALLOWED(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1) ++ ++#define _TEXASR_NESTING_OVERFLOW(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 9, 1) ++#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1) ++ ++#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 10, 1) ++#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1) ++ ++#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 11, 1) ++#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1) ++ ++#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 12, 1) ++#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1) ++ ++#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 13, 1) ++#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1) ++ ++#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 14, 1) ++#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1) ++ ++#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 15, 1) ++#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1) ++ ++#define _TEXASR_INSRUCTION_FETCH_CONFLICT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 16, 1) ++#define _TEXASRU_INSRUCTION_FETCH_CONFLICT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1) ++ ++#define _TEXASR_ABORT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 31, 1) ++#define _TEXASRU_ABORT(TEXASRU) \ ++ _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1) ++ ++ ++#define _TEXASR_SUSPENDED(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 32, 1) ++ ++#define _TEXASR_PRIVILEGE(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 35, 2) ++ ++#define _TEXASR_FAILURE_SUMMARY(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 36, 1) ++ ++#define _TEXASR_TFIAR_EXACT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 37, 1) ++ ++#define _TEXASR_ROT(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 38, 1) ++ ++#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \ ++ _TEXASR_EXTRACT_BITS(TEXASR, 63, 12) ++ ++#endif /* _HTMINTRIN_H */ +--- a/src/gcc/config/rs6000/rs6000-protos.h ++++ b/src/gcc/config/rs6000/rs6000-protos.h +@@ -50,11 +50,13 @@ + extern rtx find_addr_reg (rtx); + extern rtx gen_easy_altivec_constant (rtx); + extern const char *output_vec_const_move (rtx *); ++extern const char *rs6000_output_move_128bit (rtx *); + extern void rs6000_expand_vector_init (rtx, rtx); + extern void paired_expand_vector_init (rtx, rtx); + extern void rs6000_expand_vector_set (rtx, rtx, int); + extern void rs6000_expand_vector_extract (rtx, rtx, int); + extern bool altivec_expand_vec_perm_const (rtx op[4]); ++extern void altivec_expand_vec_perm_le (rtx op[4]); + extern bool rs6000_expand_vec_perm_const (rtx op[4]); + extern void rs6000_expand_extract_even (rtx, rtx, rtx); + extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); +@@ -70,6 +72,11 @@ + extern int registers_ok_for_quad_peep (rtx, rtx); + extern int mems_ok_for_quad_peep (rtx, rtx); + extern bool gpr_or_gpr_p (rtx, rtx); ++extern bool direct_move_p (rtx, rtx); ++extern bool quad_load_store_p (rtx, rtx); ++extern bool fusion_gpr_load_p (rtx *, bool); ++extern void expand_fusion_gpr_load (rtx *); ++extern const char *emit_fusion_gpr_load (rtx *); + extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, + enum reg_class); + extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class, +@@ -116,6 +123,7 @@ + extern void rs6000_fatal_bad_address (rtx); + extern rtx create_TOC_reference (rtx, rtx); + extern void rs6000_split_multireg_move (rtx, rtx); ++extern void rs6000_emit_le_vsx_move (rtx, rtx, enum machine_mode); + extern void rs6000_emit_move (rtx, rtx, enum machine_mode); + extern rtx rs6000_secondary_memory_needed_rtx (enum machine_mode); + extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, +@@ -135,6 +143,7 @@ + extern rtx rs6000_address_for_altivec (rtx); + extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool); + extern int rs6000_loop_align (rtx); ++extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx); + #endif /* RTX_CODE */ + + #ifdef TREE_CODE +@@ -146,6 +155,7 @@ + extern rtx rs6000_libcall_value (enum machine_mode); + extern rtx rs6000_va_arg (tree, tree); + extern int function_ok_for_sibcall (tree); ++extern int rs6000_reg_parm_stack_space (tree); + extern void rs6000_elf_declare_function_name (FILE *, const char *, tree); + extern bool rs6000_elf_in_small_data_p (const_tree); + #ifdef ARGS_SIZE_RTX +@@ -170,7 +180,8 @@ + extern void rs6000_emit_epilogue (int); + extern void rs6000_emit_eh_reg_restore (rtx, rtx); + extern const char * output_isel (rtx *); +-extern void rs6000_call_indirect_aix (rtx, rtx, rtx); ++extern void rs6000_call_aix (rtx, rtx, rtx, rtx); ++extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx); + extern void rs6000_aix_asm_output_dwarf_table_ref (char *); + extern void get_ppc476_thunk_name (char name[32]); + extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); +--- a/src/gcc/config/rs6000/t-rs6000 ++++ b/src/gcc/config/rs6000/t-rs6000 +@@ -60,6 +60,7 @@ + $(srcdir)/config/rs6000/power5.md \ + $(srcdir)/config/rs6000/power6.md \ + $(srcdir)/config/rs6000/power7.md \ ++ $(srcdir)/config/rs6000/power8.md \ + $(srcdir)/config/rs6000/cell.md \ + $(srcdir)/config/rs6000/xfpu.md \ + $(srcdir)/config/rs6000/a2.md \ +@@ -70,6 +71,8 @@ + $(srcdir)/config/rs6000/vector.md \ + $(srcdir)/config/rs6000/vsx.md \ + $(srcdir)/config/rs6000/altivec.md \ ++ $(srcdir)/config/rs6000/crypto.md \ ++ $(srcdir)/config/rs6000/htm.md \ + $(srcdir)/config/rs6000/spe.md \ + $(srcdir)/config/rs6000/dfp.md \ + $(srcdir)/config/rs6000/paired.md +--- a/src/gcc/config/rs6000/htmxlintrin.h ++++ b/src/gcc/config/rs6000/htmxlintrin.h +@@ -0,0 +1,208 @@ ++/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics. ++ Copyright (C) 2013 Free Software Foundation, Inc. ++ Contributed by Peter Bergner . ++ ++ This file is free software; you can redistribute it and/or modify it under ++ the terms of the GNU General Public License as published by the Free ++ Software Foundation; either version 3 of the License, or (at your option) ++ any later version. ++ ++ This file is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++#ifndef __HTM__ ++# error "HTM instruction set not enabled" ++#endif /* __HTM__ */ ++ ++#ifndef _HTMXLINTRIN_H ++#define _HTMXLINTRIN_H ++ ++#include ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define _TEXASR_PTR(TM_BUF) \ ++ ((texasr_t *)((TM_BUF)+0)) ++#define _TEXASRU_PTR(TM_BUF) \ ++ ((texasru_t *)((TM_BUF)+0)) ++#define _TEXASRL_PTR(TM_BUF) \ ++ ((texasrl_t *)((TM_BUF)+4)) ++#define _TFIAR_PTR(TM_BUF) \ ++ ((tfiar_t *)((TM_BUF)+8)) ++ ++typedef char TM_buff_type[16]; ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_simple_begin (void) ++{ ++ if (__builtin_expect (__builtin_tbegin (0), 1)) ++ return 1; ++ return 0; ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_begin (void* const TM_buff) ++{ ++ *_TEXASRL_PTR (TM_buff) = 0; ++ if (__builtin_expect (__builtin_tbegin (0), 1)) ++ return 1; ++#ifdef __powerpc64__ ++ *_TEXASR_PTR (TM_buff) = __builtin_get_texasr (); ++#else ++ *_TEXASRU_PTR (TM_buff) = __builtin_get_texasru (); ++ *_TEXASRL_PTR (TM_buff) = __builtin_get_texasr (); ++#endif ++ *_TFIAR_PTR (TM_buff) = __builtin_get_tfiar (); ++ return 0; ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_end (void) ++{ ++ if (__builtin_expect (__builtin_tend (0), 1)) ++ return 1; ++ return 0; ++} ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_abort (void) ++{ ++ __builtin_tabort (0); ++} ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_named_abort (unsigned char const code) ++{ ++ __builtin_tabort (code); ++} ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_resume (void) ++{ ++ __builtin_tresume (); ++} ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_suspend (void) ++{ ++ __builtin_tsuspend (); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_user_abort (void* const TM_buff) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ return _TEXASRU_ABORT (texasru); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_named_user_abort (void* const TM_buff, unsigned char *code) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ ++ *code = _TEXASRU_FAILURE_CODE (texasru); ++ return _TEXASRU_ABORT (texasru); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_illegal (void* const TM_buff) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ return _TEXASRU_DISALLOWED (texasru); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_footprint_exceeded (void* const TM_buff) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ return _TEXASRU_FOOTPRINT_OVERFLOW (texasru); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_nesting_depth (void* const TM_buff) ++{ ++ texasrl_t texasrl; ++ ++ if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL) ++ { ++ texasrl = *_TEXASRL_PTR (TM_buff); ++ if (!_TEXASR_FAILURE_SUMMARY (texasrl)) ++ texasrl = 0; ++ } ++ else ++ texasrl = (texasrl_t) __builtin_get_texasr (); ++ ++ return _TEXASR_TRANSACTION_LEVEL (texasrl); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_nested_too_deep(void* const TM_buff) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ return _TEXASRU_NESTING_OVERFLOW (texasru); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_conflict(void* const TM_buff) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ /* Return TEXASR bits 11 (Self-Induced Conflict) through ++ 14 (Translation Invalidation Conflict). */ ++ return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0; ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_is_failure_persistent(void* const TM_buff) ++{ ++ texasru_t texasru = *_TEXASRU_PTR (TM_buff); ++ return _TEXASRU_FAILURE_PERSISTENT (texasru); ++} ++ ++extern __inline long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_failure_address(void* const TM_buff) ++{ ++ return *_TFIAR_PTR (TM_buff); ++} ++ ++extern __inline long long ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__TM_failure_code(void* const TM_buff) ++{ ++ return *_TEXASR_PTR (TM_buff); ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _HTMXLINTRIN_H */ +--- a/src/gcc/config/rs6000/rs6000-builtin.def ++++ b/src/gcc/config/rs6000/rs6000-builtin.def +@@ -30,7 +30,8 @@ + RS6000_BUILTIN_A -- ABS builtins + RS6000_BUILTIN_D -- DST builtins + RS6000_BUILTIN_E -- SPE EVSEL builtins. +- RS6000_BUILTIN_P -- Altivec and VSX predicate builtins ++ RS6000_BUILTIN_H -- HTM builtins ++ RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins + RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins + RS6000_BUILTIN_S -- SPE predicate builtins + RS6000_BUILTIN_X -- special builtins +@@ -66,6 +67,10 @@ + #error "RS6000_BUILTIN_E is not defined." + #endif + ++#ifndef RS6000_BUILTIN_H ++ #error "RS6000_BUILTIN_H is not defined." ++#endif ++ + #ifndef RS6000_BUILTIN_P + #error "RS6000_BUILTIN_P is not defined." + #endif +@@ -301,6 +306,158 @@ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_nothing) /* ICODE */ + ++/* ISA 2.07 (power8) vector convenience macros. */ ++/* For the instructions that are encoded as altivec instructions use ++ __builtin_altivec_ as the builtin name. */ ++#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_altivec_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_altivec_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_altivec_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_PREDICATE), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++/* For the instructions encoded as VSX instructions use __builtin_vsx as the ++ builtin name. */ ++#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_vsx_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_P8V_OVERLOAD_1(ENUM, NAME) \ ++ RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ ++ "__builtin_vec_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_OVERLOADED /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_nothing) /* ICODE */ ++ ++#define BU_P8V_OVERLOAD_2(ENUM, NAME) \ ++ RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ ++ "__builtin_vec_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_OVERLOADED /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_nothing) /* ICODE */ ++ ++/* Crypto convenience macros. */ ++#define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_crypto_" NAME, /* NAME */ \ ++ RS6000_BTM_CRYPTO, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_crypto_" NAME, /* NAME */ \ ++ RS6000_BTM_CRYPTO, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_crypto_" NAME, /* NAME */ \ ++ RS6000_BTM_CRYPTO, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_TERNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \ ++ RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_crypto_" NAME, /* NAME */ \ ++ RS6000_BTM_CRYPTO, /* MASK */ \ ++ (RS6000_BTC_OVERLOADED /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_nothing) /* ICODE */ ++ ++#define BU_CRYPTO_OVERLOAD_2(ENUM, NAME) \ ++ RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_crypto_" NAME, /* NAME */ \ ++ RS6000_BTM_CRYPTO, /* MASK */ \ ++ (RS6000_BTC_OVERLOADED /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_nothing) /* ICODE */ ++ ++#define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \ ++ RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_crypto_" NAME, /* NAME */ \ ++ RS6000_BTM_CRYPTO, /* MASK */ \ ++ (RS6000_BTC_OVERLOADED /* ATTR */ \ ++ | RS6000_BTC_TERNARY), \ ++ CODE_FOR_nothing) /* ICODE */ ++ ++/* HTM convenience macros. */ ++#define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HTM, /* MASK */ \ ++ RS6000_BTC_ ## ATTR, /* ATTR */ \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HTM, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HTM, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HTM, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_TERNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_HTM_SPR0(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HTM, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_SPR), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_HTM_SPR1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HTM, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY \ ++ | RS6000_BTC_SPR \ ++ | RS6000_BTC_VOID), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ + /* SPE convenience macros. */ + #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ +@@ -1012,7 +1169,7 @@ + BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2) + + BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp) +-BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvdpsp) ++BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp) + BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp) + BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp) + BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe) +@@ -1052,9 +1209,9 @@ + + BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) + BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) +-BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, vsx_floordf2) +-BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, vsx_ceildf2) +-BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, vsx_btruncdf2) ++BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2) ++BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2) ++BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2) + + /* VSX predicate functions. */ + BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) +@@ -1132,6 +1289,166 @@ + BU_VSX_OVERLOAD_X (LD, "ld") + BU_VSX_OVERLOAD_X (ST, "st") + ++/* 1 argument VSX instructions added in ISA 2.07. */ ++BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn) ++BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn) ++ ++/* 1 argument altivec instructions added in ISA 2.07. */ ++BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) ++BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw) ++BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw) ++BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2) ++BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2) ++BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2) ++BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2) ++BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2) ++BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2) ++BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2) ++BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2) ++BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd) ++ ++/* 2 argument altivec instructions added in ISA 2.07. */ ++BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3) ++BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3) ++BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3) ++BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) ++BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) ++BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew) ++BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow) ++BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum) ++BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss) ++BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus) ++BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpkswus) ++BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3) ++BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3) ++BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3) ++BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3) ++BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3) ++ ++BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3) ++BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3) ++BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3) ++BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3) ++BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3) ++BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3) ++ ++BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3) ++BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3) ++BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3) ++BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3) ++BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3) ++BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3) ++ ++BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3) ++BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3) ++BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3) ++BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3) ++BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3) ++BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) ++ ++/* Vector comparison instructions added in ISA 2.07. */ ++BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) ++BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di) ++BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di) ++ ++/* Vector comparison predicate instructions added in ISA 2.07. */ ++BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p) ++BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p) ++BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p) ++ ++/* ISA 2.07 vector overloaded 1 argument functions. */ ++BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw") ++BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw") ++BU_P8V_OVERLOAD_1 (VCLZ, "vclz") ++BU_P8V_OVERLOAD_1 (VCLZB, "vclzb") ++BU_P8V_OVERLOAD_1 (VCLZH, "vclzh") ++BU_P8V_OVERLOAD_1 (VCLZW, "vclzw") ++BU_P8V_OVERLOAD_1 (VCLZD, "vclzd") ++BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt") ++BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb") ++BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth") ++BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw") ++BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd") ++BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd") ++ ++/* ISA 2.07 vector overloaded 2 argument functions. */ ++BU_P8V_OVERLOAD_2 (EQV, "eqv") ++BU_P8V_OVERLOAD_2 (NAND, "nand") ++BU_P8V_OVERLOAD_2 (ORC, "orc") ++BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm") ++BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd") ++BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud") ++BU_P8V_OVERLOAD_2 (VMINSD, "vminsd") ++BU_P8V_OVERLOAD_2 (VMINUD, "vminud") ++BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew") ++BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow") ++BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss") ++BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus") ++BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum") ++BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus") ++BU_P8V_OVERLOAD_2 (VRLD, "vrld") ++BU_P8V_OVERLOAD_2 (VSLD, "vsld") ++BU_P8V_OVERLOAD_2 (VSRAD, "vsrad") ++BU_P8V_OVERLOAD_2 (VSRD, "vsrd") ++BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") ++ ++ ++/* 1 argument crypto functions. */ ++BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) ++ ++/* 2 argument crypto functions. */ ++BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher) ++BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", CONST, crypto_vcipherlast) ++BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher) ++BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", CONST, crypto_vncipherlast) ++BU_CRYPTO_2 (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb) ++BU_CRYPTO_2 (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh) ++BU_CRYPTO_2 (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw) ++BU_CRYPTO_2 (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd) ++ ++/* 3 argument crypto functions. */ ++BU_CRYPTO_3 (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di) ++BU_CRYPTO_3 (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si) ++BU_CRYPTO_3 (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi) ++BU_CRYPTO_3 (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi) ++BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw) ++BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad) ++ ++/* 2 argument crypto overloaded functions. */ ++BU_CRYPTO_OVERLOAD_2 (VPMSUM, "vpmsum") ++ ++/* 3 argument crypto overloaded functions. */ ++BU_CRYPTO_OVERLOAD_3 (VPERMXOR, "vpermxor") ++BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") ++ ++ ++/* HTM functions. */ ++BU_HTM_1 (TABORT, "tabort", MISC, tabort) ++BU_HTM_3 (TABORTDC, "tabortdc", MISC, tabortdc) ++BU_HTM_3 (TABORTDCI, "tabortdci", MISC, tabortdci) ++BU_HTM_3 (TABORTWC, "tabortwc", MISC, tabortwc) ++BU_HTM_3 (TABORTWCI, "tabortwci", MISC, tabortwci) ++BU_HTM_1 (TBEGIN, "tbegin", MISC, tbegin) ++BU_HTM_1 (TCHECK, "tcheck", MISC, tcheck) ++BU_HTM_1 (TEND, "tend", MISC, tend) ++BU_HTM_0 (TENDALL, "tendall", MISC, tend) ++BU_HTM_0 (TRECHKPT, "trechkpt", MISC, trechkpt) ++BU_HTM_1 (TRECLAIM, "treclaim", MISC, treclaim) ++BU_HTM_0 (TRESUME, "tresume", MISC, tsr) ++BU_HTM_0 (TSUSPEND, "tsuspend", MISC, tsr) ++BU_HTM_1 (TSR, "tsr", MISC, tsr) ++BU_HTM_0 (TTEST, "ttest", MISC, ttest) ++ ++BU_HTM_SPR0 (GET_TFHAR, "get_tfhar", MISC, nothing) ++BU_HTM_SPR1 (SET_TFHAR, "set_tfhar", MISC, nothing) ++BU_HTM_SPR0 (GET_TFIAR, "get_tfiar", MISC, nothing) ++BU_HTM_SPR1 (SET_TFIAR, "set_tfiar", MISC, nothing) ++BU_HTM_SPR0 (GET_TEXASR, "get_texasr", MISC, nothing) ++BU_HTM_SPR1 (SET_TEXASR, "set_texasr", MISC, nothing) ++BU_HTM_SPR0 (GET_TEXASRU, "get_texasru", MISC, nothing) ++BU_HTM_SPR1 (SET_TEXASRU, "set_texasru", MISC, nothing) ++ ++ + /* 3 argument paired floating point builtins. */ + BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4) + BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4) +@@ -1430,10 +1747,10 @@ + RS6000_BTC_FP) + + BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase", +- RS6000_BTM_ALWAYS, RS6000_BTC_MISC) ++ RS6000_BTM_ALWAYS, RS6000_BTC_MISC) + + BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb", +- RS6000_BTM_ALWAYS, RS6000_BTC_MISC) ++ RS6000_BTM_ALWAYS, RS6000_BTC_MISC) + + /* Darwin CfString builtin. */ + BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, +--- a/src/gcc/config/rs6000/rs6000-c.c ++++ b/src/gcc/config/rs6000/rs6000-c.c +@@ -315,6 +315,8 @@ + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); + if ((flags & OPTION_MASK_POPCNTD) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); ++ if ((flags & OPTION_MASK_DIRECT_MOVE) != 0) ++ rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) + rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) +@@ -331,6 +333,12 @@ + } + if ((flags & OPTION_MASK_VSX) != 0) + rs6000_define_or_undefine_macro (define_p, "__VSX__"); ++ if ((flags & OPTION_MASK_HTM) != 0) ++ rs6000_define_or_undefine_macro (define_p, "__HTM__"); ++ if ((flags & OPTION_MASK_P8_VECTOR) != 0) ++ rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__"); ++ if ((flags & OPTION_MASK_CRYPTO) != 0) ++ rs6000_define_or_undefine_macro (define_p, "__CRYPTO__"); + + /* options from the builtin masks. */ + if ((bu_mask & RS6000_BTM_SPE) != 0) +@@ -453,7 +461,11 @@ + case ABI_AIX: + builtin_define ("_CALL_AIXDESC"); + builtin_define ("_CALL_AIX"); ++ builtin_define ("_CALL_ELF=1"); + break; ++ case ABI_ELFv2: ++ builtin_define ("_CALL_ELF=2"); ++ break; + case ABI_DARWIN: + builtin_define ("_CALL_DARWIN"); + break; +@@ -465,6 +477,13 @@ + if (TARGET_SOFT_FLOAT || !TARGET_FPRS) + builtin_define ("__NO_FPRS__"); + ++ /* Whether aggregates passed by value are aligned to a 16 byte boundary ++ if their alignment is 16 bytes or larger. */ ++ if ((TARGET_MACHO && rs6000_darwin64_abi) ++ || DEFAULT_ABI == ABI_ELFv2 ++ || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) ++ builtin_define ("__STRUCT_PARM_ALIGN__=16"); ++ + /* Generate defines for Xilinx FPU. */ + if (rs6000_xilinx_fpu) + { +@@ -505,6 +524,8 @@ + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, +@@ -577,12 +598,24 @@ + RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, + RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, +@@ -601,6 +634,10 @@ + RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, ++ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, ++ { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, +@@ -651,6 +688,18 @@ + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, +@@ -937,6 +986,10 @@ + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, + RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, +@@ -975,6 +1028,10 @@ + RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, +@@ -1021,6 +1078,10 @@ + RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, + RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, +@@ -1418,6 +1479,18 @@ + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, +@@ -1604,6 +1677,18 @@ + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, +@@ -1786,6 +1871,12 @@ + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, ++ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, ++ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, + RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, +@@ -1812,6 +1903,10 @@ + RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, ++ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, + RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, +@@ -1824,6 +1919,8 @@ + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, +@@ -1844,6 +1941,10 @@ + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, +@@ -1868,6 +1969,10 @@ + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, +@@ -2032,6 +2137,10 @@ + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, +@@ -2056,6 +2165,10 @@ + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, +@@ -2196,6 +2309,18 @@ + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, +@@ -3327,6 +3452,20 @@ + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, +@@ -3372,11 +3511,455 @@ + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, ++ { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, + ++ /* Power8 vector overloaded functions. */ ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_bool_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_bool_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_bool_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, ++ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, ++ { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, ++ ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_bool_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_bool_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_bool_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, ++ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, ++ { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, ++ ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_bool_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_bool_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_bool_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, ++ RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, ++ { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, ++ RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, ++ ++ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, ++ { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, ++ RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, ++ RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, ++ RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, ++ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, ++ RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, ++ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, ++ { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, ++ RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, ++ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, ++ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, ++ ++ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, ++ RS6000_BTI_V16QI, 0, 0, 0 }, ++ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, ++ RS6000_BTI_unsigned_V16QI, 0, 0, 0 }, ++ ++ /* Crypto builtins. */ ++ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, ++ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, ++ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, ++ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, ++ ++ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, ++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, ++ RS6000_BTI_unsigned_V16QI, 0 }, ++ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, ++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, ++ RS6000_BTI_unsigned_V8HI, 0 }, ++ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_unsigned_V4SI, 0 }, ++ { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_unsigned_V2DI, 0 }, ++ ++ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, ++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI }, ++ { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, ++ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, ++ RS6000_BTI_INTSI, RS6000_BTI_INTSI }, ++ + { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 } + }; + +@@ -3824,7 +4407,8 @@ + && (desc->op2 == RS6000_BTI_NOT_OPAQUE + || rs6000_builtin_type_compatible (types[1], desc->op2)) + && (desc->op3 == RS6000_BTI_NOT_OPAQUE +- || rs6000_builtin_type_compatible (types[2], desc->op3))) ++ || rs6000_builtin_type_compatible (types[2], desc->op3)) ++ && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) + return altivec_build_resolved_builtin (args, n, desc); + + bad: +--- a/src/gcc/config/rs6000/rs6000.opt ++++ b/src/gcc/config/rs6000/rs6000.opt +@@ -181,13 +181,16 @@ + Target Report Mask(VSX) Var(rs6000_isa_flags) + Use vector/scalar (VSX) instructions + ++mvsx-scalar-float ++Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1) ++; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default) ++ + mvsx-scalar-double +-Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) +-; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) ++Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1) ++; If -mvsx, use VSX arithmetic instructions for DFmode (on by default) + + mvsx-scalar-memory +-Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) +-; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) ++Target Undocumented Report Alias(mupper-regs-df) + + mvsx-align-128 + Target Undocumented Report Var(TARGET_VSX_ALIGN_128) +@@ -363,6 +366,14 @@ + Target RejectNegative Var(rs6000_spe_abi, 0) + Do not use the SPE ABI extensions + ++mabi=elfv1 ++Target RejectNegative Var(rs6000_elf_abi, 1) Save ++Use the ELFv1 ABI ++ ++mabi=elfv2 ++Target RejectNegative Var(rs6000_elf_abi, 2) ++Use the ELFv2 ABI ++ + ; These are here for testing during development only, do not document + ; in the manual please. + +@@ -514,3 +525,47 @@ + msave-toc-indirect + Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save + Control whether we save the TOC in the prologue for indirect calls or generate the save inline ++ ++mvsx-timode ++Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags) ++Allow 128-bit integers in VSX registers ++ ++mpower8-fusion ++Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) ++Fuse certain integer operations together for better performance on power8 ++ ++mpower8-fusion-sign ++Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) ++Allow sign extension in fusion operations ++ ++mpower8-vector ++Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) ++Use/do not use vector and scalar instructions added in ISA 2.07. ++ ++mcrypto ++Target Report Mask(CRYPTO) Var(rs6000_isa_flags) ++Use ISA 2.07 crypto instructions ++ ++mdirect-move ++Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) ++Use ISA 2.07 direct move between GPR & VSX register instructions ++ ++mhtm ++Target Report Mask(HTM) Var(rs6000_isa_flags) ++Use ISA 2.07 transactional memory (HTM) instructions ++ ++mquad-memory ++Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) ++Generate the quad word memory instructions (lq/stq/lqarx/stqcx). ++ ++mcompat-align-parm ++Target Report Var(rs6000_compat_align_parm) Init(1) Save ++Generate aggregate parameter passing code with at most 64-bit alignment. ++ ++mupper-regs-df ++Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) ++Allow double variables in upper registers with -mcpu=power7 or -mvsx ++ ++mupper-regs-sf ++Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) ++Allow float variables in upper registers with -mcpu=power8 or -mp8-vector +--- a/src/gcc/config/rs6000/linux64.h ++++ b/src/gcc/config/rs6000/linux64.h +@@ -25,9 +25,6 @@ + + #ifndef RS6000_BI_ARCH + +-#undef DEFAULT_ABI +-#define DEFAULT_ABI ABI_AIX +- + #undef TARGET_64BIT + #define TARGET_64BIT 1 + +@@ -74,7 +71,11 @@ + #undef PROCESSOR_DEFAULT + #define PROCESSOR_DEFAULT PROCESSOR_POWER7 + #undef PROCESSOR_DEFAULT64 ++#ifdef LINUX64_DEFAULT_ABI_ELFv2 ++#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8 ++#else + #define PROCESSOR_DEFAULT64 PROCESSOR_POWER7 ++#endif + + /* We don't need to generate entries in .fixup, except when + -mrelocatable or -mrelocatable-lib is given. */ +@@ -88,6 +89,12 @@ + #define INVALID_64BIT "-m%s not supported in this configuration" + #define INVALID_32BIT INVALID_64BIT + ++#ifdef LINUX64_DEFAULT_ABI_ELFv2 ++#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1) ++#else ++#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2) ++#endif ++ + #undef SUBSUBTARGET_OVERRIDE_OPTIONS + #define SUBSUBTARGET_OVERRIDE_OPTIONS \ + do \ +@@ -102,6 +109,12 @@ + error (INVALID_64BIT, "call"); \ + } \ + dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ ++ if (ELFv2_ABI_CHECK) \ ++ { \ ++ rs6000_current_abi = ABI_ELFv2; \ ++ if (dot_symbols) \ ++ error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \ ++ } \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ + { \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ +@@ -351,7 +364,11 @@ + #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" + + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" +-#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1" ++#ifdef LINUX64_DEFAULT_ABI_ELFv2 ++#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}" ++#else ++#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}" ++#endif + #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" + #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" + #if DEFAULT_LIBC == LIBC_UCLIBC +--- a/src/gcc/config/rs6000/darwin.h ++++ b/src/gcc/config/rs6000/darwin.h +@@ -205,7 +205,8 @@ + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ + "vrsave", "vscr", \ + "spe_acc", "spefscr", \ +- "sfp" \ ++ "sfp", \ ++ "tfhar", "tfiar", "texasr" \ + } + + /* This outputs NAME to FILE. */ +--- a/src/gcc/config/rs6000/rs6000.c ++++ b/src/gcc/config/rs6000/rs6000.c +@@ -96,6 +96,7 @@ + int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ + int varargs_save_offset; /* offset to save the varargs registers */ + int ehrd_offset; /* offset to EH return data */ ++ int ehcr_offset; /* offset to EH CR field data */ + int reg_size; /* register size (4 or 8) */ + HOST_WIDE_INT vars_size; /* variable save area size */ + int parm_size; /* outgoing parameter size */ +@@ -139,6 +140,8 @@ + 64-bits wide and is allocated early enough so that the offset + does not overflow the 16-bit load/store offset field. */ + rtx sdmode_stack_slot; ++ /* Flag if r2 setup is needed with ELFv2 ABI. */ ++ bool r2_setup_needed; + } machine_function; + + /* Support targetm.vectorize.builtin_mask_for_load. */ +@@ -189,9 +192,6 @@ + /* Map register number to register class. */ + enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; + +-/* Reload functions based on the type and the vector unit. */ +-static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2]; +- + static int dbg_cost_ctrl; + + /* Built in types. */ +@@ -289,6 +289,105 @@ + don't link in rs6000-c.c, so we can't call it directly. */ + void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); + ++/* Simplfy register classes into simpler classifications. We assume ++ GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range ++ check for standard register classes (gpr/floating/altivec/vsx) and ++ floating/vector classes (float/altivec/vsx). */ ++ ++enum rs6000_reg_type { ++ NO_REG_TYPE, ++ PSEUDO_REG_TYPE, ++ GPR_REG_TYPE, ++ VSX_REG_TYPE, ++ ALTIVEC_REG_TYPE, ++ FPR_REG_TYPE, ++ SPR_REG_TYPE, ++ CR_REG_TYPE, ++ SPE_ACC_TYPE, ++ SPEFSCR_REG_TYPE ++}; ++ ++/* Map register class to register type. */ ++static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES]; ++ ++/* First/last register type for the 'normal' register types (i.e. general ++ purpose, floating point, altivec, and VSX registers). */ ++#define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE) ++ ++#define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE) ++ ++ ++/* Register classes we care about in secondary reload or go if legitimate ++ address. We only need to worry about GPR, FPR, and Altivec registers here, ++ along an ANY field that is the OR of the 3 register classes. */ ++ ++enum rs6000_reload_reg_type { ++ RELOAD_REG_GPR, /* General purpose registers. */ ++ RELOAD_REG_FPR, /* Traditional floating point regs. */ ++ RELOAD_REG_VMX, /* Altivec (VMX) registers. */ ++ RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */ ++ N_RELOAD_REG ++}; ++ ++/* For setting up register classes, loop through the 3 register classes mapping ++ into real registers, and skip the ANY class, which is just an OR of the ++ bits. */ ++#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR ++#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX ++ ++/* Map reload register type to a register in the register class. */ ++struct reload_reg_map_type { ++ const char *name; /* Register class name. */ ++ int reg; /* Register in the register class. */ ++}; ++ ++static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = { ++ { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */ ++ { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */ ++ { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */ ++ { "Any", -1 }, /* RELOAD_REG_ANY. */ ++}; ++ ++/* Mask bits for each register class, indexed per mode. Historically the ++ compiler has been more restrictive which types can do PRE_MODIFY instead of ++ PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */ ++typedef unsigned char addr_mask_type; ++ ++#define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */ ++#define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */ ++#define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */ ++#define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */ ++#define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ ++#define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ ++ ++/* Register type masks based on the type, of valid addressing modes. */ ++struct rs6000_reg_addr { ++ enum insn_code reload_load; /* INSN to reload for loading. */ ++ enum insn_code reload_store; /* INSN to reload for storing. */ ++ enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */ ++ enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */ ++ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */ ++ addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */ ++}; ++ ++static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES]; ++ ++/* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */ ++static inline bool ++mode_supports_pre_incdec_p (enum machine_mode mode) ++{ ++ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC) ++ != 0); ++} ++ ++/* Helper function to say whether a mode supports PRE_MODIFY. */ ++static inline bool ++mode_supports_pre_modify_p (enum machine_mode mode) ++{ ++ return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY) ++ != 0); ++} ++ + + /* Target cpu costs. */ + +@@ -828,6 +927,25 @@ + 12, /* prefetch streams */ + }; + ++/* Instruction costs on POWER8 processors. */ ++static const ++struct processor_costs power8_cost = { ++ COSTS_N_INSNS (3), /* mulsi */ ++ COSTS_N_INSNS (3), /* mulsi_const */ ++ COSTS_N_INSNS (3), /* mulsi_const9 */ ++ COSTS_N_INSNS (3), /* muldi */ ++ COSTS_N_INSNS (19), /* divsi */ ++ COSTS_N_INSNS (35), /* divdi */ ++ COSTS_N_INSNS (3), /* fp */ ++ COSTS_N_INSNS (3), /* dmul */ ++ COSTS_N_INSNS (14), /* sdiv */ ++ COSTS_N_INSNS (17), /* ddiv */ ++ 128, /* cache line size */ ++ 32, /* l1 cache */ ++ 256, /* l2 cache */ ++ 12, /* prefetch streams */ ++}; ++ + /* Instruction costs on POWER A2 processors. */ + static const + struct processor_costs ppca2_cost = { +@@ -855,6 +973,7 @@ + #undef RS6000_BUILTIN_A + #undef RS6000_BUILTIN_D + #undef RS6000_BUILTIN_E ++#undef RS6000_BUILTIN_H + #undef RS6000_BUILTIN_P + #undef RS6000_BUILTIN_Q + #undef RS6000_BUILTIN_S +@@ -878,6 +997,9 @@ + #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ + { NAME, ICODE, MASK, ATTR }, + ++#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ ++ { NAME, ICODE, MASK, ATTR }, ++ + #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ + { NAME, ICODE, MASK, ATTR }, + +@@ -908,6 +1030,7 @@ + #undef RS6000_BUILTIN_A + #undef RS6000_BUILTIN_D + #undef RS6000_BUILTIN_E ++#undef RS6000_BUILTIN_H + #undef RS6000_BUILTIN_P + #undef RS6000_BUILTIN_Q + #undef RS6000_BUILTIN_S +@@ -948,6 +1071,7 @@ + static void paired_init_builtins (void); + static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx); + static void spe_init_builtins (void); ++static void htm_init_builtins (void); + static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); + static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); + static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); +@@ -1020,6 +1144,13 @@ + static void rs6000_print_builtin_options (FILE *, int, const char *, + HOST_WIDE_INT); + ++static enum rs6000_reg_type register_to_reg_type (rtx, bool *); ++static bool rs6000_secondary_reload_move (enum rs6000_reg_type, ++ enum rs6000_reg_type, ++ enum machine_mode, ++ secondary_reload_info *, ++ bool); ++ + /* Hash table stuff for keeping track of TOC entries. */ + + struct GTY(()) toc_hash_struct +@@ -1068,7 +1199,9 @@ + /* SPE registers. */ + "spe_acc", "spefscr", + /* Soft frame pointer. */ +- "sfp" ++ "sfp", ++ /* HTM SPR registers. */ ++ "tfhar", "tfiar", "texasr" + }; + + #ifdef TARGET_REGNAMES +@@ -1094,7 +1227,9 @@ + /* SPE registers. */ + "spe_acc", "spefscr", + /* Soft frame pointer. */ +- "sfp" ++ "sfp", ++ /* HTM SPR registers. */ ++ "tfhar", "tfiar", "texasr" + }; + #endif + +@@ -1316,6 +1451,9 @@ + #undef TARGET_RETURN_IN_MEMORY + #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory + ++#undef TARGET_RETURN_IN_MSB ++#define TARGET_RETURN_IN_MSB rs6000_return_in_msb ++ + #undef TARGET_SETUP_INCOMING_VARARGS + #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs + +@@ -1513,8 +1651,9 @@ + { + unsigned HOST_WIDE_INT reg_size; + ++ /* TF/TD modes are special in that they always take 2 registers. */ + if (FP_REGNO_P (regno)) +- reg_size = (VECTOR_MEM_VSX_P (mode) ++ reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode) + ? UNITS_PER_VSX_WORD + : UNITS_PER_FP_WORD); + +@@ -1546,16 +1685,38 @@ + { + int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1; + ++ /* PTImode can only go in GPRs. Quad word memory operations require even/odd ++ register combinations, and use PTImode where we need to deal with quad ++ word memory operations. Don't allow quad words in the argument or frame ++ pointer registers, just registers 0..31. */ ++ if (mode == PTImode) ++ return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO) ++ && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO) ++ && ((regno & 1) == 0)); ++ + /* VSX registers that overlap the FPR registers are larger than for non-VSX + implementations. Don't allow an item to be split between a FP register +- and an Altivec register. */ +- if (VECTOR_MEM_VSX_P (mode)) ++ and an Altivec register. Allow TImode in all VSX registers if the user ++ asked for it. */ ++ if (TARGET_VSX && VSX_REGNO_P (regno) ++ && (VECTOR_MEM_VSX_P (mode) ++ || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode) ++ || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode)) ++ || (TARGET_VSX_TIMODE && mode == TImode))) + { + if (FP_REGNO_P (regno)) + return FP_REGNO_P (last_regno); + + if (ALTIVEC_REGNO_P (regno)) +- return ALTIVEC_REGNO_P (last_regno); ++ { ++ if (mode == SFmode && !TARGET_UPPER_REGS_SF) ++ return 0; ++ ++ if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF) ++ return 0; ++ ++ return ALTIVEC_REGNO_P (last_regno); ++ } + } + + /* The GPRs can hold any mode, but values bigger than one register +@@ -1564,8 +1725,7 @@ + return INT_REGNO_P (last_regno); + + /* The float registers (except for VSX vector modes) can only hold floating +- modes and DImode. This excludes the 32-bit decimal float mode for +- now. */ ++ modes and DImode. */ + if (FP_REGNO_P (regno)) + { + if (SCALAR_FLOAT_MODE_P (mode) +@@ -1599,9 +1759,8 @@ + if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) + return 1; + +- /* We cannot put TImode anywhere except general register and it must be able +- to fit within the register set. In the future, allow TImode in the +- Altivec or VSX registers. */ ++ /* We cannot put non-VSX TImode or PTImode anywhere except general register ++ and it must be able to fit within the register set. */ + + return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; + } +@@ -1674,10 +1833,77 @@ + comma = ""; + } + ++ len += fprintf (stderr, "%sreg-class = %s", comma, ++ reg_class_names[(int)rs6000_regno_regclass[r]]); ++ comma = ", "; ++ ++ if (len > 70) ++ { ++ fprintf (stderr, ",\n\t"); ++ comma = ""; ++ } ++ + fprintf (stderr, "%sregno = %d\n", comma, r); + } + } + ++static const char * ++rs6000_debug_vector_unit (enum rs6000_vector v) ++{ ++ const char *ret; ++ ++ switch (v) ++ { ++ case VECTOR_NONE: ret = "none"; break; ++ case VECTOR_ALTIVEC: ret = "altivec"; break; ++ case VECTOR_VSX: ret = "vsx"; break; ++ case VECTOR_P8_VECTOR: ret = "p8_vector"; break; ++ case VECTOR_PAIRED: ret = "paired"; break; ++ case VECTOR_SPE: ret = "spe"; break; ++ case VECTOR_OTHER: ret = "other"; break; ++ default: ret = "unknown"; break; ++ } ++ ++ return ret; ++} ++ ++/* Print the address masks in a human readble fashion. */ ++DEBUG_FUNCTION void ++rs6000_debug_print_mode (ssize_t m) ++{ ++ ssize_t rc; ++ ++ fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m)); ++ for (rc = 0; rc < N_RELOAD_REG; rc++) ++ { ++ addr_mask_type mask = reg_addr[m].addr_mask[rc]; ++ fprintf (stderr, ++ " %s: %c%c%c%c%c%c", ++ reload_reg_map[rc].name, ++ (mask & RELOAD_REG_VALID) != 0 ? 'v' : ' ', ++ (mask & RELOAD_REG_MULTIPLE) != 0 ? 'm' : ' ', ++ (mask & RELOAD_REG_INDEXED) != 0 ? 'i' : ' ', ++ (mask & RELOAD_REG_OFFSET) != 0 ? 'o' : ' ', ++ (mask & RELOAD_REG_PRE_INCDEC) != 0 ? '+' : ' ', ++ (mask & RELOAD_REG_PRE_MODIFY) != 0 ? '+' : ' '); ++ } ++ ++ if (rs6000_vector_unit[m] != VECTOR_NONE ++ || rs6000_vector_mem[m] != VECTOR_NONE ++ || (reg_addr[m].reload_store != CODE_FOR_nothing) ++ || (reg_addr[m].reload_load != CODE_FOR_nothing)) ++ { ++ fprintf (stderr, ++ " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c", ++ rs6000_debug_vector_unit (rs6000_vector_unit[m]), ++ rs6000_debug_vector_unit (rs6000_vector_mem[m]), ++ (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', ++ (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*'); ++ } ++ ++ fputs ("\n", stderr); ++} ++ + #define DEBUG_FMT_ID "%-32s= " + #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" + #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: " +@@ -1690,6 +1916,7 @@ + static const char *const tf[2] = { "false", "true" }; + const char *nl = (const char *)0; + int m; ++ size_t m1, m2, v; + char costly_num[20]; + char nop_num[20]; + char flags_buffer[40]; +@@ -1700,20 +1927,67 @@ + const char *cmodel_str; + struct cl_target_option cl_opts; + +- /* Map enum rs6000_vector to string. */ +- static const char *rs6000_debug_vector_unit[] = { +- "none", +- "altivec", +- "vsx", +- "paired", +- "spe", +- "other" ++ /* Modes we want tieable information on. */ ++ static const enum machine_mode print_tieable_modes[] = { ++ QImode, ++ HImode, ++ SImode, ++ DImode, ++ TImode, ++ PTImode, ++ SFmode, ++ DFmode, ++ TFmode, ++ SDmode, ++ DDmode, ++ TDmode, ++ V8QImode, ++ V4HImode, ++ V2SImode, ++ V16QImode, ++ V8HImode, ++ V4SImode, ++ V2DImode, ++ V32QImode, ++ V16HImode, ++ V8SImode, ++ V4DImode, ++ V2SFmode, ++ V4SFmode, ++ V2DFmode, ++ V8SFmode, ++ V4DFmode, ++ CCmode, ++ CCUNSmode, ++ CCEQmode, + }; + +- fprintf (stderr, "Register information: (last virtual reg = %d)\n", +- LAST_VIRTUAL_REGISTER); +- rs6000_debug_reg_print (0, 31, "gr"); +- rs6000_debug_reg_print (32, 63, "fp"); ++ /* Virtual regs we are interested in. */ ++ const static struct { ++ int regno; /* register number. */ ++ const char *name; /* register name. */ ++ } virtual_regs[] = { ++ { STACK_POINTER_REGNUM, "stack pointer:" }, ++ { TOC_REGNUM, "toc: " }, ++ { STATIC_CHAIN_REGNUM, "static chain: " }, ++ { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " }, ++ { HARD_FRAME_POINTER_REGNUM, "hard frame: " }, ++ { ARG_POINTER_REGNUM, "arg pointer: " }, ++ { FRAME_POINTER_REGNUM, "frame pointer:" }, ++ { FIRST_PSEUDO_REGISTER, "first pseudo: " }, ++ { FIRST_VIRTUAL_REGISTER, "first virtual:" }, ++ { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" }, ++ { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " }, ++ { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" }, ++ { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" }, ++ { VIRTUAL_CFA_REGNUM, "cfa (frame): " }, ++ { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" }, ++ { LAST_VIRTUAL_REGISTER, "last virtual: " }, ++ }; ++ ++ fputs ("\nHard register information:\n", stderr); ++ rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr"); ++ rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp"); + rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO, + LAST_ALTIVEC_REGNO, + "vs"); +@@ -1726,6 +2000,10 @@ + rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a"); + rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f"); + ++ fputs ("\nVirtual/stack/frame registers:\n", stderr); ++ for (v = 0; v < ARRAY_SIZE (virtual_regs); v++) ++ fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno); ++ + fprintf (stderr, + "\n" + "d reg_class = %s\n" +@@ -1734,25 +2012,70 @@ + "wa reg_class = %s\n" + "wd reg_class = %s\n" + "wf reg_class = %s\n" +- "ws reg_class = %s\n\n", ++ "wg reg_class = %s\n" ++ "wl reg_class = %s\n" ++ "wm reg_class = %s\n" ++ "wr reg_class = %s\n" ++ "ws reg_class = %s\n" ++ "wt reg_class = %s\n" ++ "wu reg_class = %s\n" ++ "wv reg_class = %s\n" ++ "ww reg_class = %s\n" ++ "wx reg_class = %s\n" ++ "wy reg_class = %s\n" ++ "wz reg_class = %s\n" ++ "\n", + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], +- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]); ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]], ++ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]); + ++ nl = "\n"; + for (m = 0; m < NUM_MACHINE_MODES; ++m) +- if (rs6000_vector_unit[m] || rs6000_vector_mem[m]) +- { +- nl = "\n"; +- fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n", +- GET_MODE_NAME (m), +- rs6000_debug_vector_unit[ rs6000_vector_unit[m] ], +- rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]); +- } ++ rs6000_debug_print_mode (m); + ++ fputs ("\n", stderr); ++ ++ for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++) ++ { ++ enum machine_mode mode1 = print_tieable_modes[m1]; ++ bool first_time = true; ++ ++ nl = (const char *)0; ++ for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++) ++ { ++ enum machine_mode mode2 = print_tieable_modes[m2]; ++ if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2)) ++ { ++ if (first_time) ++ { ++ fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1)); ++ nl = "\n"; ++ first_time = false; ++ } ++ ++ fprintf (stderr, " %s", GET_MODE_NAME (mode2)); ++ } ++ } ++ ++ if (!first_time) ++ fputs ("\n", stderr); ++ } ++ + if (nl) + fputs (nl, stderr); + +@@ -1913,6 +2236,7 @@ + { + case ABI_NONE: abi_str = "none"; break; + case ABI_AIX: abi_str = "aix"; break; ++ case ABI_ELFv2: abi_str = "ELFv2"; break; + case ABI_V4: abi_str = "V4"; break; + case ABI_DARWIN: abi_str = "darwin"; break; + default: abi_str = "unknown"; break; +@@ -1935,6 +2259,13 @@ + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + ++ if (targetm.lra_p ()) ++ fprintf (stderr, DEBUG_FMT_S, "lra", "true"); ++ ++ if (TARGET_P8_FUSION) ++ fprintf (stderr, DEBUG_FMT_S, "p8 fusion", ++ (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero"); ++ + fprintf (stderr, DEBUG_FMT_S, "plt-format", + TARGET_SECURE_PLT ? "secure" : "bss"); + fprintf (stderr, DEBUG_FMT_S, "struct-return", +@@ -1954,11 +2285,106 @@ + (int)RS6000_BUILTIN_COUNT); + } + ++ ++/* Update the addr mask bits in reg_addr to help secondary reload and go if ++ legitimate address support to figure out the appropriate addressing to ++ use. */ ++ ++static void ++rs6000_setup_reg_addr_masks (void) ++{ ++ ssize_t rc, reg, m, nregs; ++ addr_mask_type any_addr_mask, addr_mask; ++ ++ for (m = 0; m < NUM_MACHINE_MODES; ++m) ++ { ++ /* SDmode is special in that we want to access it only via REG+REG ++ addressing on power7 and above, since we want to use the LFIWZX and ++ STFIWZX instructions to load it. */ ++ bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK); ++ ++ any_addr_mask = 0; ++ for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++) ++ { ++ addr_mask = 0; ++ reg = reload_reg_map[rc].reg; ++ ++ /* Can mode values go in the GPR/FPR/Altivec registers? */ ++ if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg]) ++ { ++ nregs = rs6000_hard_regno_nregs[m][reg]; ++ addr_mask |= RELOAD_REG_VALID; ++ ++ /* Indicate if the mode takes more than 1 physical register. If ++ it takes a single register, indicate it can do REG+REG ++ addressing. */ ++ if (nregs > 1 || m == BLKmode) ++ addr_mask |= RELOAD_REG_MULTIPLE; ++ else ++ addr_mask |= RELOAD_REG_INDEXED; ++ ++ /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY ++ addressing. Restrict addressing on SPE for 64-bit types ++ because of the SUBREG hackery used to address 64-bit floats in ++ '32-bit' GPRs. To simplify secondary reload, don't allow ++ update forms on scalar floating point types that can go in the ++ upper registers. */ ++ ++ if (TARGET_UPDATE ++ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) ++ && GET_MODE_SIZE (m) <= 8 ++ && !VECTOR_MODE_P (m) ++ && !COMPLEX_MODE_P (m) ++ && !indexed_only_p ++ && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8) ++ && !(m == DFmode && TARGET_UPPER_REGS_DF) ++ && !(m == SFmode && TARGET_UPPER_REGS_SF)) ++ { ++ addr_mask |= RELOAD_REG_PRE_INCDEC; ++ ++ /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that ++ we don't allow PRE_MODIFY for some multi-register ++ operations. */ ++ switch (m) ++ { ++ default: ++ addr_mask |= RELOAD_REG_PRE_MODIFY; ++ break; ++ ++ case DImode: ++ if (TARGET_POWERPC64) ++ addr_mask |= RELOAD_REG_PRE_MODIFY; ++ break; ++ ++ case DFmode: ++ case DDmode: ++ if (TARGET_DF_INSN) ++ addr_mask |= RELOAD_REG_PRE_MODIFY; ++ break; ++ } ++ } ++ } ++ ++ /* GPR and FPR registers can do REG+OFFSET addressing, except ++ possibly for SDmode. */ ++ if ((addr_mask != 0) && !indexed_only_p ++ && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)) ++ addr_mask |= RELOAD_REG_OFFSET; ++ ++ reg_addr[m].addr_mask[rc] = addr_mask; ++ any_addr_mask |= addr_mask; ++ } ++ ++ reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask; ++ } ++} ++ ++ + /* Initialize the various global tables that are based on register size. */ + static void + rs6000_init_hard_regno_mode_ok (bool global_init_p) + { +- int r, m, c; ++ ssize_t r, m, c; + int align64; + int align32; + +@@ -1987,21 +2413,55 @@ + rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS; + rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS; + rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS; ++ rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS; ++ rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS; ++ rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS; + rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS; + rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS; + +- /* Precalculate vector information, this must be set up before the +- rs6000_hard_regno_nregs_internal below. */ +- for (m = 0; m < NUM_MACHINE_MODES; ++m) ++ /* Precalculate register class to simpler reload register class. We don't ++ need all of the register classes that are combinations of different ++ classes, just the simple ones that have constraint letters. */ ++ for (c = 0; c < N_REG_CLASSES; c++) ++ reg_class_to_reg_type[c] = NO_REG_TYPE; ++ ++ reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE; ++ reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE; ++ reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE; ++ reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE; ++ reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE; ++ reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE; ++ reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE; ++ reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE; ++ reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE; ++ reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE; ++ reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE; ++ reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE; ++ ++ if (TARGET_VSX) + { +- rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE; +- rs6000_vector_reload[m][0] = CODE_FOR_nothing; +- rs6000_vector_reload[m][1] = CODE_FOR_nothing; ++ reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE; ++ reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE; + } ++ else ++ { ++ reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE; ++ reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE; ++ } + +- for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++) +- rs6000_constraints[c] = NO_REGS; ++ /* Precalculate the valid memory formats as well as the vector information, ++ this must be set up before the rs6000_hard_regno_nregs_internal calls ++ below. */ ++ gcc_assert ((int)VECTOR_NONE == 0); ++ memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit)); ++ memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit)); + ++ gcc_assert ((int)CODE_FOR_nothing == 0); ++ memset ((void *) ®_addr[0], '\0', sizeof (reg_addr)); ++ ++ gcc_assert ((int)NO_REGS == 0); ++ memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints)); ++ + /* The VSX hardware allows native alignment for vectors, but control whether the compiler + believes it can use native alignment or still uses 128-bit alignment. */ + if (TARGET_VSX && !TARGET_VSX_ALIGN_128) +@@ -2062,12 +2522,13 @@ + } + } + +- /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract. +- Altivec doesn't have 64-bit support. */ ++ /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to ++ do insert/splat/extract. Altivec doesn't have 64-bit integer support. */ + if (TARGET_VSX) + { + rs6000_vector_mem[V2DImode] = VECTOR_VSX; +- rs6000_vector_unit[V2DImode] = VECTOR_NONE; ++ rs6000_vector_unit[V2DImode] ++ = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE; + rs6000_vector_align[V2DImode] = align64; + } + +@@ -2076,14 +2537,48 @@ + { + rs6000_vector_unit[DFmode] = VECTOR_VSX; + rs6000_vector_mem[DFmode] +- = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE); ++ = (TARGET_UPPER_REGS_DF ? VECTOR_VSX : VECTOR_NONE); + rs6000_vector_align[DFmode] = align64; + } + ++ /* Allow TImode in VSX register and set the VSX memory macros. */ ++ if (TARGET_VSX && TARGET_VSX_TIMODE) ++ { ++ rs6000_vector_mem[TImode] = VECTOR_VSX; ++ rs6000_vector_align[TImode] = align64; ++ } ++ + /* TODO add SPE and paired floating point vector support. */ + + /* Register class constraints for the constraints that depend on compile +- switches. */ ++ switches. When the VSX code was added, different constraints were added ++ based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all ++ of the VSX registers are used. The register classes for scalar floating ++ point types is set, based on whether we allow that type into the upper ++ (Altivec) registers. GCC has register classes to target the Altivec ++ registers for load/store operations, to select using a VSX memory ++ operation instead of the traditional floating point operation. The ++ constraints are: ++ ++ d - Register class to use with traditional DFmode instructions. ++ f - Register class to use with traditional SFmode instructions. ++ v - Altivec register. ++ wa - Any VSX register. ++ wd - Preferred register class for V2DFmode. ++ wf - Preferred register class for V4SFmode. ++ wg - Float register for power6x move insns. ++ wl - Float register if we can do 32-bit signed int loads. ++ wm - VSX register for ISA 2.07 direct move operations. ++ wr - GPR if 64-bit mode is permitted. ++ ws - Register class to do ISA 2.06 DF operations. ++ wu - Altivec register for ISA 2.07 VSX SF/SI load/stores. ++ wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. ++ wt - VSX register for TImode in VSX registers. ++ ww - Register class to do SF conversions in with VSX operations. ++ wx - Float register if we can do 32-bit int stores. ++ wy - Register class to do ISA 2.07 SF operations. ++ wz - Float register if we can do 32-bit unsigned int loads. */ ++ + if (TARGET_HARD_FLOAT && TARGET_FPRS) + rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; + +@@ -2092,64 +2587,158 @@ + + if (TARGET_VSX) + { +- /* At present, we just use VSX_REGS, but we have different constraints +- based on the use, in case we want to fine tune the default register +- class used. wa = any VSX register, wf = register class to use for +- V4SF, wd = register class to use for V2DF, and ws = register classs to +- use for DF scalars. */ + rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; ++ rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; +- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; +- rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY +- ? VSX_REGS +- : FLOAT_REGS); ++ ++ if (TARGET_VSX_TIMODE) ++ rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; ++ ++ if (TARGET_UPPER_REGS_DF) ++ { ++ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; ++ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; ++ } ++ else ++ rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS; + } + ++ /* Add conditional constraints based on various options, to allow us to ++ collapse multiple insn patterns. */ + if (TARGET_ALTIVEC) + rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; + +- /* Set up the reload helper functions. */ ++ if (TARGET_MFPGPR) ++ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; ++ ++ if (TARGET_LFIWAX) ++ rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; ++ ++ if (TARGET_DIRECT_MOVE) ++ rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; ++ ++ if (TARGET_POWERPC64) ++ rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; ++ ++ if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) ++ { ++ rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS; ++ rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS; ++ rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS; ++ } ++ else if (TARGET_P8_VECTOR) ++ { ++ rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS; ++ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; ++ } ++ else if (TARGET_VSX) ++ rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; ++ ++ if (TARGET_STFIWX) ++ rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; ++ ++ if (TARGET_LFIWZX) ++ rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; ++ ++ /* Set up the reload helper and direct move functions. */ + if (TARGET_VSX || TARGET_ALTIVEC) + { + if (TARGET_64BIT) + { +- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store; +- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load; +- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store; +- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load; +- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store; +- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load; +- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store; +- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load; +- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store; +- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load; +- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store; +- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load; +- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) ++ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store; ++ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load; ++ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store; ++ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load; ++ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store; ++ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load; ++ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store; ++ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load; ++ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store; ++ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load; ++ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store; ++ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; ++ if (TARGET_VSX && TARGET_UPPER_REGS_DF) + { +- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store; +- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load; ++ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; ++ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; ++ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; ++ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; + } ++ if (TARGET_P8_VECTOR) ++ { ++ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store; ++ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; ++ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store; ++ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load; ++ } ++ if (TARGET_VSX_TIMODE) ++ { ++ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store; ++ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load; ++ } ++ if (TARGET_DIRECT_MOVE) ++ { ++ if (TARGET_POWERPC64) ++ { ++ reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti; ++ reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df; ++ reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di; ++ reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf; ++ reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si; ++ reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi; ++ reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi; ++ reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf; ++ ++ reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti; ++ reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df; ++ reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di; ++ reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf; ++ reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si; ++ reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi; ++ reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi; ++ reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf; ++ } ++ else ++ { ++ reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi; ++ reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd; ++ reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf; ++ } ++ } + } + else + { +- rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store; +- rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load; +- rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store; +- rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load; +- rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store; +- rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load; +- rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store; +- rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load; +- rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store; +- rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load; +- rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store; +- rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load; +- if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY) ++ reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store; ++ reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load; ++ reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store; ++ reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load; ++ reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store; ++ reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load; ++ reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store; ++ reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load; ++ reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store; ++ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load; ++ reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; ++ reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; ++ if (TARGET_VSX && TARGET_UPPER_REGS_DF) + { +- rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store; +- rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load; ++ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; ++ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; ++ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; ++ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; + } ++ if (TARGET_P8_VECTOR) ++ { ++ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store; ++ reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; ++ reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store; ++ reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load; ++ } ++ if (TARGET_VSX_TIMODE) ++ { ++ reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store; ++ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load; ++ } + } + } + +@@ -2267,6 +2856,11 @@ + } + } + ++ /* Update the addr mask bits in reg_addr to help secondary reload and go if ++ legitimate address support to figure out the appropriate addressing to ++ use. */ ++ rs6000_setup_reg_addr_masks (); ++ + if (global_init_p || TARGET_DEBUG_TARGET) + { + if (TARGET_DEBUG_REG) +@@ -2369,16 +2963,19 @@ + HOST_WIDE_INT + rs6000_builtin_mask_calculate (void) + { +- return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) +- | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) +- | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) +- | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) +- | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) +- | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) +- | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) +- | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) +- | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) +- | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); ++ return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) ++ | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) ++ | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) ++ | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) ++ | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) ++ | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) ++ | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) ++ | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) ++ | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) ++ | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) ++ | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) ++ | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) ++ | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)); + } + + /* Override command line options. Mostly we process the processor type and +@@ -2609,6 +3206,12 @@ + } + } + ++ /* If little-endian, default to -mstrict-align on older processors. ++ Testing for htm matches power8 and later. */ ++ if (!BYTES_BIG_ENDIAN ++ && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) ++ rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; ++ + /* Add some warnings for VSX. */ + if (TARGET_VSX) + { +@@ -2619,15 +3222,13 @@ + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) + msg = N_("-mvsx requires hardware floating point"); + else +- rs6000_isa_flags &= ~ OPTION_MASK_VSX; ++ { ++ rs6000_isa_flags &= ~ OPTION_MASK_VSX; ++ rs6000_isa_flags_explicit |= OPTION_MASK_VSX; ++ } + } + else if (TARGET_PAIRED_FLOAT) + msg = N_("-mvsx and -mpaired are incompatible"); +- /* The hardware will allow VSX and little endian, but until we make sure +- things like vector select, etc. work don't allow VSX on little endian +- systems at this point. */ +- else if (!BYTES_BIG_ENDIAN) +- msg = N_("-mvsx used with little endian code"); + else if (TARGET_AVOID_XFORM > 0) + msg = N_("-mvsx needs indexed addressing"); + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit +@@ -2647,9 +3248,24 @@ + } + } + ++ /* If hard-float/altivec/vsx were explicitly turned off then don't allow ++ the -mcpu setting to enable options that conflict. */ ++ if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX) ++ && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT ++ | OPTION_MASK_ALTIVEC ++ | OPTION_MASK_VSX)) != 0) ++ rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO ++ | OPTION_MASK_DIRECT_MOVE) ++ & ~rs6000_isa_flags_explicit); ++ ++ if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) ++ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags); ++ + /* For the newer switches (vsx, dfp, etc.) set some of the older options, + unless the user explicitly used the -mno-