Unmapped gates are incorrectly exported in Verilog

[Danil Sokolov]

The Verilog export of complex-gate circuits is wrong:
 ...
     g9 (.o(gn), .i1i1(zc), .i2i1(uv), .i3i1(gp_ack));
     g11 (.o(gp), .i1i1(uv), .i1i2i1(gn_ack), .i2i1i1(oc), .i2i2(gp));
 ...

I.e. it assumes that the two gates are from some library rather than arbitrary names, and the functions are not given.
It would be better to use assign statements like MPSAT.

Similarly for gC and stdC.