yosys-doc 0.7-2 (powerpc binary) in ubuntu zesty
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.
Details
- Package version:
- 0.7-2
- Status:
- Deleted
- Component:
- universe
- Priority:
- Optional
Downloadable files
amd64 build of yosys 0.7-2 in ubuntu zesty PROPOSED produced
these files:
- yosys-doc_0.7-2_all.deb (2.0 MiB)
Package relationships
- Suggests: