yosys binary package in Ubuntu Xenial s390x

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.

Publishing history

Date Status Target Pocket Component Section Priority Phased updates Version
  2016-02-08 01:39:26 UTC Published Ubuntu Xenial s390x release universe electronics Optional 0.5.0+20151013gitf13e387-1
  • Published
  • Copied from ubuntu xenial-proposed s390x in Primary Archive for Ubuntu
  Deleted Ubuntu Xenial s390x proposed universe electronics Optional 0.5.0+20151013gitf13e387-1
  • Removal requested .
  • Deleted by Ubuntu Archive Robot

    moved to release

  • Published
  2016-02-08 01:39:50 UTC Superseded Ubuntu Xenial s390x release universe electronics Optional 0.5.0-1
  • Removed from disk .
  • Removal requested .
  • Superseded by s390x build of yosys 0.5.0+20151013gitf13e387-1 in ubuntu xenial PROPOSED
  • Published

Source package