From 1125e3a45a733cecef2e6a88839977ae155a32d2 Mon Sep 17 00:00:00 2001 From: Suman Tripathi Date: Tue, 19 Aug 2014 12:01:49 +0530 Subject: [PATCH 1/3] UBUNTU: SAUCE: (no-up) arm64: Fix the csr-mask for APM X-Gene SoC AHCI SATA PHY clock DTS node. BugLink: http://bugs.launchpad.net/bugs/1359489 The value of the csr-mask of the SATA PHY clock DTS node has a wrong value resulting a kernel panic as the clock/reset is not proper for the PHY of the SATA host controller 1. This patch fixes the correct csr-mask value of the SATA PHY clock DTS node for the SATA Host controller 1. As the 'ok' is the default status of a device tree node, this patch removes the status of the PHY clock node of SATA Host Controller 1. The status of the clock node is handled from the firmware based on the controller enabled/disabled by the user. Signed-off-by: Loc Ho Signed-off-by: Suman Tripathi Signed-off-by: dann frazier Reference: http://www.spinics.net/lists/linux-scsi/msg77268.html Signed-off-by: Craig Magina (v7 submittal) --- arch/arm64/boot/dts/apm-storm.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index adf3101..392f216 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -194,9 +194,8 @@ reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy1clk"; - status = "disabled"; csr-offset = <0x4>; - csr-mask = <0x00>; + csr-mask = <0x3a>; enable-offset = <0x0>; enable-mask = <0x06>; }; @@ -208,7 +207,6 @@ reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy2clk"; - status = "ok"; csr-offset = <0x4>; csr-mask = <0x3a>; enable-offset = <0x0>; @@ -222,7 +220,6 @@ reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy3clk"; - status = "ok"; csr-offset = <0x4>; csr-mask = <0x3a>; enable-offset = <0x0>; -- 1.9.1