Comment 39 for bug 605042

Jeremy Kerr (jk-ozlabs) wrote :

Looks like I can trip this with any glibc version, using the attached testcase.

Basically, this does an anoymous mmap, then a cacheflush on the address returned from the mmap. We get an oops from the cacheflush on the actual coprocessor instruction:

 mcr p15, 0, r0, c7, c11, 1

- r0 is the start address given to cacheflush, and will be the address which we see the invalid paging operation on.

I'm unsure why this instruction is generating an access to this address.