From 705b0e8e90dd93f25fe42bb6ecc829630fabe150 Mon Sep 17 00:00:00 2001 From: Sebastian Hense Date: Fri, 24 Apr 2020 17:17:36 +0200 Subject: [PATCH] net/mlx5: fix endianness handling in pedit mask The mask value is provided as 64 bit and has to be casted in either 32 or 16 bit. On big endian systems the wrong half was casted which resulted in an all zero mask. Signed-off-by: Sebastian Hense --- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c index 1f9107d83848..4c12837a04ee 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -2424,10 +2424,11 @@ static int offload_pedit_fields(struct pedit_headers_action *hdrs, field_bsize = f->size * BITS_PER_BYTE; if (field_bsize == 32) { - mask_be32 = *(__be32 *)&mask; + mask_be32 = (__be32)mask; mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32)); } else if (field_bsize == 16) { - mask_be16 = *(__be16 *)&mask; + mask_be32 = (__be32)mask; + mask_be16 = *(__be16 *)&mask_be32; mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16)); } -- 2.21.1 (Apple Git-122.3)