Framework for Verilog RTL synthesis

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
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 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.