Binary package “verilator” in ubuntu bionic
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
It is designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to generate executable models
of CPUs for embedded software design teams.
Source package
Published versions
- verilator 3.916-1build1 in amd64 (Proposed)
- verilator 3.916-1build1 in amd64 (Release)
- verilator 3.916-1build1 in arm64 (Proposed)
- verilator 3.916-1build1 in arm64 (Release)
- verilator 3.916-1build1 in armhf (Proposed)
- verilator 3.916-1build1 in armhf (Release)
- verilator 3.916-1build1 in i386 (Proposed)
- verilator 3.916-1build1 in i386 (Release)
- verilator 3.916-1build1 in ppc64el (Proposed)
- verilator 3.916-1build1 in ppc64el (Release)
- verilator 3.916-1build1 in s390x (Proposed)
- verilator 3.916-1build1 in s390x (Release)